GATING OF A MESH CLOCK SIGNAL IN A PROCESSOR

Abstract

In an embodiment, a processor may include a mesh network and a clock regulation circuit. The mesh network may include multiple mesh stops to operate based on a mesh clock signal. Each mesh stop may include a bandwidth counter to transmit a bandwidth count in response to a pulse of a synchronization signal. The clock regulation circuit may be to: receive a plurality of bandwidth counts from the plurality of mesh stops; aggregate the plurality of bandwidth counts to obtain an aggregated bandwidth value; determine a cycle stealing value based at least on a comparison of the aggregated bandwidth value to at least one threshold value; and gate the mesh clock signal based on the determined cycle stealing value. Other embodiments are described and claimed.

IPC Classes  ?

• G06F 1/12 - Synchronisation of different clock signals
• G06F 1/324 - Power saving characterised by the action undertaken by lowering clock frequency