SCALABLE ADDRESS DECODING SCHEME FOR CXL TYPE-2 DEVICES WITH PROGRAMMABLE INTERLEAVE GRANULARITY
| Register | USPTO Patent |
|---|---|
| Application Number | 17478828 |
| Status | Pending |
| Filing Date | 2021-09-17 |
| First Publication Date | 2023-03-23 |
| Publication Date | 2023-03-23 |
| Owner | Intel Corporation (USA) |
| Inventor |
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Abstract
Methods and apparatus relating to a scalable address decoding scheme for Compute Express Link™ or CXL™ Type-2 devices with programmable interleave granularity are described. In an embodiment, configurator logic circuitry determines an interleave granularity and an address range size for a plurality of devices coupled to a socket of a processor. A single System Address Decoder (SAD) rule for two or more of the plurality of the devices coupled to the socket of the processor is stored in memory. A memory access transaction directed at a first device from the plurality of devices is routed to the first device in accordance with the SAD rule. Other embodiments are also disclosed and claimed.IPC Classes ?
- G06F 13/38 - Information transfer, e.g. on bus
- G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
- G06F 13/40 - Bus structure
- G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
- G06F 9/46 - Multiprogramming arrangements