Register USPTO Patent
Application Number 17479369
Status Pending
Filing Date 2021-09-20
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
  • Kanaoka, Yosuke
  • Mcree, Robin
  • Duan, Gang
  • Medhi, Gautam
  • Chen, Huang-Ta


A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

IPC Classes  ?

  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns