MEMORY SIDE PREFETCH ARCHITECTURE FOR IMPROVED MEMORY BANDWIDTH

Register USPTO Patent
Application Number 17479582
Status Pending
Filing Date 2021-09-20
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor
  • Moga, Adrian
  • Echeruo, Ugonna
  • Roytman, Eduard
  • Sistla, Krishnakanth
  • Nuzman, Joseph
  • Ganesh, Brinda
  • Chinthamani, Meenakshisundaram
  • Liu, Yen-Cheng
  • Muralidhara, Sai Prashanth
  • Kozhikkottu, Vivek
  • Alam, Hanna
  • Srirangam, Narasimha Sridhar

Abstract

Methods and apparatus relating to memory side prefetch architecture for improved memory bandwidth are described. In an embodiment, logic circuitry transmits a Direct Memory Controller Prefetch (DMCP) request to cause a prefetch of data from memory. A memory controller receives the DMCP request and issues a plurality of read operations to the memory in response to the DMCP request. Data read from the memory is stored in a storage structure in response to the plurality of read operations. Other embodiments are also disclosed and claimed.

IPC Classes  ?

  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal