IMMEDIATE OFFSET OF LOAD STORE AND ATOMIC INSTRUCTIONS

Register USPTO Patent
Application Number 17480528
Status Pending
Filing Date 2021-09-21
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor
  • Ray, Joydeep
  • Appu, Abhishek R.
  • Bauer, Timothy R.
  • Valerio, James
  • Chen, Weiyu
  • Maiyuran, Subramaniam
  • Surti, Prasoonkumar
  • Vaidyanathan, Karthik
  • Benthin, Carsten
  • Woop, Sven
  • Chen, Jiasheng

Abstract

One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus