MULTI LAYER PACKAGE SUBSTRATE HAVING DIFFERENT DIELECTRIC MATERIALS FOR METAL LAYERS WITH DIFFERENT CIRCUIT STRUCTURES
|First Publication Date||2023-03-23|
|Owner||Intel Corporation (USA)|
AbstractAn apparatus is described. The apparatus includes a semiconductor chip package substrate having alternating metal and dielectric layers. First and second ones of the dielectric layers that are directly above and directly below a first of the metal layers that is patterned to have supply and/or reference voltage structures have respectively higher dielectric constant (Dk) and higher dissipation factor (Df) than third and fourth ones of the dielectric layers that are directly above and directly below a second of the metal layers that is patterned to have signal wires that are to transport signals having a pulse width of 1 ns or less.
IPC Classes ?
- H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
- H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
- H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates