GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
|First Publication Date||2023-03-23|
|Owner||Intel Corporation (USA)|
AbstractAn apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.
IPC Classes ?
- G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
- G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
- G06F 12/02 - Addressing or allocation; Relocation
- G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining