INTEGRATED THERMOELECTRIC DEVICE TO MITIGATE INTEGRATED CIRCUIT HOT SPOTS

Register USPTO Patent
Application Number 17481501
Status Pending
Filing Date 2021-09-22
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner INTEL CORPORATION (USA)
Inventor
  • Sato, Noriyuki
  • Yoo, Hui Jae
  • Lin, Kevin L.
  • Le, Van H.
  • Sharma, Abhishek Anil

Abstract

Techniques are provided for forming one or more thermoelectric devices integrated within a substrate of an integrated circuit. Backside substrate processing may be used to form adjacent portions of the substrate that are doped with alternating dopant types (e.g., n-type dopants alternating with p-type dopants). The substrate can then be etched to form pillars of the various n-type and p-type portions. Adjacent pillars of opposite dopant type can be electrically connected together via a conductive layer. Additionally, the top portions of adjacent pillars are connected together, and the bottom portions of a next pair of adjacent pillars being coupled together, in a repeating pattern to ensure that current flows through the length of each of the doped pillars. The flow of current through alternating n-type and p-type doped material creates a heat flux that transfers heat from one end of the integrated thermoelectric device to the other end.

IPC Classes  ?

  • H01L 35/32 - SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR - Details thereof operating with Peltier or Seebeck effect only characterised by the structure or configuration of the cell or thermocouple forming the device
  • H01L 27/16 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including thermomagnetic components