Register USPTO Patent
Application Number 17482166
Status Pending
Filing Date 2021-09-22
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
  • Chen, Jiasheng
  • Rhee, Changwon
  • Ganapathy, Sabareesh
  • Henry, Gregory
  • Fu, Fangwen


Emulating floating point calculation using lower precision format calculations is described. An example of a processor includes a floating point unit (FPU) to provide a native floating point operation in a first precision format; and systolic array hardware including multiple data processing units, wherein the processor is to receive data for performance of a matrix multiplication operation in the first precision format; enable an emulated floating point multiplication operation using one or more values with a second precision format, the second precision format having a lower precision than the first precision format, the emulated floating point multiplication including operation of the systolic array hardware; and generate an emulated result for the matrix multiplication operation.

IPC Classes  ?

  • G06F 7/487 - Multiplying; Dividing
  • G06F 7/485 - Adding; Subtracting
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 17/16 - Matrix or vector computation
  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors