Register USPTO Patent
Application Number 17482228
Status Pending
Filing Date 2021-09-22
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
  • Haran, Mohit K.
  • Hasan, Mohammad
  • Ghani, Tahir
  • Murthy, Anand S.


Integrated circuit structures having a dielectric gate wall and a dielectric gate plug, and methods of fabricating integrated circuit structures having a dielectric gate wall and a dielectric gate plug, are described. For example, an integrated circuit structure includes a sub-fin having a portion protruding above a shallow trench isolation (STI) structure. A plurality of horizontally stacked nanowires is over the sub-fin. A gate dielectric material layer is over the protruding portion of the sub-fin, over the STI structure, and surrounding the horizontally stacked nanowires. A conductive gate layer is over the gate dielectric material layer. A conductive gate fill material is over the conductive gate layer. A dielectric gate wall is laterally spaced apart from the sub-fin and the plurality of horizontally stacked nanowires, the dielectric gate wall on the STI structure. A dielectric gate plug is on the dielectric gate wall.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate