FIRST LEVEL INTERCONNECT UNDER BUMP METALLIZATIONS FOR FINE PITCH HETEROGENEOUS APPLICATIONS
| Register | USPTO Patent |
|---|---|
| Application Number | 17482275 |
| Status | Pending |
| Filing Date | 2021-09-22 |
| First Publication Date | 2023-03-23 |
| Publication Date | 2023-03-23 |
| Owner | Intel Corporation (USA) |
| Inventor |
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Abstract
Embodiments disclosed herein include electronic packages with first level interconnects that comprise a first layer. In an embodiment, the electronic package comprises a package substrate and a pad on the package substrate. In an embodiment, the pad comprises copper. In an embodiment, a first layer is over the pad. In an embodiment, the first layer comprises iron. In an embodiment, a solder is over the first layer, and a die is coupled to the package substrate by the solder.IPC Classes ?
- H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
- H01L 23/498 - Leads on insulating substrates
- H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L 23/528 - Layout of the interconnection structure