Register USPTO Patent
Application Number 17482578
Status Pending
Filing Date 2021-09-23
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor Waller, William K.


In one embodiment, a non-volatile memory apparatus includes memory tiles comprising a set of main memory tiles in rows and columns, a set of row termination tiles at the ends of the rows, and a set of column termination tiles at the ends of the columns. Each memory tile includes a plurality of decks, with each deck comprising bitlines, wordlines orthogonal to the bitlines, and memory cells between overlapping areas of the bitlines and the wordlines. The bitlines/wordlines include a set of bitlines/wordlines of a first layer that traverse row/column termination tiles and main memory tiles adjacent the row/column termination tiles, with each bitline/wordline of the set of bitlines/wordlines connected to another bitline of a second layer in the termination tile.

IPC Classes  ?

  • G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C 8/10 - Decoders