ELECTRONIC PACKAGING ARCHITECTURE WITH CUSTOMIZED VARIABLE METAL THICKNESS ON SAME BUILDUP LAYER

Register USPTO Patent
Application Number 17482852
Status Pending
Filing Date 2021-09-23
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor
  • Ecton, Jeremy D.
  • Darmawikarta, Kristof
  • Nad, Suddhasattwa
  • Ojeda, Oscar
  • Nie, Bai
  • Marin, Brandon C.
  • Duan, Gang
  • Vehonsky, Jacob
  • Ozkan, Onur
  • Haehn, Nicholas S.

Abstract

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices