LOW TEMPERATURE, HIGH GERMANIUM, HIGH BORON SIGE:B PEPI WITH A SILICON RICH CAPPING LAYER FOR ULTRA-LOW PMOS CONTACT RESISTIVITY AND THERMAL STABILITY
|First Publication Date||2023-03-23|
|Owner||Intel Corporation (USA)|
AbstractGate-all-around integrated circuit structures having confined epitaxial source or drain structures, are described. For example, an integrated circuit structure includes a plurality of nanowires above a sub-fin. A gate stack is over the plurality of nanowires and the sub-fin. Epitaxial source or drain structures are on opposite ends of the plurality of nanowires. The epitaxial source or drain structures comprise i) a first PMOS epitaxial (pEPI) region of germanium and boron, ii) a second pEPI region of silicon, germanium and boron on the first pEPI region at a contact location, iii) a capping layer comprising silicon over the second pEPI region. A conductive contact material comprising titanium is on the capping layer.
IPC Classes ?
- H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
- H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L 29/66 - Types of semiconductor device