SCALABLE EOS AND AGING TOLERANT LEVEL SHIFTER FOR A HIGH VOLTAGE DESIGN FOR THIN GATE TECHNOLOGY
| Register | USPTO Patent |
|---|---|
| Application Number | 17482912 |
| Status | Pending |
| Filing Date | 2021-09-23 |
| First Publication Date | 2023-03-23 |
| Publication Date | 2023-03-23 |
| Owner | Intel Corporation (USA) |
| Inventor |
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Abstract
A level shifter circuit, comprising one or more thin gate transistors having source and drain terminals coupled, respectively, to a power supply node and a reference node, where the one or more thin gate transistors have an electrical over stress (EOS) threshold voltage that is lower than a voltage of the power supply applied across two terminals of the one or more thin gate transistors. The circuit further includes a PFET pulldown circuit coupled to an EOS protection circuit to limit the voltage difference across at least two terminals of the one or more thin gate transistors to a voltage below the EOS threshold voltage based on the threshold voltage the PFET.IPC Classes ?
- H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only