CORE-BASED SPECULATIVE PAGE FAULT LIST

Register USPTO Patent
Application Number 17482944
Status Pending
Filing Date 2021-09-23
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor
  • Opferman, Toby
  • Chynoweth, Michael W.
  • Chabukswar, Rajshree A.
  • Bahirji, Vijay C.

Abstract

An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode