Time encoded data communication protocol, apparatus and method for generating and receiving a data signal

Register USPTO Patent
Application Number 17810845
Status Pending
Filing Date 2022-07-06
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
  • Banin, Elan
  • Mann, Eytan
  • Banin, Rotem
  • Gernizky, Ronen
  • Degani, Ofir
  • Kushnir, Igal
  • Porat, Shahar
  • Rubin, Amir
  • Volokitin, Vladimir
  • Kashani, Elinor
  • Felsenstein, Dmitry
  • Eshkoli, Ayal
  • Davidson, Tal
  • Ooi, Eng Hun
  • Tsfati, Yossi
  • Shimon, Ran


An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

IPC Classes  ?

  • H04B 1/04 - Circuits
  • H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop