CO-PACKAGING WITH SILICON PHOTONICS HYBRID PLANAR LIGHTWAVE CIRCUIT

Register USPTO Patent
Application Number 17992670
Status Pending
Filing Date 2022-11-22
First Publication Date 2023-03-23
Publication Date 2023-03-23
Owner Intel Corporation (USA)
Inventor
  • Kim, Sang Yup
  • Yim, Myung Jin
  • Kim, Woosung

Abstract

An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

IPC Classes  ?

  • G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • G02B 6/42 - Coupling light guides with opto-electronic elements