Register WIPO Patent
Application Number US2021050499
Publication Number 2023/043439
Status In Force
Filing Date 2021-09-15
Publication Date 2023-03-23
  • Ghosh, Kausik
  • Bose, Pratim
  • Hodigere, Arun Venkatasubbaiah


An apparatus for processing data is provided comprising persistent memory circuitry, non-persistent memory circuitry and memory controller circuitry. The memory controller circuitry provides two or more memory sub-channels and each memory sub-channel is for routing of memory access transactions for at least one of the persistent memory circuitry and the non-persistent memory circuitry. The memory controller circuitry has channel selection circuitry to detect when there are no non-persistent memory transactions on one of the two or more memory sub-channels and responsive to the detection, is to route any persistent memory transactions to a different one of the two or more memory sub-channels. A memory controller apparatus, a persistent memory Dual In-line Memory Module, a method and computer program are also provided.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 1/3225 - Monitoring of peripheral devices of memory devices
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/46 - Multiprogramming arrangements
  • G11C 5/04 - Supports for storage elements; Mounting or fixing of storage elements on such supports