09 - Scientific and electric apparatus and instruments
40 - Treatment of materials; recycling, air and water treatment,
42 - Scientific, technological and industrial services, research and design
Goods & Services
Semiconductors; semiconductor component; semiconductor
memories; semiconductor wafers; integrated circuits;
multiprocessor chips; dynamic random access memory (DRAM);
solid state drives; blank flash memory cards; blank USB
flash drives; processors [central processing units]; image
sensors for video cameras; image sensors for photographic
devices; image sensors for smartphone cameras; image sensors
for tablet computer cameras; computer software for use in
semiconductor design; computer software for use in designing
and manufacturing of semiconductor systems and for designing
of semiconductor cell library and integrated circuit;
computer software for use in providing information on
semiconductor manufacturing process; computer software for
use to improve accuracy and efficiency in the field of
semiconductor manufacturing; computer software for use in
processing semiconductor wafers. Semiconductor and integrated circuit foundry; custom
manufacturing and assembling services relating to
semiconductor parts and integrated circuits; processing of
semiconductors; processing of parts for semiconductor
manufacturing. Product research, custom design and testing for new product
development regarding semiconductors; product research,
custom design and testing for new product development
regarding semiconductor cell libraries; design of
semiconductors or integrated circuits; design of
semiconductor chips; technology consultation services
regarding semiconductors; technology consultation services
regarding integrated circuits; software as a service [SaaS]
featuring software for use in semiconductor design; software
as a service [SaaS] featuring software for use in integrated
circuit design; design of semiconductor manufacturing
machines.
09 - Scientific and electric apparatus and instruments
Goods & Services
Smartphones; hinges in the nature of a component of
smartphones; folding hinges for smartphones; flexible hinges
to enable smartphones to reorient the content on the
smartphone screen when the phone is partially folded or
unfolded.
4.
COMPOSITE CATHODE ACTIVE MATERIAL, CATHODE AND LITHIUM BATTERY EACH CONTAINING COMPOSITE CATHODE ACTIVE MATERIAL, AND PREPARATION METHOD OF CATHODE ACTIVE MATERIAL
A composite cathode active material includes: a core including a plurality of primary particles; and a shell on the core, wherein the primary particles include a first lithium transition metal oxide comprising nickel, the shell includes a first layer and a second layer on the first layer, the first layer includes a first composition containing a first metal, the second layer includes a second composition containing phosphorus, and the first metal includes at least one or more metal, other than nickel, belonging to any of Groups 2 to 5 and Groups 7 to 15 of the Periodic Table of the Elements. Also a cathode, and a lithium battery each including the composite cathode active material, and a method of preparing the composite cathode active material.
H01M 4/525 - Selection of substances as active materials, active masses, active liquids of inorganic oxides or hydroxides of nickel, cobalt or iron of mixed oxides or hydroxides containing iron, cobalt or nickel for inserting or intercalating light metals, e.g. LiNiO2, LiCoO2 or LiCoOxFy
H01M 4/62 - Selection of inactive substances as ingredients for active masses, e.g. binders, fillers
5.
ELECTRONIC DEVICE PROVIDING RESPONSE TO VOICE INPUT, AND METHOD AND COMPUTER READABLE MEDIUM THEREOF
An electronic apparatus, method, and computer readable medium are provided. The electronic apparatus includes a communicator, and a controller. The controller, based on a first voice input being received, controls the communicator to receive data including first response information corresponding to the first voice input from a server, and outputs the first response information on a display, and based on a second voice input being received, controls the communicator to receive data including second response information corresponding to the second voice input from the server, and outputs the second response information on the display. Based on whether the second voice input is received within a predetermined time from a time corresponding to the output of the first response information, whether a use of utterance history information is identified, and the second response information is displayed differently based on whether the second voice input is received within the predetermined time.
A wearable electronic device includes a display, and at least one processor connected to the display, where the at least one processor is configured to obtain a first space necessary for a motion of a user corresponding to a motion of an avatar, the motion of the avatar being performed in a virtual space of virtual reality (VR) content displayed through the display, obtain a second space for safely performing the motion of the user, set a scale value, based on the first space and the second space, and based on obtaining the motion of the user, determine, using the set scale value, a size of the motion of the avatar, the motion of the avatar being performed by the motion of the user.
Integrated circuit devices may include a first upper channel region on a substrate, a first lower channel region between the substrate and the first upper channel region, a first intergate insulator that is between the first lower channel region and the first upper channel region and includes a lower portion and an upper portion, an upper gate electrode, and a lower gate electrode between the substrate and the upper gate electrode. The first upper channel region and the upper portion of the first intergate insulator may be in the upper gate electrode. The first lower channel region and the lower portion of the first intergate insulator are in the lower gate electrode.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The disclosure relates to a method for processing a communication path in a portable communication device, which includes: identifying whether at least some of a plurality of active elements included in a communication circuit disposed between an antenna and a communication processor are in an abnormal state and, based on an abnormal state of a first active element supporting delivery of a signal of a first frequency band among the plurality of active elements being detected, controlling the portable communication device to deliver the signal of the first frequency band based on a second active element different form the first active element among the plurality of active element, and a portable communication device supporting the same.
H04B 7/08 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
Methods and apparatuses for facilitating broadcast target wake time (TWT) negotiation on one link between multi-link devices (MLDs) in a wireless local area network to establish broadcast TWT schedules on other links between the same MLDs. A non-access point (AP) MLD comprises a processor and stations (STAs), each comprising a transceiver configured to form a link with a corresponding AP of an AP MLD. The processor is operably coupled to the STAs and configured to generate or receive a first message for a broadcast TWT negotiation, wherein the first message indicates that the broadcast TWT negotiation is for a broadcast TWT schedule on at least one first link of the links. The transceiver of a first of the STAs is further configured to transmit or receive the first message to or from the AP MLD over a second of the links.
A wafer dicing method includes preparing a wafer that includes a plurality of device forming regions and a scribe lane region that separates the plurality of device forming regions, forming a plurality of semiconductor devices in the plurality of device forming regions of the wafer, respectively, forming a plurality of inner cracks in the scribe lane region of the wafer by repeatedly irradiating a multiple pulse laser beam that includes a plurality of sub-laser beams along the scribe lane region, wherein the plurality of sub-laser beams have decreasing peak powers, and separating the plurality of semiconductor devices from each other along the plurality of inner cracks.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
B23K 26/06 - Shaping the laser beam, e.g. by masks or multi-focusing
B23K 26/0622 - Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses
B23K 26/53 - Working by transmitting the laser beam through or within the workpiece for modifying or reforming the material inside the workpiece, e.g. for producing break initiation cracks
A semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes a first UBM layer including a first metal material or an alloy of the first metal material; and a second UBM layer between one of the bumps and the first UBM layer and including a second metal material.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
12.
RECYCLED POLYPROPYLENE COMPOSITE RESIN COMPOSITION AND WASHING MACHINE COMPRISING THE SAME
Disclosed herein are a recycled polypropylene composite material resin composition and a washing machine including the same. A glass fiber-reinforced recycled polypropylene resin composition includes, in weight percent of the glass fiber-reinforced recycle polypropylene resin composition, about 10 to 30% of waste glass fiber mat-reinforced thermoplastic (GMT), about 35 to 47% of a homo-polypropylene base resin, about 30 to 45% of long glass fiber-reinforced polypropylene, and about 0.5 to 3.0% of a compatibilizer, and a weight average molecular weight of the composition may be about 250,000 g/mol or more.
A semiconductor package includes a redistribution structure in which redistribution layers and insulating layers are alternately stacked. A semiconductor chip is electrically connected to the redistribution layers, and bumps are electrically connected to the redistribution layers and arranged on one surface of the redistribution structure. The redistribution layers include pads arranged to face the bumps, and each of the pads includes a first pad portion offset from a center of each of the pads in a first direction, a second pad portion offset from the center of each of the pads in a second direction, and a connection portion connecting the first and second pad portions. The connection portion includes a protruding portion that defines a first recessed region recessed adjacent to the first pad portion and a second recessed region recessed adjacent to the second pad portion.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
14.
DEVICE, OPERATING METHOD, MEMORY DEVICE, AND CXL MEMORY EXPANSION DEVICE
A device, an operating method of a memory controller, a memory device, and a compute express link (CXL) memory expansion device all for managing a row hammer are provided. The device includes a volatile memory and a memory controller that is configured to detect, based on input row addresses, a pattern size of a row hammer attack pattern and a row distribution of row hammer addresses, to determine, according to a type of the row distribution, whether to perform refresh management, and for every L access corresponding to the pattern size, to provide, to the volatile memory, a refresh management command and a target row address, where L is an integer greater than or equal to 1.
An electronic device is disclosed. An electronic device may include: a foldable housing including a hinge, a first housing connected to the hinge and including a first surface oriented in a first direction and a second surface oriented in a second direction opposite the first direction, a second housing connected to the hinge and including a third surface oriented in a third direction and a fourth surface oriented in a fourth direction opposite the third direction, wherein the second housing is configured to be folded on the first housing about the hinge, and side surfaces surrounding at least a part of a space between the first surface and the second surface and at least a part of a space between the third surface and the fourth surface; and a display having ductility and extending from the first surface to the third surface to configure the first surface and the third surface, wherein the foldable housing is disposed along an edge of the display and includes bezels extending from respective side surfaces to an active area of the display, and wherein the bezels include, in an area configuring the first surface and the third surface of the foldable housing, extensions spaced apart from edge portions of the display, and support portions disposed between the edge of the display and the extensions to be in contact with the edge portions of the display.
The disclosure relates to a 5G or 6G communication system for supporting higher data rates. The disclosure discloses a method and an apparatus capable of optimizing early EPS fallback. A method performed by a terminal in a wireless communication system includes receiving, from a base station of a first RAT, a message to command an inter-RAT HO, the message including information indicating that the inter-RAT HO is triggered by EPS fallback for IMS voice; performing the inter-RAT HO based on the message; based on a failure of the inter-RAT HO, identifying whether there is a suitable cell of a second RAT for selection; in case that there is no suitable cell of the second RAT, selecting an acceptable cell of the second RAT based on the IMS voice being for an emergency service; and logging a time until the terminal accesses the acceptable cell of the second RAT.
A semiconductor device includes an active pattern on a substrate with first and second regions; first and second source/drain regions on the first and second regions; first and second source/drain contacts on the first and second source/drain regions; and a separation structure intersecting the active pattern between the first and second source/drain contacts, and extending into the active pattern between the first and second source/drain regions, wherein an upper surface of the second source/drain contact is higher than an upper surface of the first source/drain contact, and wherein the separation structure has an asymmetrical structure having an upper surface of a first portion adjacent to the first source/drain contact higher than an upper surface of a second portion adjacent to the second source/drain contact.
Disclosed is an electronic apparatus including a display, a memory configured to store at least one instruction, and at least one processor configured to execute the at least one instruction stored in the memory to obtain input documents, recognize, an element comprising at least one of a character, an image, or a combination of the character and the image; classify a type of each of the input documents based on a kind of the recognized element, and obtain calibration documents by arranging the recognized elements in a row based on the classified type of each of the input documents; and control the display to display the obtained calibration documents.
G09G 5/34 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
A semiconductor device includes a peripheral circuit structure including a plurality of circuit areas, a cell array structure including a pair of memory cell blocks overlapping the peripheral circuit structure in a first direction and spaced apart in a second direction, perpendicular to the first direction, with a peripheral circuit connection area therebetween, a first circuit area of the plurality of circuit areas that overlaps the peripheral circuit connection area in the first direction, and at least one contact plug extending in the first direction from the peripheral circuit connection area, and including a first end portion configured to connect to at least one circuit included in the first circuit area and facing the first circuit area and a second end portion configured to connect to an external connection terminal.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Provided is a diagnostic robot including: a communication interface; and at least one processor configured to: control the communication interface to search for at least one candidate electronic device, select a target electronic device from among the at least one candidate electronic device, and identify a component of the target electronic device on which to perform a fault diagnosis, control the communication interface to transmit information associated with a diagnosis range to the target electronic device, obtain first diagnostic data by performing a first fault diagnosis on a component of the diagnostic robot, control the communication interface to receive, from the target electronic device, second diagnostic data generated from a second fault diagnosis performed on the component of the target electronic device while the target electronic device is positioned at a diagnosis area within the diagnosis range, and identify whether there is an abnormality in the component of the target electronic device based on the first diagnostic data and the second diagnostic data.
In some embodiments, an integrated circuit device includes a substrate, a fin-type active region on the substrate that extends in a first direction, a plurality of semiconductor patterns spaced apart from an upper surface of the fin-type active region and include a channel region, a gate electrode, and a gate cut insulating pattern. The gate electrode extends in a second direction on the fin-type active region and is disposed between the plurality of semiconductor patterns. The gate electrode includes a first sidewall extending in the second direction and a second sidewall extending in the first direction. The gate cut insulating pattern is on a second sidewall of the gate electrode. An upper portion of the gate cut insulating pattern is wider in the second direction than a lower portion of the gate cut insulating pattern. A portion of a sidewall of the gate cut insulating pattern is curved.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A method and electronic device for executing application concurrently with other devices are provided. An address of an external electronic device and a location of an application is obtained. A connection is established with a device using a short-range communication protocol. The application is obtained and executed in conjunction with the device.
H04M 1/72412 - User interfaces specially adapted for cordless or mobile telephones with means for local support of applications that increase the functionality by interfacing with external accessories using two-way short-range wireless interfaces
H04B 5/00 - Near-field transmission systems, e.g. inductive loop type
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A semiconductor device may include a substrate, a bitline extending in a first direction on the substrate, and an active pattern on the bitline. The semiconductor device may include a back gate electrode extending beside one side of the active pattern in a second direction perpendicular to the first direction across the bitline, and a wordline extending in the second direction beside the other side of the active pattern. A length of the active pattern in the second direction may be greater than a length of the bitline in the second direction.
Disclosed is an operating method of a storage controller communicating with a host and memory regions, which includes receiving a write request for a first memory region of the memory regions from the host, determining the first memory region as unavailable, based on a status information set, generating redirection information indicating that a second memory region of the memory regions is selected instead of the first memory region, performing a write operation in the second memory region based on the redirection information, updating status information of the second memory region in the status information set based on the write operation, outputting redirection result information indicating that write data of the write request are processed in the second memory region, to the host, and receiving a read request corresponding to the write data and including information of the second memory region from the host.
A driving robot includes: a camera including a depth camera; and at least one processor configured to: control the camera to acquire depth data in one or more areas where the driving robot moves, identify, from the acquired depth data, a plurality of scan data sets corresponding to a plurality of predetermined height levels, identify, based on the plurality of scan data sets, a plurality of feature scores corresponding to the plurality of scan data sets, and generate at least one area map corresponding to at least one scan data set among the plurality of scan data sets, wherein a feature score, among the plurality of feature scores, corresponding to the at least one scan data set is greater than or equal to a predetermined critical value.
A memory core circuit includes: (i) a memory cell array having sub cell arrays therein, and (ii) a core control circuit having sub peripheral circuits therein, such that each sub peripheral circuit extends underneath a corresponding sub cell array. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. Each sub peripheral circuit includes sub wordline drivers configured to drive the wordlines, bitline sense amplifiers configured to sense voltages of the bitlines, a row decoding circuit configured to control the sub wordline drivers to select one of the wordlines, a power circuit configured to supply power to each sub peripheral circuit, and a control circuit configured to control operation of each sub peripheral circuit. By using a CoP structure that efficiently provides the core control circuit, the size of the memory core circuit may be reduced and a design margin may be enhanced.
Provided is an image processing method according to an embodiment, which includes: obtaining a label of a first image by inputting the first image to a recognition model; obtaining reference style data for a target reference image to which a visual sentiment label is assigned, the visual sentiment label being the same as the obtained label from among visual sentiment labels pre-assigned to reference images; generating second style data based on first style data for the first image and the obtained reference style data; and generating a second image based on the generated second style data.
An integrated circuit device includes a first chip and a second chip. The first chip includes a first substrate including a through-via region, a prohibition region, and a device region, the prohibition region surrounding the through-via region in a plan view. The first chip further includes a through-via penetrating the first substrate in the through-via region, and a power gating cell disposed in the prohibition region. The second chip includes a second substrate, and a plurality of circuit blocks configured to receive power and/or signals through the through-via.
In various embodiments, a method performed by a mobility management device, includes obtaining mobility information of a user equipment (UE). The method includes generating a predicted tracking area list for the UE based on the mobility information. The method includes transmitting, to the UE, a message including the predicted tracking area list to initiate a registration procedure based on the UE being out of a range of a plurality of tracking areas of the predicted tracking area list. The method includes based on identifying downlink data for the UE, performing a paging procedure in each of cells in the predicted tracking area list.
An image sensor includes a pixel array including a plurality of pixels operating in a plurality of modes, a readout circuit configured to receive a pixel signal corresponding to each of the plurality of modes from each of the pixels and generate a pixel value that is a digital signal from the pixel signal, and a signal processor configured to determine whether a target pixel value is a black spot generation value for each of the pixels based on at least one of comparison pixel values of each comparison mode among a plurality of comparison modes having a smaller output gain than a target mode corresponding to the target pixel value, and correct the target pixel value when the target pixel value is the black spot generation value.
A method performed by a multi-subscriber identity module (MUSIM) user equipment (UE) for continuing operation of the MUSIM UE in a first mode, the MUSIM UE including a first SIM and a second SIM, and the method including transmitting, by the MUSIM UE, an uplink signalling message in response to determining a trigger condition has been satisfied, the uplink signalling message including one of compatible band information for the first SIM and the SIM, or one or more other stacks serving band information associated with the second SIM, receiving, by the MUSIM UE from a network, a radio resource control (RRC) reconfiguration signalling message for performing at least one activity at the first SIM in response to the transmitting the uplink signalling message, and performing, by the MUSIM UE, the at least one activity based on the RRC reconfiguration signalling message.
An electronic device is provided. The electronic device includes a sensor module, at least one display, a memory, and at least one processor. The at least one processor displays a plurality of components through the display in a first mode of the electronic device, determines a pivot region including a plurality of grids, detects a change to a second mode of the electronic device based on sensing information sensed through the sensor module, and maintains a layout of components included in the pivot region and display the plurality of components in the second mode.
G06F 9/451 - Execution arrangements for user interfaces
G06F 1/16 - Constructional details or arrangements
G06F 3/0346 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of the device orientation or free movement in a 3D space, e.g. 3D mice, 6-DOF [six degrees of freedom] pointers using gyroscopes, accelerometers or tilt-sensors
H04M 1/02 - Constructional features of telephone sets
33.
METHOD AND APPARATUS FOR DETERMINING PREAMBLES AND RACH OCCASIONS FOR 2 STEP RANDOM ACCESS
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure provides method and apparatus of determining preamble and RACH occasions for 2-step random access.
Method and apparatuses for channel state information (CSI) feedback in cellular systems. A method for operating a user equipment (UE) to report CSI includes transmitting first information related to a capability of the UE to support machine learning (ML) based CSI reporting and second information related to a selection of a ML model for CSI reporting. The method further includes receiving third information related to configuring a first ML model for determining the CSI, fourth information related to processing a ML model output, fifth information related to reception of CSI reference signals (CSI-RS s) on a cell, and the CSI-RSs based on the fifth information. The method further includes determining, based on the third and fourth information and the reception of the CSI-RSs, a CSI report using the first ML model and transmitting a channel with the CSI report.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A gas treatment method, including: treating an exhaust gas discharged from a semiconductor process chamber using a gas treatment system; and discharging the treated exhaust gas, wherein the treating of the exhaust gas includes: operating a first thermal oxidizer to treat the exhaust gas discharged from the semiconductor process chamber, the first thermal oxidizer being connected to the semiconductor process chamber and allowing the treated exhaust gas to pass through a plasma processing apparatus connected to the first thermal oxidizer; stopping the operation of the first thermal oxidizer to perform maintenance on the first thermal oxidizer; and wherein the stopping the operation of the first thermal oxidizer comprises: performing maintenance on the first thermal oxidizer; and operating the plasma processing apparatus to treat the exhaust gas discharged from the semiconductor process chamber
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
An operating method performed by a user equipment (UE) in a wireless communication system according to some embodiments of the present disclosure may include: generating a source link for transmitting and receiving data to and from a source base station; receiving, from the source base station, a radio resource control (RRC) message including configuration information for handover to a target base station; starting a timer, in response to the reception of the RRC message; transmitting, to the target base station, a message for handover to the target base station while the timer is running; and determining, in a case where the handover to the target base station fails up until the timer expires, whether to trigger RRC re-establishment, based on a state of the source link.
An image sensor, a mobile device, and an image sensor operation method for reducing a data transmission latency are disclosed. The image sensor includes an interface circuit configured to receive compressed data from an external processor, at least one memory configured to store the compressed data, and a control logic circuit configured to decompress the compressed data based on an initialized first clock rate, wherein, after the control logic circuit decompresses the compressed data, the first clock rate is reset to a second clock rate.
H04N 25/76 - Addressed sensors, e.g. MOS or CMOS sensors
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 23/57 - Mechanical or electrical details of cameras or camera modules specially adapted for being embedded in other devices
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
38.
SEMICONDUCTOR MEMORY DEVICE AND MEMORY MODULE HAVING VARIOUS OPERATION MODES
A semiconductor memory device includes a receiving circuit, a multiplexing circuit, a decoding circuit and a memory cell array. The receiving circuit receives a plurality of input command/address (CA) signals, and generates a plurality of CA signal groups based on the input CA signals and a clock signal. The multiplexing circuit operates in one of a first operation mode and a second operation mode based on a mode selection signal, outputs the plurality of CA signal groups as a plurality of selected CA signal groups in the first operation mode, and generates the plurality of selected CA signal groups by multiplexing the plurality of sub-CA signals included in the plurality of CA signal groups in the second operation mode. The decoding circuit generates a plurality of output CA signals based on the plurality of selected CA signal groups.
The present disclosure relates to a communication technique that merges IoT technology with a 5G communication system for supporting higher data transmission rates than 4G systems, and a system for same. The present disclosure may be applied to intelligent services (for example, smart homes, smart buildings, smart cities, smart cars or connected cars, healthcare, digital education, retail business, security and safety-related services, etc.) on the basis of 5G communication technology and IoT-related technology. In addition, the present disclosure relates to a method and device for transmitting a signal through a plurality of slots in a wireless communication system.
H04W 72/0446 - Resources in time domain, e.g. slots or frames
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
40.
METHOD FOR SUPPORTING ERASURE CODE DATA PROTECTION WITH EMBEDDED PCIE SWITCH INSIDE FPGA+SSD
A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
A semiconductor device includes a substrate. A plurality of horizontal structures is stacked on the substrate and spaced apart from each other. A plurality of vertical structures penetrates through the plurality of horizontal structures. Each of the plurality of vertical structures includes a vertical source line, a vertical bit line, a channel layer, and a dielectric layer. The channel layer is in direct contact with the vertical source line and the vertical bit line. The dielectric layer is disposed between the plurality of horizontal structures and the channel layer. Each of the plurality of horizontal structures includes a first conductive layer, a ferroelectric layer surrounding at least a portion of the first conductive layer, and a second conductive layer disposed between the ferroelectric layer and the dielectric layer.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
42.
PLASMA SHUTTER AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME
Provided is a substrate processing apparatus, including a process chamber, a plasma shutter configured ascend to close the process chamber, and an upper liner on the process chamber, wherein the process chamber includes a process space in which a substrate process is performed, and an insertion passage adjacent to the process space and connecting the process space to an outside of the process chamber, wherein the upper liner includes an extension liner, wherein the extension liner faces a connection inner surface that upwardly extends from an inner end of a passage ceiling forming the insertion passage, and wherein, in a state where the plasma shutter ascends to close the process space, an upper end of the plasma shutter is inserted between the connection inner surface and the extension liner.
An appliance is described. A write engine may process a write request from an application to write a first data into a memory. The write request may including the first data and an address. A compression engine may compress the first data to produce a first compressed data. A write module may store the first compressed data in the memory. The first data may be a first part of a page that may further include a second data as a second part. The first compressed data may be a first part of a compressed page that may further include a second compressed data as a second part.
A cooking apparatus includes a main body, and a cooking plate mounted on an upper surface of the main body to cook a cooking material. The cooking plate includes a base material, a diamond-like carbon (DLC) coating layer formed on an upper surface of the base material, to contact a cooking container when the cooking container is placed on the cooking plate, and an adhesive layer interposed between the base material and the DLC coating layer, and including at least one of Si and SiOx.
C03C 17/42 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions at least one coating of an organic material and at least one non-metal coating
Provided is a display apparatus including: a liquid crystal panel; a source driver configured to output a grayscale voltage to the liquid crystal panel; a timing controller configured to transmit a source control signal to the source driver; a scaler configured to transmit image data corresponding to content received from an external source to the timing controller; and a controller configured to adjust a driving scan rate of the liquid crystal panel to correspond to a set scan rate of the content, and control at least one of the scaler or the timing controller to adjust a data rate of an output signal based on the driving scan rate.
G09G 3/36 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source using liquid crystals
A semiconductor device includes a plurality of memory cells each including a cell transistor and a memcitor connected to the cell transistor, and the memcitor includes an information storage layer including a ferroelectric material, a first electrode and a second electrode connected to both ends of the information storage layer, a fixed layer stacked on the information storage layer and including a paraelectric material or an antiferroelectric material, and a third electrode connected to the fixed layer without contacting the information storage layer.
An audio signal processing method, an audio signal processing apparatus, a computer device and a storage medium are provided. The audio signal processing method includes acquiring, by using the voice registration module based on a first audio signal, a first hidden state corresponding to a voice registration module is acquired, and, extracting, based on the first hidden state, a target audio signal from a second audio signal.
G10L 17/02 - Preprocessing operations, e.g. segment selection; Pattern representation or modelling, e.g. based on linear discriminant analysis [LDA] or principal components; Feature selection or extraction
G10L 17/04 - Training, enrolment or model building
G10L 25/18 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being spectral information of each sub-band
There is provided a semiconductor package in which warpage of an interposer is prevented to improve product reliability. The semiconductor package comprising a first substrate including a first insulating layer, and a first conductive pattern disposed in the first insulating layer, a semiconductor chip disposed on the first substrate, an interposer disposed on the semiconductor chip, wherein the interposer includes a second insulating layer, and a second conductive pattern disposed in the second insulating layer, a support member disposed on a bottom surface of the second insulating layer and is in contact with an upper surface of the semiconductor chip, wherein the support member includes a first lower pad and a bump disposed under the first lower pad and a first connection member disposed between the first substrate and the interposer so as to connect the first conductive pattern and the second conductive pattern to each other.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
49.
METHOD, DEVICE AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR RTS/CTS ADAPTIVE ENABLEMENT/DISABLEMENT
A method and device for RTS/CTS adaptive enablement/disablement are provided. The method for RTS/CTS adaptive enablement includes changing a first state to a second state in response to determining that a first packet error rate satisfies a condition, the first packet error rate being measured in the first state, and each of the first state and the second state corresponding to a different one of an RTS/CTS enabled state and an RTS/CTS disabled state, and determining whether to change from the second state to the first state based on a second packet error rate and a threshold, the second packet error rate being measured in the second state.
A method performed by a first terminal is provided. The method includes identifying capabilities of the first terminal connected to at least one component device, establishing, via a server, a session associated with an augmented reality (AR) service based on the capabilities of the first terminal, performing pre-processing on 3 dimensional (3D) media data acquired by the at least one component device, and transmitting, to a second terminal, the pre-processed 3D media data.
A semiconductor device includes a S/A circuit, bit lines, a gate electrode, a gate insulation pattern, a channel, an upper contact plug and a capacitor on a substrate. The bit lines includes first, second, third and fourth bit lines sequentially arranged in the second direction. A first lower contact plug, a first lower wiring and a second lower contact plug are sequentially stacked in a third direction between the S/A circuit and the first bit line, and are electrically connected to the S/A circuit and the first bit line. A third lower contact plug, a second lower wiring and a fourth lower contact plug are sequentially stacked in the third direction between the S/A circuit and the third bit line, and are electrically connected to the S/A circuit and the third bit line. The first and second lower wirings are at different levels from each other.
A cleaning device and a method therefor are provided. The cleaning device includes a vacuum cleaner including a dust collecting container and a docking station to which the dust collecting container is coupled. The docking station includes a suction device configured to move air from the dust collecting container to inside of the docking station, a collector configured to collect a foreign substance that is moved together with the air by driving of the suction device, a suction flow path along which air moves inside the docking station, a flow adjusting device configured to open or close the suction flow path, and at least one processor configured to control the suction device to operate based on the dust collecting container being coupled to the docking station, and control the flow adjusting device to periodically open and close the suction flow path in a state in which the suction device operates.
A47L 9/14 - Bags or the like; Attachment of, or closures for, bags
A47L 9/28 - Installation of the electric equipment, e.g. adaptation or attachment to the suction cleaner; Controlling suction cleaners by electric means
53.
METHOD AND APPARATUS FOR IMPROVEMENTS IN APPLICATION DISCOVERY AND EVENT EXPOSURE
The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of things (IoT). A method, by a network data analytics function (NWDAF) entity, for supporting user equipment (UE) data collection from a UE, includes receiving, from a service consumer network function (NF) entity, a first request for the UE data collection for analytics, the first request including analytics filter information, discovering an application function (AF) entity that provides the UE data collection based on AF profiles of the AF entity, determining a list of subscription permanent identifiers (SUPIs) from at least one of an access and mobile management function (AMF) entity and a session management function (SMF) entity based on the analytics filter information, transmitting, to the AF entity, a second request for a subscription to the AF entity for the UE data collection, wherein the subscription is associated with a list of UEs related to the determined list of the SUPIs, and receiving, from the AF entity, a notification on processed data collected according to the subscription.
A method of providing an auxiliary power by an auxiliary power supply. The method may include converting an external power to a plurality of charging voltages; charging a charging circuit with a first charging voltage of the plurality of charging voltages; monitoring a voltage of the charging circuit; when capacitance of the charging circuit is less than a first reference capacitance, charging the charging circuit with a second charging voltage of the plurality of charging voltages, the second charging voltage being higher than the first charging voltage by a first voltage amount; and providing an auxiliary power to outside the auxiliary power supply. The auxiliary power may be generated based on the voltage of the charging circuit.
A three-dimensional semiconductor memory device may include a substrate, a peripheral circuit structure on the substrate, and a cell array structure on the peripheral circuit structure. The cell array structure may include a stack that includes interlayer insulating layers and conductive patterns alternately stacked with one another, a source structure on the stack, and a vertical structure that extends in the stack and is electrically connected to a bottom surface of the source structure. The vertical structure may include a channel layer that includes first portions respectively in vertical channel holes extending in the stack, and a second portion that extends in a region between the stack and the source structure and is electrically connected to the first portions.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
56.
RF CIRCUIT FOR PREVENTING DAMAGE TO POWER AMPLIFIER
According to an embodiment, a Radio Frequency (RF) circuit comprises: a power amplifier; a switching circuit configured to electrically connect the power amplifier to a first switch in case that an output voltage of the power amplifier does not exceed a threshold voltage and to electrically connect the power amplifier to a terminating resistor in case that the output voltage of the power amplifier exceeds the threshold voltage; a first electrical path formed between the power amplifier and the switching circuit; and a first diode connected to a second electrical path formed from a first point of the first electrical path to the switching circuit, the first diode connected between the first point and the switching circuit.
According to an embodiment of the disclosure, a charging cradle for mounting and charging a wireless vacuum cleaner, may include: a cradle, and a cleaning station including an automatic cover opening/closing device physically connected to the wireless cleaner and disposed on the cradle. The automatic cover opening/closing device may include: a lower case, an upper case integrally connected to the lower case, a middle case coupled to each of the lower case and the upper case and configured to be movable away from the lower case or toward the lower case, the middle case being rotatably coupled to the lower case, a cover configured to open/close the upper case, a driver comprising a motor and meshing with the middle case and configured to provide a force for rotating and moving the middle case, and a mechanical device provided in the middle case and configured to open/close the cover in response to operation of the driver.
A47L 9/28 - Installation of the electric equipment, e.g. adaptation or attachment to the suction cleaner; Controlling suction cleaners by electric means
58.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
59.
CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME
A chip-on-film package includes: a lower base film including a first surface and a second surface, which are opposite to each other; an upper base film including a third surface and a fourth surface, which are opposite to each other, and is disposed on the lower base film; a first semiconductor chip mounted on the second surface of the lower base film; a second semiconductor chip mounted on the third surface of the upper base film; and an interposer film interposed between the lower and upper base films, wherein the second and third surfaces face each other.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
60.
PHOTONIC INTEGRATED CIRCUIT PLATFORM AND OPTICAL PHASE ARRAY DEVICE USING THE SAME
A photonic integrated circuit platform includes a substrate, a first oxide layer disposed on the substrate and including an insulating transparent oxide, and a first optical element layer disposed on the first oxide layer and including a semiconductor material. The photonic integrated circuit platform further includes a second optical element layer disposed on the first optical element layer and including an insulating material different from the insulating transparent oxide of the first oxide layer, the second optical element layer further including a compound semiconductor material different from the semiconductor material of the first optical element layer, a second oxide layer disposed on the second optical element layer and including an insulating transparent oxide, and a plurality of optical elements formed by patterning the first optical element layer or the second optical element layer.
G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
An integrated circuit device includes a plurality of wiring structures on a substrate and extending in a first direction parallel to an upper surface of the substrate and each including a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate; an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material; and a capping layer on an upper surface of the wiring layer and including a conductive material; a via layer on the wiring structures, the via layer being electrically connected to one wiring structure; and an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and an upper surface of each insulating pattern.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A semiconductor device includes a substrate including first and second regions; a first active fin extending in a first direction on the first region; a second active fin extending in the first direction on the second region; an isolation pattern on the substrate between the first and second regions; a first gate structure on the first active fin, extending in a second direction perpendicular to the first direction, and onto an upper surface of the isolation pattern; and a second gate structure on the second active fin, extending in the second direction, and onto the upper surface of the isolation pattern, wherein the first gate structure includes a first portion having a first width and a second portion having a second width that is less than the first width, and the second gate structure includes a third portion having the first width and a fourth portion having the second width.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
63.
NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME
According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.
G11C 16/26 - Sensing or reading circuits; Data output circuits
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
64.
CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME
A chip on film (COF) package includes a film substrate including a base film having a mounting region, a main line pattern extending on the base film, and a branch line pattern extending on the base film and electrically connected to the main line pattern, a semiconductor chip vertically overlapping the mounting region, a first bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the main line pattern, and a second bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the branch line pattern, the branch line pattern extends so as not to overlap a first edge of the first bump structure facing a first edge of the mounting region and a first edge of the second bump structure facing the first edge of the mounting region.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
65.
METHOD, DEVICE, AND ELECTRONIC APPARATUS FOR SECURELY PASSING DATA
A method for passing data includes: a secure operating system allocating a cache area in trusted execution environment (TEE) to data in response to a client application (CA) calling a trusted application (TA) entry to pass the data to a TA; the secure operating system copying the data from a pre-allocated shared memory to the cache area; and the secure operating system running the TA entry so that the TA obtains the data from the cache area.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
An torque pattern adjustment apparatus including a display configured to display a first torque pattern corresponding to a gait cycle, and a generator configured to generate a second torque pattern by adjusting at least a portion of the first torque pattern in response to a reception of an input, and a torque pattern adjustment method using the same may be provided. The first torque pattern may be applied to a joint of a user.
A food waste disposer including a housing; a grinding device inside the housing to grind food waste; an exhaust fan inside the housing to form an air flow; an exhaust pipe connected to the exhaust fan to form an exhaust flow path along which air from the grinding device flows via the air flow formed by the exhaust fan; a filter assembly to adsorb contaminants from the air flowing along the exhaust flow path; a branch pipe branching from the exhaust pipe between the grinding device and the exhaust fan to form a connection flow path communicating with the exhaust flow path; and a sterilization device connected to the branch pipe to selectively open and close the connection flow path, and, with the connection flow path being open, generate and supply plasma to the exhaust pipe through the connection flow path via an intake airflow formed by the exhaust fan.
B02C 18/00 - Disintegrating by knives or other cutting or tearing members which chop material into fragments; Mincing machines or similar apparatus using worms or the like
B02C 18/12 - Disintegrating by knives or other cutting or tearing members which chop material into fragments; Mincing machines or similar apparatus using worms or the like with rotating knives within vertical containers with drive arranged below container
B02C 18/16 - Disintegrating by knives or other cutting or tearing members which chop material into fragments; Mincing machines or similar apparatus using worms or the like with rotating knives - Details
B02C 23/26 - Passing gas through crushing or disintegrating zone characterised by point of gas entry or exit or by gas flow path
68.
WEARABLE DEVICE FOR PROVIDING INFORMATION ABOUT AN APPLICATION THROUGH AN EXTERNAL DISPLAY AND METHOD OF CONTROLLING THE WEARABLE DEVICE
Provided is a wearable device that includes: a first display provided on a first surface of the wearable device configured to face a face of a user wearing the wearable device, and a second display provided on a second surface of the wearable device configured to face an external environment of the wearable device when the wearable device is worn by the user. The wearable device may be configured to display a first execution screen of a first application on the first display, while the wearable device is worn by the user, determine a display type for information to be displayed on the second display, while displaying the first execution screen on the first display, and display information related to the first execution screen on the second display based on the display type.
An example method for controlling an electronic device includes detecting at least one user and acquiring user information of the detected at least one user; determining a user mode based on the acquired user information; determining a service to be provided to the detected at least one user, by inputting the user information and the determined user mode as input data to a model learned by an artificial intelligence algorithm; and providing the determined service corresponding to the user mode. A method for providing the service by the electronic device may at least partially use an artificial intelligence model learned according to at least one of machine learning, neural network, and deep learning algorithms.
An integrated circuit device includes a back side interconnection structure extending in a first horizontal direction. An active substrate includes a fin-type active area extending in the first horizontal direction on the back side interconnection structure. A metal silicide film is between the back side interconnection structure and the active substrate. A plurality of gate structures extends in a second horizontal direction perpendicular to the first horizontal direction on the active substrate. A first source/drain area and a second source/drain area are spaced apart from each other in the first horizontal direction with the plurality of gate structures therebetween on the active substrate. The first source/drain area directly contacts the active substrate. The second source/drain area is spaced apart from the active substrate and insulated from the active substrate.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
The disclosure provides a method for generating relightable 3D portrait using a deep neural network and a computing device implementing the method. A possibility of obtaining, in real time and on computing devices having limited processing resources, realistically relighted 3D portraits having quality higher or at least comparable to quality achieved by prior art solutions, but without utilizing complex and costly equipment is provided. A method for rendering a relighted 3D portrait of a person, the method including: receiving an input defining a camera viewpoint and lighting conditions, rasterizing latent descriptors of a 3D point cloud at different resolutions based on the camera viewpoint to obtain rasterized images, wherein the 3D point cloud is generated based on a sequence of images captured by a camera with a blinking flash while moving the camera at least partly around an upper body, the sequence of images comprising a set of flash images and a set of no-flash images, processing the rasterized images with a deep neural network to predict albedo, normals, environmental shadow maps, and segmentation mask for the received camera viewpoint, and fusing the predicted albedo, normals, environmental shadow maps, and segmentation mask into the relighted 3D portrait based on the lighting conditions.
A capacitor structure includes a lower electrode structure disposed on a substrate, including an oxide of a first metal having 4 valence electrons, and being doped with a second metal having 3, 5, 6, or 7 valence electrons, a dielectric pattern disposed on a sidewall of the lower electrode structure, and an upper electrode disposed on a sidewall of the dielectric pattern.
An electronic device is provided. The electronic device includes at least one first communication device supporting at least one short-range communication, at least one second communication device supporting cellular communication, and at least one processor. The at least one processor may be configured to transmit a first message for requesting first information to an external electronic device supporting the short-range communication through the at least one first communication device, based on the execution command of the first application, receive a second message including the first information, compare the first information and the second information, transmit and/or receive data corresponding to the first application to and/or from the server through a part of the at least one second communication device, based on the electronic device being determined as the primary device, based on a comparison result of the first information and the second information.
A method including determining a first internal short circuit resistance value of a first battery based on the sensor data, determining a first internal short circuit state of the first battery using the first internal short circuit resistance value, and performing a first control process of reducing a current of the first battery, for alleviating a current burden of the first battery, in response to the determined first internal short circuit state being a first state other than a predetermined normal state.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
75.
SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A semiconductor device includes a first semiconductor chip. The first semiconductor chip includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, and having a first active layer adjacent to the first surface, the first semiconductor substrate having a quadrangle shape from a plan view; a first through electrode penetrating at least a portion of the first semiconductor substrate and connected to the first active layer; a second chip connection pad on the second surface of the first semiconductor substrate and connected to the first through electrode; a first dummy pattern positioned outside the second chip connection pad on the second surface of the first semiconductor substrate from the plan view, the first dummy pattern comprising a line pattern extending horizontally along the second surface of the first semiconductor substrate; and a first chip connection pad on the first surface of the first semiconductor substrate and connected to the first through electrode. The first dummy pattern is disposed adjacent to at least one side of four sides of the quadrangle shape of the first semiconductor substrate from the plan view.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
76.
MEMORY DEVICE, A CONTROLLER FOR CONTROLLING THE SAME, A MEMORY SYSTEM INCLUDING THE SAME, AND AN OPERATING METHOD OF THE SAME
A memory device including: a memory cell array including a plurality of memory cells disposed at intersections of wordlines and bitlines; an error correction circuit configured to read data from the memory cell array and to correct an error in the read data; and an error check and scrub (ECS) circuit configured to perform a scrubbing operation on the memory cell array, wherein the ECS circuit includes: a first register configured to store an error address obtained in the scrubbing operation; and a second register configured to store a page offline address received from an external device.
An example electronic device may include a foldable housing, including a hinge, a first housing connected to the hinge and including a first surface facing a first direction and a second surface facing a second direction opposite the first direction, and a second housing connected to the hinge, including a third surface facing a third direction and a fourth surface facing a fourth direction opposite the third direction, the second housing configured to be foldable with respect to the first housing about the hinge, wherein the first surface faces the third surface in a folded state of the electronic device; a display extending from the first surface to the third surface to provide the first surface and the third surface and including a touch controller configured to control a receiving function of an input on the display; a processor disposed inside the first or second housing and operatively coupled to the display; and a memory operatively connected to the processor, wherein the memory may store instructions that, when executed, cause the processor to control the electronic device to: detect the occurrence of changing an angle between the first housing and the second housing; receive a touch interrupt produced based on an input on the display; identify characteristics of the input in response to detecting the change in the angle; and determine whether to cancel the touch event corresponding to the input based on the characteristics of the input.
G06F 1/16 - Constructional details or arrangements
G06F 3/04883 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures for inputting data by handwriting, e.g. gesture or text
A semiconductor device is provided. The semiconductor device includes an active pattern extending in a first horizontal direction, a plurality of lower nanosheets stacked on the active pattern and spaced apart from one another in a vertical direction, a separation layer on the plurality of lower nanosheets, a plurality of upper nanosheets stacked on the separation layer and spaced apart from one another in the vertical direction, a gate electrode extending on the active pattern in a second horizontal direction, the gate electrode surrounding each of the plurality of lower nanosheets, the separation layer and the plurality of upper nano sheets, and a first conductive layer between the gate electrode and each of a top surface and a bottom surface of the plurality of upper nanosheets. The first conductive layer is not between the gate electrode and sidewalls of the plurality of upper nanosheets.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
An image sensor including: a pixel array including first and second pixel groups, each of the first and second pixel groups includes of pixels arranged in rows and columns; and a row driver configured to provide transmission control signals to the pixel array, the first pixel group includes a first auto-focus (AF) pixel including photodiodes arranged in a first direction, the pixels of the first pixel group output a pixel signal through a first column line, and the second pixel group includes a second AF pixel including photodiodes arranged in a second direction perpendicular to the first direction, the pixels of the second pixel group output a pixel signal through a second column line, and the first AF pixel of the first pixel group and the second AF pixel of the second pixel group receive same transmission control signals.
A compressor circuit and a semiconductor integrated circuit included the compressor circuit are provided. The semiconductor integrated circuit includes a compressor circuit which includes a first full adder circuit which receives an A1 signal, a B1 signal, and a CI signal to output an IS signal and an ICO signal, and a second full adder circuit which receives a B2 signal, the IS signal, and a CI2 signal to output an S signal and a CO signal. Each of the first full adder circuit and the second full adder circuit are in an L-shaped layout, the first full adder circuit and the second full adder circuit have bent portions that are point-symmetrically engaged with each other, and the compressor circuit is in a rectangular shape. The number of transistors in the second full adder circuit is smaller than the number of transistors in the first full adder circuit.
H03K 17/00 - Electronic switching or gating, i.e. not by contact-making and -breaking
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
81.
WIRE-DRIVEN EXOSKELETON MANIPULATOR AND ROBOT CLEANER HAVING THE SAME
A manipulator may include a base link having a ring shape; a first ring-shaped link having a ring shape and disposed to rotate at a predetermined angle at a front end of the base link; a second ring-shaped link having a ring shape and disposed to rotate at a predetermined angle at a front end of the first ring-shaped link; a first Borden cable and a second Borden cable connected to the first ring-shaped link and formed to rotate the first ring-shaped link; a third Borden cable and a fourth Borden cable connected to the second ring-shaped link and formed to rotate the second ring-shaped link; and a driving device that operates the first Borden cable, the second Borden cable, the third Borden cable, and the fourth Borden cable.
A method of a user equipment in a wireless communication system, includes: receiving, from a base station, configuration information including at least one of a pre-condition, a trigger condition, and a cancel condition for a handover from the base station to a satellite; receiving a first reference signal from the base station and a second reference signal from the satellite, respectively; measuring Reference Signal Received Power (RSRP) of each of the first reference signal and the second reference signal; and transmitting a first measurement report to the base station, based on a determination that the trigger condition related to the first reference signal and the pre-condition related to the second reference signal are satisfied.
Provided is a retainer ring, a chemical mechanical polishing apparatuses including the same, and a substrate polishing method using the same. A slurry groove is upwardly recessed from a bottom surface of the retainer ring. The slurry groove extends in an arc shape from an inner surface of the retainer ring toward an outer surface of the retainer ring. A curvature radius of the slurry groove is greater than a distance between a center of the retainer ring and a curvature center of the slurry groove.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
84.
SENSE AMPLIFIER, MEMORY DEVICE INCLUDING SENSE AMPLIFIER AND OPERATING METHOD OF MEMORY DEVICE
A sense amplifier includes a first isolation transistor connected to a first memory cell through a first bit line, a second isolation transistor connected to a second memory cell through a second bit line, and sense amplifying circuitry connected to the first memory cell through the first isolation transistor, connected to the second memory cell through the second isolation transistor, and latch, to a pair of sense bit lines, data corresponding to a cell voltage stored in the first memory cell or the second memory cell, wherein the sense amplifying circuitry is configured to perform an offset cancellation operation while a charge sharing operation is performed between the first memory cell and the first bit line or between the second memory cell and the second bit line.
Disclosed herein is a washing machine including a cabinet, a tub provided in the cabinet, a rotating tub rotatably provided in the tub, a shaft connected to rotate the rotating tub, a motor configured to rotate the shaft and including a rotor and a stator, a drip pan disposed at a lower end of the cabinet, and a friction member mounted on a lower end of the shaft and configured to contact with at least one surface of the drip pan, wherein the friction member includes a first portion secured to the shaft, a second portion connected to the first portion and having a curved surface in contact with the at least one surface of the drip pan.
D06F 37/24 - Mountings, e.g. resilient mountings, for the rotary receptacle, motor, tub or casing; Preventing or damping vibrations in machines with a receptacle rotating or oscillating about a vertical axis
D06F 37/20 - Mountings, e.g. resilient mountings, for the rotary receptacle, motor, tub or casing; Preventing or damping vibrations
A method and a system for image capturing of an eye are provided. The image capturing method in an electronic device includes directing radar signals on one or more portions of the eye that is required to be captured, determining an amount of signals absorbed into one or more portions of the eye by measuring the amount of signals reflected by one or more portions of the eye and estimating size of one or more portions of the eye based on the amount of signals absorbed, and generating an image of the eye having the portions with the estimated sizes.
G06V 40/18 - Eye characteristics, e.g. of the iris
G01S 7/41 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisation; Target signature; Target cross-section
G01S 13/89 - Radar or analogous systems, specially adapted for specific applications for mapping or imaging
Disclosed is an electronic apparatus which performs speech recognition. The apparatus includes: at least one sensor; a memory storing context data each corresponding to a plurality of commands; a microphone; and at least one processor configured to acquire a text corresponding to a voice command in case that the voice command is received through the microphone, identify context data corresponding to an identified command in case that a command having similarity of a first threshold value or more with the acquired text is identified among the plurality of commands stored in the memory, acquire a control signal corresponding to the identified command in case that current context data including context data acquired through the at least one sensor is identified as having similarity of a second threshold value or more with the context data corresponding to the identified command, and perform an operation based on the control signal.
A processor includes an instruction pipeline that sequentially processes an original instruction and a duplicate instruction, which is generated by duplicating the original instruction. An original register file stores a result obtained by processing the original instruction in the instruction pipeline within a register of a nth index thereof. A duplicate register file stores a result obtained by processing the duplicate instruction in the instruction pipeline within a register of a nth index thereof. A comparing unit compares the register of the nth index in the original register file with the register of nth index in the duplicate register file and outputs an error detection signal, in response to a control signal.
Provided is an electronic device that may receive information corresponding to a user utterance from a first external electronic device, identify a second external electronic device to perform at least a part of an action corresponding to the user utterance, based on determining that the first external electronic device and the second external electronic device are not located within a specified range: determine a target external electronic device to provide a first notification and transmit a command to the target external electronic device to provide the first notification, and transmit a command to the second external electronic device to perform the part of the action corresponding to the user utterance.
A quantum dot of a light emitting device, includes: a core; and a shell around the core and including halogen elements of at least one type, wherein a first number per unit volume of halogen elements in a first area of the shell, that includes an outer surface of the shell, is larger than a second number per unit volume of halogen elements in a second area of the shell other than the outer surface of the shell.
H01L 33/06 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
H01L 33/28 - Materials of the light emitting region containing only elements of group II and group VI of the periodic system
H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system
91.
ERROR CORRECTION CODE DECODER USING CONSTACYCLIC CODE, AND MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Seoul National University R&DB Foundation (Republic of Korea)
Inventor
Hyun, Jihwan
Kim, Chanki
Kim, Jaewha
No, Jongseon
Choi, Junghwan
Abstract
An error correction code (ECC) decoder includes a syndrome generator and a burst error corrector. The syndrome generator generates global syndrome data and local syndrome data using input data and a parity check matrix based on a constacyclic code. The burst error corrector corrects a correctable error included in the input data using the global syndrome data and the local syndrome data. The input data includes a plurality of data bits arranged along a first direction and a second direction. The ECC decoder simultaneously corrects a single burst error and a multi-bit error. The single burst error occurs on two or more symbols arranged along the first direction in the input data, and each symbol includes two or more data bits. The multi-bit error randomly occurs on two or more data bits in the input data.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
92.
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
A semiconductor device includes a gate stack structure including insulating patterns and conductive patterns which are alternately stacked, a first separation structure penetrating the gate stack structure, a second separation structure penetrating the gate stack structure and being adjacent to the first separation structure, first and second memory channel structures penetrating the gate stack structure and disposed between the first separation structure and the second separation structure, a first bit line overlapping with the first and second memory channel structures and electrically connected to the first memory channel structure, and a second bit line overlapping with the first and second memory channel structures and the first bit line and electrically connected to the second memory channel structure.
A blade for sawing a panel, including a first blade portion configured to saw the panel along a first direction, wherein the panel includes a plurality of panel level packages (PLPs) arranged in the first direction and a second direction which is substantially perpendicular to the first direction; and a second blade portion arranged on an upper surface of the first blade portion, and configured to saw the panel along the second direction, wherein a width of the second blade portion is greater than a width of the first blade portion.
B26D 1/00 - Cutting through work characterised by the nature or movement of the cutting member; Apparatus or machines therefor; Cutting members therefor
B26D 1/06 - Cutting through work characterised by the nature or movement of the cutting member; Apparatus or machines therefor; Cutting members therefor involving a cutting member which does not travel with the work having a linearly-movable cutting member wherein the cutting member reciprocates
94.
METHOD AND APPARATUS WITH SIDECAR PATTERN CHECKPOINTING
A method including, for each of a plurality of job nodes, corresponding to a job request of a scheduler node, distributing an application container and a sidecar container of a corresponding job node of the plurality of job nodes, and storing, by the sidecar container, information about a respective state of the application container in a memory through a communication between the sidecar container and at least one sidecar container of another job node of the plurality of job nodes.
A lithium garnet material has the formula Li7-δLa3Z2z-x-y-zM1xM2yM3zO12, where M1 is one or a combination of (Y, In, Mg, Ca, Ba, Sc, Sr, Ru) with oxidation number (valence) lower than 4+, M2 is one or a combination of (Bi, Ta, Nb, Mo, Sb, Te) with oxidation number (valence) higher than 4+, and M3 is one or a combination of (Hf, Ti, Sn, Si) with oxidation number (valence) equal to 4+, subject to 0
Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H10N 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups
97.
APPARATUS AND METHOD FOR ESTIMATING BIO-INFORMATION
An apparatus for estimating bio-information includes: a sensor including one or more light sources configured to emit light to an object and a plurality of detectors configured to detect light reflected from the object; and a processor configured to transform a plurality of light quantities obtained from respective detectors of the plurality of detectors to a distance domain, to combine the plurality of transformed light quantities in the distance domain, to correct the combined light quantity based on a reference light quantity for correcting a deviation of a distance between the one or more light sources and the plurality of detectors, and to estimate bio-information based on a light quantity resulting from the correction.
An edge ring includes a ring body having an axis parallel to a first direction; and a plurality of protrusions provided at an inner side surface of the ring body and protruding toward the axis, the plurality of protrusions being spaced apart from each other in a circumference direction of the edge ring, wherein a first distance between the axis and a first point on the inner side surface of the ring body between two adjacent protrusions of the plurality of protrusions is larger than a second distance between the axis and a second point on the inner side surface of the ring body at which a protrusion of the plurality of protrusions is provided.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A memory device and a method of precharging a decoded address are provided. The memory device includes a memory cell array comprising a plurality of rows; a row decoder configured to select a row to be activated from among the plurality of rows based on a decoded row address; and an interface circuit configured to: generate the decoded row address based on decoding a plurality of bits of a row address, transfer the decoded row address to the row decoder, in a first mode of the memory device, precharge the decoded row address that is transferred to the row decoder, and in a second mode of the memory device, determine whether a precharge signal is received in the second mode, and precharge the decoded row address based on the precharge signal.
Disclosed are a wearable device on which a virtual object is displayed by using a single display module or a plurality of display modules, and a control method thereof. A wearable device according to an embodiment of the present document comprises: a first display module; a second display module; and at least one processor, wherein the at least one processor may be configured to: output, in a first mode, image data through the first display module and the second display module; identify switching from the first mode to a second mode; determine, in the second mode, any one display module from among the first display module or the second display module as an output display module; and control the output display module so that the image data is output through the determined output display module.
G06T 19/00 - Manipulating 3D models or images for computer graphics
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G06F 3/0481 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
G06F 1/16 - Constructional details or arrangements