Abstract

A machine-implemented method for managing a flash storage system includes receiving a command for a data operation. The method includes determining a projected life value for each of a plurality of flash memory devices in the flash storage system, wherein the projected life value for at least one of the plurality of flash memory devices is higher than the projected life value for at least another one of the plurality of flash memory devices. The method also includes selecting a flash memory block on one of the plurality of flash memory devices for the data operation based on the respective projected life values for the plurality of flash memory devices.

IPC Classes  ?

• G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

Embodiments of the present invention include a memory unit and a processor coupled to a memory unit. The processor is operable to group a plurality of subsets of data from an input data stream and compute a first hash value corresponding to a first grouped subset of data. Additionally, the processor is operable to detect a match between the first hash value and a second hash value stored in a hash table. Furthermore, the processor is also configured to monitor a hash value match frequency for the input data stream in which the processor is operable to increment a counter value responsive to a detection of the match and determine an entropy level for the input data stream based on the counter value relative to a frequent hash value match threshold. The processor can generate an instruction to either initialize performance of a data compression operation when the counter value meets or exceeds the frequent hash value match threshold or refrain from the performance of the data compression operation when the counter value fails to meet the frequent hash value match threshold.

IPC Classes  ?

• H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
• G06F 7/00 - Methods or arrangements for processing data by operating upon the order or content of the data handled
• G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures

Abstract

In various embodiments, a high-density solid-state storage unit includes a base section and a cassette section having plurality of flash cards. The cassette section can be removably attached to the base section to provide security of data stored on the plurality of flash cards. The cassette section provides for physical security of the flash cards in part through packaging of the enclosure and energy transfer to the base station. The cassette section further provides for security of the data stored on the flash cards in part through a trusted platform module (TPM) embodied as a removable module connected to a universal serial bus (USB) style connector.

IPC Classes  ?

• G06F 1/16 - Constructional details or arrangements
• G06F 1/18 - Packaging or power distribution

Abstract

Systems described herein enable PCIe device components to be used with multiple PCIe topologies and with host systems of varying configurations. In some cases, a number of varying PHYs and PCIe cores are utilized to increase the number of applications and/or specifications that may be satisfied with a host interface design. Further, some systems described herein may include a number of synchronizers, clock multiplier units, and selectors to create a hsot interface that can be configured for a number of applications. Despite increasing the flexibility of the usage of systems disclosed herein, costs can be reduced by using the systems of the present disclosure for PCIe based devices.

IPC Classes  ?

• G06F 13/14 - Handling requests for interconnection or transfer

Abstract

First data is received for storing in a first asymmetric memory device. A first writing phase is identified as a current writing phase. A first segment included in the first asymmetric memory device is identified as next segment available for writing data. The first data is written to the first segment. Information associated with the first segment is stored, along with information indicating that the first segment is written in the first writing phase. Second data is received for storing in the asymmetric memory. A second segment included in the first asymmetric memory device is identified as the next segment available for writing data. The second data is written to the second segment. Information associated with the second segment and the second memory block is stored along with information indicating that the second segment is written in the second writing phase.

IPC Classes  ?

• G06F 12/02 - Addressing or allocation; Relocation
• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result