Provided is a method for migrating from a first storage system to a second storage system. The method includes receiving a command to migrate from a first storage system to a second storage system, wherein the first storage system comprises a first primary storage and a first secondary storage, and wherein the second storage system comprises a second primary storage and a second secondary storage. The method further includes initiating, in response to receiving the command, data replication between the first primary storage and the second primary storage. The method further includes initiating, in response to receiving the command, data replication between the first primary storage and the second secondary storage. The method further includes migrating from the first storage system to the second storage system.
At least one request to store diagnostic state of a virtual machine is obtained. Based on obtaining the at least one request, a store of diagnostic state of the virtual machine is performed to provide stored diagnostic state of the virtual machine. The performing the store includes encrypting the diagnostic state of the virtual machine that is unencrypted and being stored to prevent a reading of the diagnostic state of the virtual machine by an untrusted entity prior to encrypting the diagnostic state of the virtual machine that is unencrypted and being stored.
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
A trusted execution environment obtains an attestation request. The attestation request includes at least an attestation key. Based on obtaining the attestation request, one or more integrity measurements are computed, and the computing uses at least the attestation key. The one or more integrity measurements are provided to an entity, and the one or more integrity measurements are to be used to verify that a secure guest has been started using a selected secure guest image and selected secure guest metadata.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
A secure guest generates an updated image for the secure guest, and computes one or more measurements for the updated image. The secure guest provides the one or more measurements to a trusted execution environment and obtains from the trusted execution environment metadata for the updated image. The metadata is generated based on metadata of the secure guest and obtaining the one or more measurements.
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A query operation is performed to obtain information for a select entity of a computing environment. The information includes boost information of one or more boost features currently available for the select entity. The one or more boost features are to be used to temporarily adjust one or more processing attributes of the select entity. The boost information obtained from performing the query operation is provided in an accessible location to be used to perform one or more actions to facilitate processing in the computing environment.
A vector entry of a signaling vector is registered to a buffer summary group. The buffer summary group includes one or more summary indicators for one or more buffers assigned to the buffer summary group. A command is processed that sets a vector indicator in the vector entry and based on setting the vector indicator in the vector entry, a summary indicator of the one or more summary indicators is set in the buffer summary group.
Edge device task management by receiving an indicator corresponding to a first container running a task on a first edge device of a cluster of edge devices, wherein the indicator indicates an error status of the first container, and wherein task data of the task is stored in a first local storage of the first edge device, selecting a second edge device from the cluster of edge devices, wherein a second container on the second edge device is to run the task, instructing the first and second edge devices to transfer the task data from the first local storage of the first edge device to a second local storage of the second edge device, and in response to receiving a notification that indicates the task data has been transferred from the first local storage to the second local storage, sending the task to the second container.
A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.
An indication of a function to be executed is obtained, in which the function is one function of an instruction and configured to perform multiple operations. A determination is made of an operation of the multiple operations to be performed, and a set of function-specific parameters is validated using a set of values and a corresponding set of relationships. The set of values and corresponding set of relationships are based on the operation to be performed. One set of values and corresponding set of relationships are to be used for the operation to be performed, and another set of values and corresponding set of relationships are to be used for another operation of the multiple operations.
A tensor of a first select dimension is reformatted to provide one or more sub-tensors of a second select dimension. The reformatting includes determining a number of sub-tensors to be used to represent the tensor. The reformatting further includes creating the number of sub-tensors, in which a sub-tensor is to start on a boundary of a memory unit. Data of the tensor is rearranged to fit within the number of sub-tensors.
An instruction to perform a recurrent neural network cell activation is executed. The executing includes performing a plurality of operations of the recurrent neural network cell activation to provide a result of the recurrent neural network cell activation. The plurality of operations is performed in a single invocation of the instruction. The recurrent neural network cell activation is, for instance, a long short-term memory cell activation or a gated recurrent unit cell activation.
An instruction to convert data from a source data type to a target data type is obtained. The source data type is selected from one or more source data types supported by the instruction, and the target data type is selected from one or more target data types supported by the instruction. Based on a selected data type of the source data type or the target data type, a determination is made of a rounding mode for use by the instruction. The rounding mode is implicitly set based on the selected data type; it is assigned to the selected data type. A conversion of the data from the source data type to the target data type is performed. The conversion includes performing a rounding operation using the rounding mode implicitly set. The performing the conversion provides a result in the target data type, which is written to a select location.
An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.
A method, apparatus and computer system to identify threats on a TCP/IP-based network. The approach leverages a set of reference patterns (or "network spectrals") associated with one or more defined Indicators of Compromise (IoCs). At least one reference pattern is time-bounded and profiles a network traffic pattern using a set of session data (e.g., volume, direction, traffic metadata) that is payload-neutral and may be derived in part by time-series compression of at least one non-varying encoding interval. Network traffic data associated with a traffic pattern under test is received and encoded to generate a test spectral. A stream-based real-time comparison is performed to determine whether the test spectral matches against any of the reference spectrals. Responsive to identifying a match, a given remediation or mitigation action is then taken. A reference spectral may represent a bi- or multi-directional flow, and the multi-directional flow may involve multiple entities.
Mechanisms are provided for intelligently identifying an execution environment to execute a computing job. An execution time of the computing job in each execution environment of a plurality of execution environments is predicted by applying a set of existing machine learning models matching execution context information and key parameters of the computing job and execution environment information of the execution environment. The predicted execution time of the machine learning models is aggregated. The aggregated predicted execution times of the computing job are summarized for the plurality of execution environments. Responsive to a selection of an execution environment from the plurality of execution environments based on the summary of the aggregated predicted execution times of the computing job, the computing job is executed in the selected execution environment. Related data during the execution of the computing job in the selected execution environment is collected.
A collection of code fragments loaded in an interactive development platform for running on a first processor can be received. A candidate fragment in the collection of code fragments can be determined for migration to a second processor based on characterizing the collection of code fragments. Based on a location of the candidate fragment in the collection of code fragments, a spot can be identified in the collection of code fragments to inject a code for saving program context. The code for saving program context can be injected in the identified spot. Responsive to the code for saving program context having run on the first processor and based on a criterion, the program context can be migrated to the second processor.
A phase change memory (PCM) cell is disclosed which includes a first electrode (102), a heater (104) electrically connected to the first electrode, a PCM material (112) electrically connected to the heater, a second electrode (114) electrically connected to the PCM material, and a resistive liner (108) in direct contact with and electrically connected to a sidewall of the heater and to the PCM material. The resistive liner may have an L-shaped cross-section with a first leg extending along the sidewall of the heater and a second leg extending outward from the heater.
An electrostatic protection device for protecting an input port of an electronic circuit. The electrostatic protection device includes a first stacked coil, a second stacked coil, and an input terminal, wherein the second stacked coil is inductively coupled to the first stacked coil. The first stacked coil comprises a first coil input connected to the input terminal, a first coil output port connected to a lower frequency ESD protection circuit, and a first coil termination port connected to a termination load, and wherein the lower frequency ESD protection circuit comprises a lower frequency output. The second stacked coil comprises an output port connected to a higher frequency ESD protection circuit, and wherein the higher frequency ESD protection circuit comprises a higher frequency output. The electrostatic protection device comprises a summation circuit configured for outputting a summation of the higher frequency output and the lower frequency output.
An instruction to perform an operation selected from a plurality of operations configured for the instruction is executed. The executing includes determining a value of a selected operand of the instruction. The determining the value is based on a control of the instruction and includes reading the selected operand of the instruction from a selected operand location to obtain the value of the selected operand, based on the control having a first value, and using a predetermined value as the value of the selected operand, based on the control having a second value. The value and another selected operand of the instruction are multiplied to obtain a product. An arithmetic operation is performed using the product and a chosen operand of the instruction to obtain an intermediate result. A result from the intermediate result is obtained and placed in a selected location.
A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
21.
VECTOR CONVERT HEXADECIMAL FLOATING POINT TO SCALED DECIMAL INSTRUCTION
An instruction to perform converting and scaling operations is provided. Execution of the instruction includes converting an input value in one format to provide a converted result in another format. The converted result is scaled to provide a scaled result. A result obtained from the scaled result is placed in a selected location. Further, an instruction to perform scaling and converting operations is provided. Execution of the instruction includes scaling an input value in one format to provide a scaled result and converting the scaled result from the one format to provide a converted result in another format. A result obtained from the converted result is placed in a selected location.
Vector pack and unpack instructions are described. An instruction to perform a conversion between one decimal format and another decimal format is executed, in which the one decimal format or the other decimal format is a zoned decimal format. The executing includes obtaining a value from at least one register specified using the instruction. At least a portion of the value is converted from the one decimal format to the other decimal format different from the one decimal format to provide a converted result. A result obtained from the converted result is written into a single register specified using the instruction.
An instruction to perform scaling, converting and splitting operations is executed. The executing the instruction includes scaling an input value in one format to provide a scaled result. The scaled result is converted from the one format to provide a converted result in another format. The converted result is split into multiple parts, and one or more parts of the multiple parts are placed in a selected location.
A field effect transistor (FET) device is provided. The device includes an isolation region on a support substrate that separates a first back gate from a second back gate, and a gate dielectric layer on a first channel region and a second channel region. The device further includes a conductive gate layer having a work function value and a ferroelectric layer on the gate dielectric layer, wherein the first back gate can adjust a threshold voltage for the first channel region, and the second back gate can adjust a threshold voltage for the second channel region.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
H01L 27/10 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
25.
MIXED CONDUCTING VOLATILE MEMORY ELEMENT FOR ACCELERATED WRITING OF NONVOLATILE MEMRISTIVE DEVICE
An analog memory structure, and methods of writing to such a structure are provided. The analog memory structure includes a volatile memory element in series with a non-volatile memory element. The analog memory structure may change resistance upon application of a voltage. This may enable accelerated writing of the analog memory structure.
G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
26.
WRAP-AROUND CONTACTS INCLUDING LOCALIZED METAL SILICIDE
A conformally deposited metal liner used for forming discrete, wrap-around contact structures is localized between pairs of gate structures and below the tops of the gate structures. Block mask patterning is employed to protect transistors over active regions of a substrate while portions of the metal liner between active regions are removed. A chamfering technique is employed to selectively remove further portions of the metal liner within the active regions. Metal silicide liners formed on the source/drain regions using the conformally deposited metal liner are electrically connected to source/drain contact metal following the deposition and patterning of a dielectric layer and subsequent metallization.
A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.
A method, a computer program product, and a system of adversarial semi-supervised one-shot training using a data stream. The method includes receiving a data stream based on an observation, wherein the data stream includes unlabeled data and labeled data. The method also includes training a prediction model with the labeled data using stochastic gradient descent based on a classification loss and an adversarial term and training a representation model with the labeled data and the unlabeled data based on a reconstruction loss and the adversarial term. The adversarial term is a cross-entropy between the middle layer output data from the models. The classification loss is a cross-entropy between the labeled data and an output from the prediction model. The method further includes updating a discriminator with middle layer output data from the prediction model and the representation model and based on a discrimination loss, and discarding the data stream.
A device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has a tunable conductance. The select transistor is a ferroelectric field-effect transistor (FeFET) device which includes a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to the first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
30.
OPTIMIZING PLACEMENTS OF WORKLOADS ON MULTIPLE PLATFORMS AS A SERVICE BASED ON COSTS AND SERVICE LEVELS
A computer-implemented method, a computer program product, and a computer system for optimizing workload placements in a system of multiple platforms as a service. A computer first places respective workloads on respective platforms that yield lowest costs for the respective workloads. The computer determines whether mandatory constraints are satisfied. The computer checks best effort constraints, in response to the mandatory constraints being satisfied. The computer determines a set of workloads for which the best effort constraints are not satisfied and determines a set of candidate platforms that yield the lowest costs and enable the best effort constraints to be satisfied. From the set of workloads, the computer selects a workload that has a lowest upgraded cost and updates the workload by setting an upgraded platform index.
In an approach for improving performance of a batch job (232) running on database servers in an active-active architecture. A processor (504), responsive to the batch job (232) being ready to be executed on a source database server (210), sends a first communication to a target database server (220) with a synchronization start point (410). While executing the batch job (232), the processor (504) utilizes a pre-lock function, pre-load function, and lock avoidance function to prevent lock conflicts (420). The processor (504), responsive to either the source database server (210) or the target database server (220) encountering a commit statement, suspends the respective database server and sends a second communication to ask if the other respective database server is ready to complete the commit statement (430). The processor (504), responsive to the other respective database server confirming its ready to complete the commit statement, completes the commit statement on both the source database server (210) and the target database server (220).
An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.
H03K 19/02 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
H03K 19/12 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using diode rectifiers
33.
AUTOMATIC GENERATION OF AFFINITY AND ANTI-AFFINITY RULES
A computer implemented method, including: receiving an application to be deployed on a container-based environment (301); obtaining a specification for the application including information regarding a portion of the application contained within a given container (302); extracting portion information corresponding to connections between different portions of the application and interferences between different portions of the application (303); identifying affinity indicators and anti-affinity indicators for the portions of the application, wherein the affinity indicators are based upon the connections between different portions of the application and wherein the anti-affinity indicators are based upon the interferences between different portions of the application; and constructing affinity rules and anti-affinity rules for the containers by combining the affinity indicators to construct affinity rules and combining the anti-affinity indicators to construct anti-affinity rules (306).
Systems, computer-implemented methods, and computer program products to facilitate estimation of quantum resources to calculate an expectation value of a stochastic process using a re-parameterization method are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise a re-parameterization component that applies a quantum fault-tolerant operation to a variationally prepared quantum state corresponding to a probability distribution to produce a quantum state corresponding to a target probability distribution. The computer executable components can further comprise an estimation component that estimates at least one defined criterion of a quantum computer to be used to compute an expectation value of a stochastic process associated with the target probability distribution.
Establishing secure communications by sending a server certificate message, the certificate message including a first certificate associated with a first encryption algorithm and a second certificate associated with a second encryption algorithm, the first certificate and second certificate bound to each other, signing a first message associated with client-server communications using a first private key, the first private key associated with the first certificate, signing a second message associated with the client-server communications using a second private key, the second private key associated with the second certificate, the second message including the signed first message, and sending a server certificate verify message, the server certificate verify message comprising the signed first message and the signed second message.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
Conflict-free, stall-free, broadcast networks on neural inference chips are provided. A neural inference chip comprises a plurality of network nodes and a network on chip interconnecting the plurality of network nodes. The network comprises at least one pair of directional paths. The paths of each pair have opposite directions and a common end. The network is configured to accept data at any of the plurality of nodes. The network is configured to propagate data along a first of the pair of directional paths from a source node to the common end of the pair of directional paths and along a second of the pair of directional paths from the common end of the pair of directional paths to one or more destination node..
A first object at a memory address is identified. A first index location in a bitmap that corresponds to that memory address is calculated. A bit is set at the first index location. A pointer to a child object within the first object is detected. A memory address of that child object is identified using the pointer. A second index location in the bitmap that corresponds to that memory address is calculated. A bit is set at the second index location. A bit is also set at a third index location, which is adjacent to the first index location.
Techniques regarding routing qubit data are provided. For example, one or more embodiments described herein can comprise a computer-implemented method for training a quantum controller fast path interface that can control the qubit data routing. The computer-implemented method can comprise training, by a system operatively coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.
The disclosed Josephson junction device (110) includes a lower superconducting layer (210) formed on a substrate (220), a junction layer (240) formed on the lower superconducting material layer, and an upper superconducting layer (230) formed over the junction layer, wherein at least the lower superconducting layer comprises grains having a size that is larger than a size (260) of a Josephson junction. Alternatively, the lower superconducting layer is an alloy, preferably of Al, having an average grain size less than 20 nm and smaller than a length and width of the junction.
A computer-implemented method for detecting and monitoring bias in an application includes index training data and obtaining a plurality of correlation values of one or more features in the indexed training data with a target variable. For each of the one or more features, a first value and a favorable result and a second value along with the unfavorable result is calculated. An absolute value of a difference between the calculated first value and the calculated second value is calculated. A total sum of the calculated absolute value of the plurality of correlation values of the one of the one or more features is calculated.
Devices and/or computer-implemented methods facilitating static ZZ suppression and Purcell loss reduction using mode-selective coupling in two-junction superconducting qubits are provided. In an embodiment, a device can comprise a superconducting bus resonator. The device can further comprise a first superconducting qubit. The device can further comprise a second superconducting qubit, the first superconducting qubit and the second superconducting qubit respectively comprising: a first superconducting pad; a second superconducting pad; a third superconducting pad; a first Josephson Junction coupled to the first superconducting pad and the second superconducting pad; and a second Josephson Junction coupled to the second superconducting pad and the third superconducting pad. The first superconducting pad and the second superconducting pad of the first superconducting qubit and the second superconducting qubit are coupled to the superconducting bus resonator. The superconducting bus resonator entangles the first superconducting qubit and the second superconducting qubit based on receiving a control signal.
An example operation includes one or more of receiving event data from an entity, determining the event data satisfies an endorsement policy, setting an identifier that corresponds to a context of the event data, generating an event which includes the event data and the identifier, and submitting the event for recording in a decentralized database, wherein the identifier is used to validate that a state corresponding to the context in the event data is correct.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
A device package includes a chip carrier having a cavity and one or more microwave waveguides configured to route signals. There is a chip including one or more pads and located within the cavity of the chip carrier. Each pad is aligned with a corresponding connector pad of a microwave waveguide of the one or more microwave waveguides of the chip carrier. At least one of the one or more pads is coupled to the connector pad of the corresponding microwave waveguide by way of an overlap capacitive coupling between the at least one pad and the aligned corresponding connector pad of the microwave waveguide.
Devices and/or computer-implemented methods to facilitate ZZ cancellation between qubits are provided. According to an embodiment, a device can comprise a coupler device that operates in a first oscillating mode and a second oscillating mode. The device can further comprise a first superconducting qubit coupled to the coupler device based on a first oscillating mode structure corresponding to the first oscillating mode and based on a second oscillating mode structure corresponding to the second oscillating mode. The device can further comprise a second superconducting qubit coupled to the coupler device based on the first oscillating mode structure and the second oscillating mode structure.
H03K 19/195 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
45.
TUNABLE QUANTUM COUPLER FACILITATING A QUANTUM GATE BETWEEN QUBITS
Devices and/or computer-implemented methods to facilitate a quantum gate between qubits using a tunable coupler and a capacitor device are provided. According to an embodiment, a quantum coupler device can comprise a tunable coupler coupled between terminals of a same polarity of a first qubit and a second qubit, the tunable coupler configured to control a first coupling between the first qubit and the second qubit. The quantum coupler device can further comprise a capacitor device coupled to terminals of an opposite polarity of the first qubit and the second qubit, the capacitor device configured to provide a second coupling that is opposite in sign relative to the first coupling.
A method for improving lifetime and coherence time of a qubit in a quantum mechanical device includes providing a substrate having at least one qubit formed on the frontside, the at least one qubit having capacitor pads, and removing substrate material from the backside at an area opposite the qubit and/or depositing a superconducting metal layer at the backside area opposite the qubit to reduce radiofrequency electrical current loss due to at least one of silicon-air (SA) interface, metal-air (MA) interface or silicon-metal (SM) interface.
A data storage system includes a plurality of data blocks. A set of data blocks are protected by an erasure correcting code and each of the data blocks in the set of data blocks includes block identification information. The data storage system includes a processor and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to verify the block identification information for each of the data blocks in the set of data blocks at a time of read (1102), and as part of reconstructing a data block, reconstruct the block identification information for the data block and verify the block identification information (1104).
Techniques for selectively tuning the operating frequency of superconducting Josephson junction resonators are provided which include chemically altering a Josephson junction (110) via a plasma treatment, preferably by masked exposure of a transmon qubit die (104) to plasma (502) including reactants such as hydrogen or oxygen. In particular, the plasma treatment adjusts an electrical resistance of the Josephson junction. An apparatus for carrying out the plasma treatment is also disclosed.
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
49.
DRIFT REGULARIZATION TO COUNTERACT VARIATION IN DRIFT COEFFICIENTS FOR ANALOG ACCELERATORS
A drift regularization is provided to counteract variation in drift coefficients in analog neural networks. A method of training an artificial neural network is illustrated. A plurality of weights is randomly initialized. Each of the plurality of weights corresponds to a synapse of an artificial neural network. At least one array of inputs is inputted to the artificial neural network. At least one array of outputs is determined by the artificial neural network based on the at least one array of inputs and the plurality of weights. The at least one array of outputs is compared to ground truth data to determine a first loss. A second loss is determined by adding a drift regularization to the first loss. The drift regularization is positively correlated to variance of the at least one array of outputs. The plurality of weights is updated based on the second loss by backpropagation.
A quantum system includes a qubit array comprising a plurality of qubits. A bus resonator is coupled between at least one pair of qubits in the qubit array. A switch is coupled between the at least one qubit pair of qubits.
Semiconductor device designs having a buried power rail (602) with a sloped epitaxy buried contact (1702) are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate (202); source and drains (906) on opposite sides of the at least one gate, wherein at least one of the source and drains (906) has a sloped surface (1402); a buried power rail (602) embedded in the substrate (202); and a buried contact (1702) that connects the buried power rail (602) to the sloped surface (1402) of the at least one source and drain (906). Sidewall spacers (502) separate the buried power rail (602) from the substrate (202). A top of the sloped surface (1402) of the at least one source and drain (906) is above a top surface of the buried contact (1702).Methods of forming a semiconductor FET device are also provided.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
52.
TARGETED PARTIAL RE-ENRICHMENT OF A CORPUS BASED ON NLP MODEL ENHANCEMENTS
A computer-implemented method include determining that at least one natural language processing (NLP) request is associated with at least one surface form, the NLP request being for a corpus, a database comprising preexisting annotations associated with the corpus. An index query related to the at least one surface form is performed to generate index query results, the index query results including identification of portions of the corpus affected by the NLP request. A scope of the NLP request related to the database is determined based on the index query results, the scope including identification of impacted candidate annotations of the preexisting annotations affected by the NLP request. An NLP service is performed on the corpus according to the scope and the portions, thereby resulting in updates. The updates are committed to the database associated with the corpus.
A method comprises receiving a workload for a computer system; sweeping at least one parameter of the computer system while executing the workload; monitoring one or more characteristics of the computer system while sweeping the at least one parameter, the one or more characteristics including total power consumption of the computer system; generating a power profile for the workload that indicates a respective selected value for the at least one parameter based on analysis of the monitored total power consumption of the computer system while sweeping the at least one parameter, and executing the workload based on the respective selected value of the at least one parameter.
A phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state at one or more second conditions. A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer and a second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and second conditions are different. Therefore, the first and second semiconductor materials can be in different amorphous and/or crystalline states. The layers can have split amorphous/crystalline states. By controlling how the layers are split, the PCD can be in different resistive states.
A method for checking an integrity of an object to be deployed to a cluster is provided. The method detects a resource creation request. The method, responsive to the request being an initial resource creation request for the object, verifies the integrity of the object based on properties in the request to create a release secret in the cluster for a positive integrity verification result for the object. The release secret represents a specific deployment configuration of the object on the cluster. The method, responsive to the request being other than the initial resource request, checks if the request corresponds to the specific deployment configuration of the object by checking against the release secret in the cluster. The method, responsive to the request corresponding to a deployment of the object and the release secret being present in the cluster, creates a resource requested by the request in the cluster.
A hybrid sensor can be generated by training a machine learning model, such as a neural network, based on a training data set. The training data set can include a first time series of upstream sensor data (504, 514, 702, 802) having forward dependence to a target variable (108, 110, 112, 604, 708, 804), a second time series of downstream sensor data (508, 518, 704, 806) having backward dependence to the target variable (108, 110, 112, 604, 708, 804) and a time series of measured target variable (108, 110, 112, 604, 708, 804) data associated with the target variable (108, 110, 112, 604, 708, 804). The target variable (108, 110, 112, 604, 708, 804) has measuring frequency which is lower than the measuring frequencies associated with the upstream sensor data (504, 514, 70, 802) and the downstream sensor data (508, 518, 704, 806). The hybrid sensor can estimate a value of the target variable (108, 110, 112, 604, 708, 804) at a given time, for example, during which no actual measured target variable (108, 110, 112, 604, 708, 804) value is available.
One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p- n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
58.
MULTI-RESONANT COUPLING ARCHITECTURES FOR ZZ INTERACTION REDUCTION
Systems and techniques that facilitate multi-resonant couplers for preserving ZX interaction while reducing ZZ interaction are provided. In various embodiments, a first qubit can have a first operational frequency and a second qubit can have a second operational frequency, and a multi-resonant architecture can couple the first qubit to the second qubit.
G06N 10/00 - Quantum computing, i.e. information processing based on quantum-mechanical phenomena
H03K 5/1252 - Suppression or limitation of noise or interference
H03K 17/92 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of superconductive devices
A computer implemented method for identifying an application topology includes identifying a sandbox environment corresponding to an application of interest, analyzing the sandbox environment to identify a set of communication links between services within the sandbox environment indicating a first topology, identifying a production system corresponding to the application of interest, querying the production system to identify a set of structural dependencies indicating a second topology, and creating a complete topology of the cloud application by combining the first topology and the second topology. A computer program product and computer system for identifying an application topology are additionally disclosed herein.
Implementing a convolutional neural network (CNN) includes configuring a crosspoint array to implement a convolution layer in the CNN. Convolution kernels of the layer are stored in crosspoint devices of the array. Computations for the CNN are performed by iterating a set of operations for a predetermined number of times. The operations include transmitting voltage pulses corresponding to a subpart of a vector of input data to the crosspoint array. The voltage pulses generate electric currents that are representative of performing multiplication operations at the crosspoint device based on weight values stored at the crosspoint devices. A set of integrators accumulates an electric charge based on the output electric currents from the respective crosspoint devices. The crosspoint array outputs the accumulated charge after iterating for the predetermined number of times. The accumulated charge represents a multiply-add result of the vector of input data and the one or more convolution kernels.
Methods and resulting structures for nanosheet devices having asymmetric gate stacks are disclosed. A nanosheet stack (102) is formed over a substrate (104). The nanosheet stack (102) includes alternating semiconductor layers (108) and sacrificial layers (110). A sacrificial liner (202) is formed over the nanosheet stack (102) and a dielectric gate structure (204) is formed over the nanosheet stack (102) and the sacrificial liner (202). A first inner spacer (302) is formed on a sidewall of the sacrificial layers (110). A gate (112) is formed over channel regions of the nanosheet stack (102). The gate (112) includes a conductive bridge that extends over the substrate (104) in a direction orthogonal to the nanosheet stack (102). A second inner spacer (902) is formed on a sidewall of the gate (112). The first inner spacer (302) is formed prior to the gate (112) stack, while the second inner spacer (902) is formed after, and consequently, the gate (112) stack is asymmetrical.
A computer-implemented method is presented for performing Q-learning with language model for unsupervised text summarization. The method includes mapping each word of a sentence into a vector by using word embedding via a deep learning natural language processing model, assigning each of the words to an action and operation status, determining, for each of the words whose operation status represents "unoperated," a status by calculating a local encoding and a global encoding, and concatenating the local encoding and the global encoding, the local encoding calculated based on a vector, an action, and an operation status of the word, and the global encoding calculated based on each of the local encodings of the words in a self-attention fashion, and determining, via an editorial agent, a Q-value for each of the words in terms of each of three actions based on the status.
An artificial intelligence (AI) platform to support a continuous integration and deployment (CI/CD) pipeline for software development and operations (DevOps). One or more dependency graphs are generated based on application artifacts. A machine learning (ML) model is leveraged to capture a relationship between components in the dependency graph (s) and one or more pipeline artifacts. Responsive a change of an application artifact, the captured relationship is leveraged to identify an impact of the detected change on the pipeline artifact (s). The CI/CD pipeline is selectively optimized and executed based on the identified impact to improve the efficiency of the pipeline and the deployment time.
A computer-implemented method is presented for performing matrix sketching by employing an analog crossbar architecture. The method includes low rank updating a first matrix for a first period of time, copying the first matrix into a dynamic correction computing device, switching to a second matrix to low rank update the second matrix for a second period of time, as the second matrix is low rank updated, feeding the first matrix with first stochastic pulses to reset the first matrix back to a first matrix symmetry point, copying the second matrix into the dynamic correction computing device, switching back to the first matrix to low rank update the first matrix for a third period of time, and as the first matrix is low rank updated, feeding the second matrix with second stochastic pulses to reset the second matrix back to a second matrix symmetry point.
Maximum expressivity can be received representing a ratio between maximum and minimum input weights to a neuron of a neural network implementing a weighted real-valued logic gate. Operator arity can be received associated with the neuron. Logical constraints associated with the weighted real-valued logic gate can be determined in terms of weights associated with inputs to the neuron, a threshold-of-truth, and a neuron threshold for activation. The threshold-of-truth can be determined as a parameter used in an activation function of the neuron, based on solving an activation optimization formulated based on the logical constraints, the activation optimization maximizing a product of expressivity representing a distribution width of input weights to the neuron and gradient quality for the neuron given the operator arity and the maximum expressivity. The neural network of logical neurons can be trained using the activation function at the neuron, the activation function using the determined threshold-of-truth.
A method for automatically reducing the dimensionality of a mathematical representation of a controlled application system is provided. The method includes receiving, at a control system, data corresponding to control action and system state variables relating to the controlled application system, fitting a constrained reinforcement learning (CRL) model to the controlled application system based on the data, and automatically identifying a subset of the system state variables by selecting control action variables of interest and identifying system state variables that drive the CRL model to recommend each control action variable of interest. The method also includes automatically performing state space dimensionality reduction of the CRL model using the subset of system state variables, estimating a transition probability matrix for a constrained Markov decision process (CMDP) model of the controlled application system, and formulating the CMDP model as a linear programming (LP) problem using the transition probability matrix and several costs.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
67.
PREDICTION OF PERFORMANCE DEGRADATION WITH NON-LINEAR CHARACTERISTICS
Described are techniques for predicting gradual performance degradation with non-linear characteristics. The techniques including a method comprising inputting a new data sample to a failure prediction model, wherein the failure prediction model is trained using a labeled historical dataset, wherein respective data points are associated with a look-back window and a prediction horizon to create respective training samples, wherein the respective training samples are clustered in a plurality of clusters, and wherein the plurality of clusters are each associated with a normalcy score and an anomaly score. The method further comprises outputting a classification associated with the new data sample based on comparing a first anomaly score of a first cluster of the plurality of clusters that includes the new data sample to an average anomaly score of clusters of the plurality of clusters having the normalcy score greater than the anomaly score.
Provided are techniques for optimized deployment of analytic models in an edge topology. A description of a multi-tiered edge topology with a plurality of nodes, a multimedia stream analytics composition, and performance objectives are received, where the multimedia stream analytics composition includes tasks that use analytic models. The analytic models are optimized and clustered to form clusters of optimized analytic models. A representative optimized analytic model is selected from each of the clusters. A configuration recommendation is determined that indicates deployment of the tasks and of each selected representative optimized analytic model on the plurality of nodes to meet the performance objectives. One or more workflows are generated from the configuration recommendation and executed on the plurality of nodes to generate output for the multimedia stream analytics composition.
An example operation includes one or more of connecting, by an identity provisioning node, a blockchain one to a blockchain two, creating, by an identity provisioning node, an interoperation identity network (IIN) for the blockchain one and for the blockchain two as an instance of a self-sovereign identity (SSI) network, executing a smart contract to: invoke an IIN access control policy, map attributes and permissions of the blockchain one to attributes and permissions of the blockchain two based on the IIN access control policy, and generate a valid verifiable credential (VC) of the IIN in the blockchain one and in the blockchain two based on the mapped attributes and the permissions.
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
A method selectively installs a particular signature on a particular gateway based on the type of signature and the type of computer asset that is protected by that particular gateway. A system and/or analyst receives multiple signatures, where different signatures from the multiple signatures are specific for different types of computer assets. The system and/or analyst identifies and extracts a particular signature, from the multiple signatures, that will protect, if implemented on the appropriate gateway, a particular computer asset. The system and/or analyst identifies the appropriate gateway that protects the particular computer asset, and installs only the extracted particular signature from the multiple signatures on that appropriate gateway.
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A system for configuring and using a logical neural network including a graph syntax tree of formulae in a represented knowledgebase connected to each other via nodes representing each proposition. One neuron exists for each logical connective occurring in each formula and, additionally, one neuron for each unique proposition occurring in any formula. All neurons return pairs of values representing upper and lower bounds on truth values of their corresponding subformulae and propositions. Neurons corresponding to logical connectives accept as input the output of neurons corresponding to their operands and have activation functions configured to match the connectives' truth functions. Neurons corresponding to propositions accept as input the output of neurons established as proofs of bounds on the propositions' truth values and have activation functions configured to aggregate the tightest such bounds. Bidirectional inference permits every occurrence of each proposition in each formula to be used as a potential proof.
In one method of write sort management, a write sort task related to write sorting a write list of data units to be destaged to storage, is assigned to a storage controller to improve the load balance among plural storage controllers. The available processing capacities of each of the storage controllers is determined by, for example, polling each of the storage controllers. A write sort task may then be assigned to a selected storage controller as a function of determined available processing capacities of each of the storage controllers to improve the load balance among the storage controllers.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A method for fabricating a semiconductor structure. The method comprises fabricating a photonic crystal structure (113) of a first material, in particular a first semiconductor material and selectively removing the first material within a predefined part of the photonic crystal structure (113). The method further comprises replacing the first material within the predefined part of the photonic crystal structure (113) with one or more second materials by selective epitaxy. The one or more second materials may be in particular semiconductor materials. A device is obtained by such a method.
A described method includes receiving, by a database system, an instruction to change a first data element in a table in a database, which includes a first copy and a second copy of the table. A first entry is created in a first change-table. The first entry includes an updated value for a first data element. A second entry is created in a second change-table. Creating the second entry includes, changing the updated value into a ciphertext if the first data element is secured, and storing the ciphertext into the second entry. If the first data element is non-secured, the updated value is stored into the second entry as is. The second copy of the table is modified using the second change-table. The second copy of the table is used to respond to subsequent queries.
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
75.
REAL-TIME DETECTION AND CORRECTION OF SHADOWING IN HYPERSPECTRAL RETINAL IMAGES
A method for real-time detection and correction of shadowing in hyperspectral retinal images may include capturing receiving, using a processor, a hyperspectral image of a retina of a patient, detecting, by the processor, a shadow in the hyperspectral image, determining, by the processor that the shadow of the hyperspectral image exceeds a threshold, and in response to determining that the shadow of the hyperspectral image exceeds the threshold, initiating, using the processor, a capture of an additional hyperspectral image of the retina of the patient. Various other methods, systems, and computer-readable media are also disclosed.
A61B 3/12 - Objective types, i.e. instruments for examining the eyes independent of the patients perceptions or reactions for looking at the eye fundus, e.g. ophthalmoscopes
Embodiments are disclosed for a method for a security model. The method includes generating a Bloch sphere based on a system information and event management (SIEM) of a security domain and a structured threat information expression trusted automated exchange of indicator information. The method also includes generating a quantum state probabilities matrix based on the Bloch sphere. Further, the method includes training a security threat model to perform security threat classifications based on the quantum state probabilities matrix. Additionally, the method includes performing a machine learning classification of the security domain based on the quantum state probabilities matrix.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A computer-implemented method according to one aspect includes determining whether an operating system of a node of a distributed computing environment is functioning correctly by sending a first management query to the node; in response to determining that the operating system of the node is not functioning correctly, determining whether the node has an active communication link by sending a second management query to ports associated with the node; and in response to determining that the node has an active communication link, resetting the active communication link for the node by sending a reset request to the ports associated with the node.
Embodiments for implementing an enhanced network stack framework in a computing environment. A plurality of network buffers coherently attached between one or more applications and a network interface may be shared while bypassing one or more drivers and an operating systems using an application buffer, a circular buffer and a queuing and pooling operation.
Disclosed are systems and methods that can facilitate a quantum adaptive execution method based on previous quantum circuits and intermediate results. This can generate an optimized adaptive compilation methodology for a specific backend and the previous quantum circuits dependents and redirect by the job dispatcher to the right quantum backend. Some of the quantum circuits can be dependent on other quantum circuits based on the intermediate results produced by previous circuits. The system can manage the optimization of circuits based on its dependencies and by the results generated by the previous quantum circuits. In this way, the system can get an optimal result for a quantum circuit and inject it to the compiler unit to generate an adaptive compilation result. The resulting post-processing unit is the one in charge to apply this logic and manage the input/output of data to push it in the compiler units and the job dispatcher.
An example system includes a processor to receive concepts extracted from a result set corresponding to a query and result associations for each extracted concept. The processor is to build a graph based on the extracted concepts, wherein the graph comprises a number of nodes representing the extracted concepts and weighted edges representing similarity between concepts extracted from shared results. The processor is to partition the graph into subgraphs with vertices corresponding to candidate facets for vertices having higher sums of weighted edges. The processor is to rank the candidate facets. The processor is to select higher ranked candidate facets to use as facets. The processor is to output facets with a result set in response to the query.
Systems, computer-implemented methods, and computer program products to facilitate generation of microservices from a monolithic application based on runtime traces are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a model component that learns cluster assignments of classes in a monolithic application based on runtime traces of executed test cases. The computer executable components can further comprise a cluster component that employs the model component to generate clusters of the classes based on the cluster assignments to identify one or more microservices of the monolithic application.
A thermal interface material (TIM) structure for directing heat in a three-dimensional space including a TIM sheet (100). The TIM sheet (100) includes a lower portion (102) along a lower plane;a first side portion along a first side plane;a first upper portion along an upper plane;a first fold between the lower portion (102) and the first side portion positioning the first side portion substantially perpendicular to the lower portion (102); and a second fold between the first side portion and the first upper portion positioning the first upper portion on substantially perpendicular to the first side portion and substantially parallel to the lower portion (102).
Pierced thermal interface constructions including a thermal interface material (TIM) structure comprising: a TIM sheet comprising a plurality of piercings, where each of the plurality of piercings comprises a cavity and displaced material, and where the displaced material from each of the plurality of piercings protrudes away from the TIM sheet.
A computing device, method, and system are provided of improving data quality to conserve computational resources. The computing device receives a raw dataset. One or more data quality metric goals corresponding to the received raw dataset are received. A schema of the dataset is determined. An initial set of validation nodes is identified based on the schema of the dataset. The initial set of validation nodes are executed. A next set of validation nodes are iteratively expanded and executed based on the schema of the dataset until a termination criterion is reached. A corrected dataset of the raw dataset is provided based on the iterative execution of the initial and next set of validation nodes.
A method of a primary peer is disclosed, comprising: receiving view change messages which request a view change from a previous primary peer of a blockchain to the primary peer, identifying that a change to a state of the blockchain is in process with the previous primary peer based on metadata of the received view change messages; verifying that the change to the state of the blockchain corresponds to a latest change to the blockchain based on a received view data message; and transmitting a new view message to following peers which includes the in-process change to the state of the blockchain.
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check of credit lines or negative lists
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
86.
DIFFERENTIAL MIXED SIGNAL MULTIPLIER WITH THREE CAPACITORS
A differential mixed-signal logic processor is provided?The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B?Each of plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors?A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors?
A method of generating three-dimensional (3D) spikes. The method comprising receiving a signal comprising time-series data and generating a first two- dimensional (2D) grid. Generating the first 2D grid comprises mapping segments of the time-series data to respective positions of the first 2D grid, and generating, for each position, a spike train corresponding to the respective mapped segment. The method further comprises generating a second 2D grid including performing, for each position, a mathematical operation on the spike train of the corresponding position of the first 2D grid. The method further comprises generating a third 2D grid including performing spatial filtering on the positions of the second 2D grid. The method further comprises generating a 3D grid based on a combination of the first 2D grid, the second 2D grid, and the third 2D grid. The 3D grid comprises one or more 3D spikes.
An example operation includes one or more of receiving, by a data processing node, inference data object from a multi-channel data server over a blockchain, sorting, by the data processing node, longitudinal records contained in the inference data object, linking, by the data processing node, transaction outcomes and inferences data from the inference data object to the sorted longitudinal records, and recording linked data onto a blockchain ledger. The data processing node serves as a validator of data from a robo-advisory using natural language (NL) processing to reduce bias and measure effectiveness of inference from the robo-advisory.
G06F 16/22 - Indexing; Data structures therefor; Storage structures
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database system; Distributed database system architectures therefor
A technique for generating a performance prediction of a machine learning model with uncertainty intervals includes obtaining a first model configured to perform a task and a production dataset?At least one metric predicting a performance of the first model at performing the task on the production dataset is generated using a second model. The second model is a meta-model associated with the first model. At least one value predicting an uncertainty of the at least one metric predicting the performance of the first model at performing the task on the production dataset is generated using a third model. The third model is a meta-meta-model associated with the second model. An indication of the at least one metric predicting the performance of the first model and the at least one value predicting the uncertainty of the at least one metric is provided.
Examples described herein provide a computer-implemented method that includes registering at least one of a plurality of virtual internet protocol addresses (VIPAs) to each of a plurality of network adapters. The method further includes distributing, by each of the plurality of network adapters, inbound data among each of the plurality of network adapters using an address resolution protocol.
Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.
A computer-implemented method for unambiguously identifying entities in a database system may be provided. The method comprises storing data items as records with different attributes in a table of a database, storing naming rules for selected combinations of the attributes of the data items, and prioritizing the naming rules. The method also comprises determining a hash value for each of the selected combinations of the attributes of the data items, and identifying duplicate data items using the determined hash values and the prioritized naming rules.
Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H05K 1/16 - Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
Methods and systems for generating database statistics. Table statistics in a metadata catalog of a source database system are observed, statistics generation costs utilizing a target database system are estimated, and source statistics generation costs utilizing a source database system are estimated. The statistics generation costs are compared and statistics generation queries by the target database system are triggered in response to the statistics generation costs utilizing the target database system having a predefined relationship with the source statistics generation costs utilizing the source database system. The statistics generation queries are performed by the target database system in response to the triggering by the source database system. The generated statistics are sent from the target database system to the source database system, the table statistics in a metadata catalog are updated based on the generated statistics, and the updated table statistics are used to optimize a query plan.
A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.
Reducing attack surface by selectively collocating applications on host computers is provided. System resources utilized by each application running in a plurality of host computers of a data processing environment are measured. Which applications running in the plurality of host computers that utilize similar system resources are determined. Those applications utilizing similar system resources are collocated on respective host computers.
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Technology for managing objects. A method is applied to a set of objects, for example, in view of commissioning such objects. The method includes patterning a surface of each object of a set of objects to be managed. The patterning is accomplished by using hard particles to make indentations in a surface of each object of the set of object, with the pattern formed on each object being a unique physical fingerprint that can be used to identify the object when performing various manage method(s) on the objects
An optical synapse comprises a memristive device for non-volatile storage of a synaptic weight dependent on resistance of the device, and an optical modulator for volatile modulation of optical transmission in a waveguide. The memristive device and optical modulator are connected in control circuitry which is operable, in a write mode, to supply a programming signal to the memristive device to program the synaptic weight and, in a read mode, to supply an electrical signal, dependent on the synaptic weight, to the optical modulator whereby the optical transmission is controlled in a volatile manner in dependence on programmed synaptic weight.
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
99.
OPERATING A SUPERCONDUCTING CHANNEL BY ELECTRON INJECTION
The invention is notably directed to a method of operating a superconducting channel. The method relies on a device including: a potentially superconducting material; a gate electrode; and an electrically insulating medium. A channel is defined by the potentially superconducting material. The gate electrode positioned adjacent to the channel, such that an end surface of the gate electrode faces a portion of the channel. The electrically insulating medium is arranged in such a manner that it electrically insulates the gate electrode from the channel. Rendering the channel superconducting by cooling down the device. Next, a voltage difference is applied between the gate electrode and the channel to inject electrons in the channel through the electrically insulating medium and thereby generate a gate current between the gate electrode and the channel. The electrons are injected with an average energy sufficient to modify a critical current IC of the channel.
A semiconductor structure (100) includes a first semiconductor channel having a plurality of vertical nanowires (106) and a second semiconducting channel having a plurality of vertical nanowires (106). The first semiconducting channel and the second semiconducting channel are configured to be in a stacked configuration. The plurality of vertical nanowires (106) of the first semiconducting channel are configurated to be in alternating positions relative to the plurality of vertical nanowires (106) of the second semiconducting channel.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
patents
