A structure of a circuitry substrate for securing an area from tampering is disclosed. The structure includes a circuitry substrate with at least one of a top tamper enclosure and a bottom tamper enclosure covering a component in a protected area of the circuitry substrate. The top and bottom tamper enclosures are adhesively bonded to a surface of the circuitry substrate, and a tear initiation site is added to a side of the perimeter of circuitry substrate bordering the protected area that includes at least one tamper enclosure, such that the tear initiation site is located and configured to enable propagation of a delamination of at least one internal layer of the circuitry substrate and a severing of a security circuit when a removal force is applied to the at least one of the top tamper enclosure and the bottom tamper enclosure.
A computer implemented method for manipulating an image comprising pixels. A group of processor units creates editable text having changeable text attributes from text in the image. The group of processor units forms a text layer for the image with the editable text created from the text in the image, wherein the editable text is located in text positions in the text layer corresponding to positions of the text in the image. The group of processor units creates a set of editable shapes having changeable shape attributes, wherein the set of editable shapes correspond to a set of shapes in the image. The group of processor units forms a shape layer for the image with the set of editable shapes. The set of editable shapes have a set of shape positions in the shape layer that correspond to a set of positions of the set of shapes in the image.
Methods, systems (126), and computer program products for domain adaptive speech recognition using artificial intelligence are provided herein. A computer-implemented method includes generating a set of language data candidates, each language data candidate comprising one or more graphemes, by processing a sequence of phonemes related to input speech data using an artificial intelligence-based data conversion model (104) (302); determining, for a target pair of phonemes and graphemes, a subset of graphemes from the set of language data candidates (304); generating a first speech recognition output by processing the subset of graphemes using at least one biasing language model (108) and an artificial intelligence-based speech recognition model (306); generating a second speech recognition output by replacing at least a portion of the subset of graphemes in the first speech recognition output with at least one of the graphemes from the target pair (308); and performing automated actions based on the second speech recognition output (310).
Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor having multiple qubits. The system includes an array of light emitting sources. Each light emitting source is aligned with a qubit on the quantum processor. The system includes a controller configured to receive a selection of a qubit and to enable a light emitting source from the array of light emitting sources to emit light to the selected qubit. The light is use to scramble strongly coupled two- level systems (TLSs) in the quantum processor.
Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system uses an iterative process of applying light pulses and examining qubit relaxation times to eliminate or minimize two-level system (TLS) interaction with qubits. The system applies a first light pulse to illuminate a quantum processor having one or more qubits. The system receives qubit relaxation times that are measured at different electric field frequencies after applying the first light pulse. The system applies a second light pulse to illuminate the quantum processor upon determining that the received qubit relaxation times indicates presence of a strongly coupled TLS in the quantum processor.
A system, method, and computer program product perform audio-visual inspection at a surface of a liquid over machinery that is operating under the surface. The audio-visual inspection includes each of feeding surface wave movements into a neural network, feeding bubble formation pattern into the neural network, feeding bubble dimensions into the neural network, and feeding underwater acoustic information to the neural network. The system, method, and computer program product further identify, using the neural network, a statistical anomaly from the audio-visual inspection indicating an anomaly of the performance of the machinery.
A computer-implemented method, system and computer program product for recommending design changes in designing a digital integrated circuit. An analysis of the digital integrated circuit being designed is performed, where the result of such an analysis involves violations being identified and stored. A stored violation, such as a cross-domain, cross-hierarchy and multi-cycle violation, may then be analyzed to identify a root cause of the violation using a rule. Such a rule may be used for triaging various failures in the cross-domain, cross-hierarchy and/or multi-cycle violation of the digital integrated circuit. A design change in the design of the digital integrated circuit may then be recommended based on the identified root cause of the violation. In this manner, the root cause of failures are effectively identified in the design of digital integrated circuits using an offline analysis of cross-domain, cross-hierarchy and/or multi-cycle violations using a rules-based approach.
Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system includes a quantum processor comprising a plurality of qubits. The system includes a light emitting source that can be tuned to produce light pulses of different wavelengths. The system includes an array of bandpass filters. Each bandpass filter is aligned with a qubit on the quantum processor and has a unique pass band. The system may include a controller configured to receive a selection of a qubit and to tune the light emitting source to emit a light pulse having a wavelength that falls within a range of a bandpass filter that is aligned with the selected qubit. The light pulse is used to scramble an ensemble of strongly coupled two-level system (TLS) in the processor.
Identifying an indistinct entity within an image can include generating by an image filter multiple gradients, each of which corresponds to one of a plurality of pixels of an image captured by an imager. The image can be searched for a likely repeating pattern. Responsive to detecting, based on the multiple gradients, a likely repeating pattern within the image, data structures can be generated, the data structures comprising a set of probabilistically weighted feature vectors corresponding to the likely repeating pattern. A machine learning model can classify each of the set of probabilistically weighted feature vectors. An identity of the likely repeating pattern can be output, the identity based on the machine learning model classifications of the probabilistically weighted feature vectors.
A semiconductor device includes backside power rails located between N channel field effect transistor to N channel field effect transistor spaces, and between at least one P channel field effect transistor to P channel field effect transistor space; and backside local signal lines located between the backside power rails.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
A semiconductor structure is presented including a bottom field effect transistor (FET) including a plurality of bottom source/drain (S/D) epi regions, a top FET including a plurality of top S/D epi regions, a bonding dielectric layer disposed directly between the bottom FET and the top FET, and a node contact advantageously extending from a bottom S/D epi region of the plurality of bottom S/D epi regions of the bottom FET through the bonding dielectric layer and into the top FET. The bottom FET includes an inverter gate. The top FET electrically connects to back-end-of-line (BEOL) components and the bottom FET electrically connects to a backside power delivery network (BSPDN).
Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.
Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.
Tasks are selected for hibernation by recording user preferences for tasks having no penalty for hibernation and sleep; and assigning thresholds for battery power at which tasks are selected for a least one of hibernation and sleep. The assigning of the thresholds for battery power include considering current usage of hardware resources by a user and battery health per battery segment. A penalty score is determined for tasks based upon the user preferences for tasks having no penalty, and task performance including at least one of frequency of utilization, memory utilization, task dependency characteristics and task memory hierarchy. The penalty performance is a value including both the user preference and the task performance. Tasks can then be put into at least one of hibernation mode and sleep mode dictated by their penalty performance during the thresholds for battery power.
The present specification describes a computer-implemented method. A first comparison test is executed to determine whether an unknown object is of a first sub-class of a class of objects. Responsive to determining that the unknown object is not of the first sub-class, it is determined whether the unknown object is an instance of a second sub-class by determining whether there are additional sub-classes other than the first sub-class and a second sub-class. Responsive to determining that there are additional sub-classes, the second code fragment executes while refraining from assuming the unknown object is of a particular sub-class.
A memory device includes a substrate and vertically stacked ferroelectric capacitors formed on the substrate. A first ferroelectric capacitor has a different capacitive output than a second ferroelectric capacitor when a constant voltage is applied. First and second electrodes are in electrical contact with the vertically stacked ferroelectric capacitors. In some instances, a first capacitor plate in the first ferroelectric capacitor and a second capacitor plate in the second ferroelectric capacitor have different thicknesses. The different thicknesses allow the capacitive output for each capacitor to produce different electric field outputs. Accordingly, a combination of different output signals can be produced based on different threshold voltage levels for each capacitor contributing to the output.
Photonic content-addressable memories (CAMs) and applications thereof are provided. The CAM includes a photonic cross-bar array comprising a plurality of row and column waveguides, and a plurality of photonic filter devices. Each filter device is selectively programmable in first and second states representing respective stored bit values that filters out light according to the programming. An encoder for encoding a plurality of input bit-strings into optical signals such that bit values in different bit-strings are encoded using optical signals in different pairs of optical states, and to simultaneously supply the optical signals corresponding to each bit-position in the bit-strings to a respective row waveguide of the array. The CAM further comprises a detector for detecting light in any of said optical states in each column waveguide, thereby identifying any mismatch between each input bit-string and bit values stored in the filter devices coupling light to that waveguide.
G11C 15/00 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
18.
VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS WITH HIGH PERFORMANCE OUTPUT
A vertical-transport field-effect transistor (VTFET) is on a wafer. The VTFET has a first width. The first width is a contacted poly pitch (CPP). A bottom source/drain region of the VTFET extends at least the first width from the VTFET. A contact from a frontside of the VTFET is connected to the bottom source/drain region.
A semiconductor structure includes a first source-drain region; a second source-drain region; at least one channel region coupling the first and second source-drain regions; and a gate adjacent the at least one channel region. A bottom dielectric isolation region is located inward of the gate. First and second bottom silicon regions are respectively located inward of the first and second source-drain regions. A back side contact projects through the second bottom silicon region into the second source-drain region.
Embodiments are disclosed for a three-terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device. The three-terminal SOT MRAM device includes a first type field effect transistor (FET) that drives an SOT line. Additionally, the first type FET includes a write gate in electrical contact with a write wordline (WWL). Further, the device also includes a second type FET in electrical contact with a magnetic tunnel junction (MTJ). Also, the second type FET comprises a read gate in electrical contact with a read wordline (RWL). Additionally, the first type FET is disposed above the second type FET. Further, the three-terminal SOT MRAM device provides a density of three contacted poly pitch (CPP) per two cells.
A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.
A method for data transfer from a legacy system to a modernized application alternative to the legacy system is provided. A Robotic Process Automation (RPA) agent monitors incoming legacy payloads. The RPA agent creates an integration pathway from the legacy system to the modernized application alternative to the legacy system. The RPA agent intercepts the incoming legacy payloads using any of payload injection, cancellation, or workflow interruption by integrating the RPA agent at a User Interface (UI) or an Application Programming Interface (API) level. The RPA agent captures the incoming legacy payloads. The RPA agent executes a determination of heritage, modernized, or mixed origination. The method also includes installing, through the integration pathway under a control of the RPA agent, portions of the legacy system corresponding to the incoming legacy payloads into the modernized application alternative to the legacy system responsive to the determination of heritage, modernized, or mixed origination.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
23.
INTELLIGENT ASSIGNMENT OF ROBOTIC EDGE DEVICES IN AN EDGE COMPUTING ECOSYSTEM
Provided is a computer-implemented method, system, and computer program product for intelligently assigning robotic edge devices to perform a task using an edge computing ecosystem. A processor may identify a plurality of robotic edge devices in a geographic location. The processor may determine attributes for each robotic edge device of the plurality of robotic edge devices. The processor may identify a task to be performed at the geographic location by the plurality of robotic edge devices. The processor may determine, based on the attributes, a subset of robotic edge devices that are capable of completing the task. The processor may assign the subset of robotic edge devices to complete the task.
A computer implemented method for automated generation and verification of a technology specific logic model and a technology independent logic model of a memory array, the method at least comprising: having a first set of parameters; having a set of constraints, creating a second set of parameters; generating the technology independent model of the memory array wherein the second set of parameters and the set of constraints are used; generating the technology specific model of the memory array wherein the first set of parameters and the set of constraints are used; verifying the technology independent model and the technology specific model for equivalence on a sequential logic basis.
Embodiments of the present invention are directed to monolithic stacked field effect transistor (SFET) processing methods and resulting structures having dual middle dielectric isolation (MDI) separation. In a non-limiting embodiment of the invention, a first nanosheet is formed and a second nanosheet is vertically stacked over the first nanosheet. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet and a middle dielectric isolation structure is formed between the first nanosheet and the second nanosheet. The middle dielectric isolation structure includes a first middle dielectric isolation layer and a second middle dielectric isolation layer vertically stacked over the first middle dielectric isolation layer. A portion of the gate extends between the first middle dielectric isolation layer and the second middle dielectric isolation layer in the middle dielectric isolation structure.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
A VTFET is on a wafer and a backside power delivery network is on a backside of the wafer. A first backside contact is connected to a gate of the VTFET and a first portion of the backside power delivery network. The VTFET has a first width and the first width is a contacted poly pitch (CPP). The first backside contact may be at least the first width from the VTFET. The first backside contact may be double the first width from the VTFET.
A first VTFET is provided on a wafer. A second VTFET is adjacent to the first VTFET on the wafer. A backside power deliver network is on a backside of the wafer. A shared frontside contact is on a frontside of the wafer. The shared frontside contact is connected to a first top source/drain region of the first VTFET, a second top source/drain region of the second VTFET, and the backside power delivery network.
Facilitating transfer of data from a first machine and/or computing system to at least a second machine and/or computing system in instances where traditional data transfer methods (such as using a communications network) are not immediately feasible is achieved by identifying a triggering event for physical transport of data, collecting the data to be transported, and transferring the data. Secure transfer of the collected data is achieved via encryption of the collected data.
A magnetic random access memory (MRAM) apparatus includes a magnetic tunnel junction (MTJ) stack; a spin-orbit-torque (SOT) layer that underlies the MTJ stack; and a dielectric pillar that underlies the SOT layer and the MTJ stack. The SOT layer has a stepped profile.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
A hybrid bonded semiconductor structure includes a first substrate and a second substrate each having an interface joined in a hybrid bond. Each substrate has a die portion and a crackstop structure adjacent the die portion. One or more voids in the first substrate and the second substrate are formed in or about a portion of a periphery of each crackstop structure. At least some of the one or more voids in the first substrate and the second substrate are substantially aligned to form a unified void with airgaps across the hybrid bond interface.
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer
An example operation may include one or more of invoking, via an operating system, execution of a plurality of software programs having a first mode of operation that causes the plurality of software programs to operate in a first resource consuming mode, monitoring physical resources of a computing device that are consumed by the plurality of software programs, determining to reduce or allow expanded consumption of the physical resources of the computing device by the plurality of software programs based on the monitored physical resources, and in response to the determination, switching from a first mode of operation of a software program from among the plurality of software programs and to a second mode of operation of the software program that causes the software program to operate in a second resource consuming mode that consumes either less or more physical resources than the first resource consuming mode.
A magnetoresistive random access memory (MRAM) structure is provided. The MRAM structure includes a chiral spin-orbit-torque (SOT) metal bottom electrode (18) under the magnetic free layer (26) where the chiral SOT metal bottom electrode (18) is surrounded by a via dielectric material structure (24). The chiral SOT metal bottom electrode (18) enables a charge current direction, a spin current direction and a spin polarization direction to be in the same direction which is perpendicular to a horizontal surface of the chiral SOT metal bottom electrode (18).
A computer implemented method, apparatus, system, and computer program product manages updates to images. A computer system determines shared layers present between the images selected for update management. The images comprise executable code that are run to create containers. The computer system detects a change in a shared layer in the shared layers for an image in the images. The computer system updates the shared layer in the shared layers in a set of the images having the shared layer in response to detecting the change to the shared layer for the image. According to other illustrative embodiments, a computer system and a computer program product for managing updates to images are provided.
In an approach for enhancing an experience of a user listening to and/or watching an audio-visual content by modifying future audio and/or video frames of the audio-visual content, a processor captures a set of sensor data from an IoT device worn by the first user. A processor analyzes the set of sensor data to generate one or more connotations by converting the emotion using an emotional vector analytics technique and a supervised machine learning technique. A processor scores the one or more connotations on a basis of similarity between the emotion exhibited by the first user and an emotion expected to be provoked by a second user. A processor determines whether a score of the one or more connotations exceeds a pre-configured threshold level. Responsive to determining the score does not exceed the pre-configured threshold level, a processor generates a suggestion for the producer of the audio-visual content.
H04N 21/442 - Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed or the storage space available from the internal hard disk
36.
POWER GATING DUMMY POWER TRANSISTORS FOR BACK SIDE POWER DELIVERY NETWORKS
A semiconductor chip device includes a substrate with a back end of line layer and a backside power delivery network. An input power line is electrically coupled to the backside power delivery network. Dummy transistors are positioned in a circuit with analog or digital circuit elements. A power gating transistor is positioned in the circuit between the dummy transistors and the analog or digital circuit elements. Power from the power input line is provided from the backside power delivery network, through the dummy transistors, and controlled by the power gating transistor for transfer to the analog or digital circuit elements. The device uses a backside delivery of power to the area of the dummy transistors to transfer power into the analog or digital circuit elements, which leaves more of the front side footprint for functional devices.
H01L 23/528 - Layout of the interconnection structure
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
37.
VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTOR WITH BACKSIDE SOURCE/DRAIN CONNECTIONS
A VTFET is provided on a wafer. A backside power delivery network is on a backside of the wafer. A first backside contact is connected to a bottom source/drain region of the VTFET and a first portion of the backside power delivery network. A second backside contact is connected to top source/drain region of the VTFET and a second portion of the backside power delivery network.
Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.
Improving the runtime and discovery recovery performance for cloud-based logical volume management systems when performing mirror write operations. A mirror write consistency check (MWCC) policy that incorporates aspects of Active MWCC policies and Passive MWCC policies are utilized to more efficiently ensure that data is properly mirrored from a first copy of a logical volume to the second copy of a logical volume (as well as to potentially multiple other copies of the logical volume).
An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
An embodiment includes analyzing text content of a user query to identify via natural language processing (NLP) a query topic. The embodiment maps the query topic to a topic cluster at a node of a hierarchical model of a text database. The embodiment generates query demand data indicative of demand for the topic cluster based on user queries. The embodiment identifies the topic cluster as a topic-cache candidate based on the query demand data. The embodiment compares an amount of memory required for storing text associated with the first topic cluster to available cache memory. The embodiment caches the text of the topic cluster candidate upon determining that there is sufficient available cache memory space.
Systems and methods for operating a beamforming circuit are described. A processor can activate a transmitting element among a plurality of transmitting elements of a beamforming circuit. The processor can activate a receiving element among a plurality of receiving elements of a beamforming circuit. The processor can receive a direct current (DC) signal that represents phase and amplitude of the activated transmitting element and the activated receiving element. The processor can adjust a setting of the beamforming circuit to receive additional DC signals that represent phases and amplitudes of the activated transmitting element and the activated receiving element under the adjusted setting. The processor can determine calibration values for the beamforming circuit based on the DC signal and the additional DC signals.
H04B 7/0408 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas using two or more beams, i.e. beam diversity
43.
TESTING OF OPERATING SYSTEM (OS) KERNEL HELPER FUNCTIONS ACCESSIBLE THROUGH EXTENDED BPF (EBPF) FILTERS
A method to test an OS kernel interface, such as an eBPF helper function. The interface has a grammar that defines the kernel interface. Testing is carried out using eBPF code that invokes and tests the interface using a fuzzing engine. To facilitate the process, additional user space code is configured to generate at least one kernel event that triggers the eBPF code to run, and to transform inputs from the fuzzing engine according to the grammar that defines the kernel interface. After loading the eBPF code into the OS kernel, the user space code issues the kernel event that causes the eBPF code to run. In response, and as the fuzzing engine executes, the eBPF code records arguments sent to the OS kernel through the kernel interface. The arguments are passed through a data structure shared by the eBPF code and the user space code. By recording the arguments and other diagnostic information, the security of the kernel interface is evaluated.
According to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. The present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/528 - Layout of the interconnection structure
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Semiconductor devices and methods of making the same include a first lower device and a second lower device on a substrate. A first upper device is over the first lower device and a second upper device is over the second lower device. A first lower contact extends from a height above the first upper device and makes electrical contact with a top surface and a sidewall surface of the first lower device. A second lower contact extends from a height above the second upper device and makes electrical contact with a top surface and a sidewall surface of the second lower device. An insulating barrier is between the first lower contact and the second lower contact.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A method includes, in response to receiving an incoming service request and establishing a call chain of pods of a service mesh network, setting a retry locker parameter to a locked state for each pod in the call chain. A locked retry locker parameter prevents the pod from initiating retries of a service request. The method includes, in response to determining that a pod in the call chain is unavailable, setting the retry locker parameter to an unlocked state for a previous pod just prior to the pod that is unavailable. The unlocked state allows a retry to the pod that is unavailable. In response to the previous pod reaching a retry limit, the method includes setting the retry locker parameter to unlocked for each pod in the call chain and sending a service termination message to a service requester.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
H04L 67/566 - Grouping or aggregating service requests, e.g. for unified processing
H04L 69/40 - Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass for recovering from a failure of a protocol instance or entity, e.g. service redundancy protocols, protocol state redundancy or protocol service redirection
A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.
H10N 69/00 - Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group
G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
H01P 3/02 - Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01P 5/02 - Coupling devices of the waveguide type with invariable factor of coupling
A phase change memory structure with improved sidewall heater and formation thereof may be presented. Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in the active region of the cell. Presented herein may be a side wall heater, where the upper section extends through bilayer dielectric to contact a phase change material layer and the lower section of the sidewall heater has conductive layers in contact with the bottom electrode. The width of the sidewall heater may reflect an inverted T shape reducing the current requirement to reset the phase change material.
A semiconductor device includes a nanosheet stack on a substrate. A first source/drain is on a first side of the nanosheet stack and a second source/drain is on an opposing side of the nanosheet stack. A backside contact includes a first contact end on a first end of the first source/drain and an opposing second contact end in electrical communication with a backside power distribution network. A frontside contact includes a first contact end on a first end of the second source/drain and an opposing second contact end in electrical communication with a backend of line (BEOL) interconnect. A placeholder extends from an opposing second end of the second source/drain.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Using exported data of a machine learning model and a model training environment specification, a resource usage specification and a code module usage specification of the model are identified. A code module installation specification is determined from a code module requirements specification and a target execution environment specification. The code modules specified by the code module installation specification are caused to be installed in the target execution environment. Using data of the updated target execution environment, the updated target execution environment is validated for execution of the model. Execution of the model in the updated target execution environment is simulated. The model is deployed in the updated target execution environment responsive to the simulating being successful.
A computer-implemented method for executing a serverless workload on a transient infrastructure is disclosed. The method comprises receiving a request for executing a workload and at least one policy, selecting an infrastructure component of the transient infrastructure for an execution of the workload, wherein the transient infrastructure is implemented utilizing a plurality of geographically distributed computing nodes, and executing the workload on the transient infrastructure. Furthermore, the method comprises upon receiving an interfering event during the execution of the workload causing a stop of the workload execution, freezing the execution of the workload, storing intermediate results and statuses of the workload execution in a cross-domain storage system, terminating the execution of the workload, and continuing the workload execution using the intermediate results and under a constraint defined by the at least one policy.
To limit resistance variability across a resistive random-access memory (RRAM) call, the disclosure includes an RRAM cell with a resistance spreading layer within the RRAM cell between the top and bottom electrodes of the RRAM cell. The resistance spreading layer is in series with and has no impedance with a filament forming layer of the RRAM cell. The resistance spreading layer may be below the filament forming layer or the resistance spreading layer may be above the filament forming layer. The resistance spreading layer may further be in series with and has no impedance with the bottom electrode or the top electrode.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
54.
AUTO-WRAPPERING TOOLS WITH GUIDANCE FROM EXEMPLAR COMMANDS
Information received from a graphical user interface (GUI) and a list of user-curated command line patterns are received by an auto-wrapper system, wherein the auto-wrapper system is associated with an analytics workflow service. A module including a parameter space having one or more parameters and options used in the list of user-curated command line patterns is generated, by the auto-wrapper system, wherein content for each parameter is derived from the parameter's presence in the list of user-curated command line patterns combined with the information received from a GUI.
Mechanisms are provided for dispatching requests to service instances based on data storage boundaries. A request specifying an identity is received and dispatched to a service instance of a data storage boundary, where each data storage boundary is defined by a regulation or policy restricting data storage of specific types of data to computing devices within a specified boundary. A feedback response, specifying a target location, is received from the service instance in response to determining that the service instance cannot access the data because the data is associated with a different data storage boundary. A dynamic dispatch rule specifying the identity and the target location is generated and a subsequent request specifying the identity is processed by executing this dynamic dispatch rule to dispatch the subsequent request directly to a service instance associated with the target location.
A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region (28) located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region (46) located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure (32) located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure (52) located adjacent to at least one of the second source/drain regions of at one of the second FETs.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
58.
BUILD ENVIRONMENT FOR SOFTWARE DEVELOPMENT, SECURITY, AND OPERATIONS
Aspects of the present disclosure relate generally to software development environments and, more particularly, to systems, computer program products, and methods of automating software development, security, and operations (DevSecOps). For example, a computer- implemented method includes receiving, by a processor, a plurality of infrastructure as code files specifying a configuration of a runtime environment for a deployable image of source code in a continuous integration and continuous delivery pipeline for a cloud platform; generating, by the processor, compliance code for at least one file of the plurality of infrastructure as code files; building, by the processor, the deployable image of the source code in the continuous integration and continuous delivery pipeline according to the configuration specified by the plurality of infrastructure as code files and the compliance code; and deploying, by the processor, an instance of the image in the runtime environment.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
59.
SUB-EUV PATTERNING HEATERS FOR BAR MUSHROOM CELL PCM
A phase change material (PCM) memory cell having a metal heater element of sub-EUV dimension. The PCM memory cell includes a bottom electrode of a metal-containing material, a memory cell structure including a phase change material; and a metal heater element of sub-extreme ultraviolet (sub-EUV) dimension situated between and electrically connecting the bottom electrode and PCM memory cell structure. The metal heater element is formed of a circular via structure of sub-EUV dimension and has a seamless metal-nitride fill material. The circular via structure of sub-extreme ultraviolet (sub-EUV) dimension further includes a metal-nitride liner of sub-EUV dimension, the metal-nitride liner of sub-EUV dimension including a thicker metal-nitride liner bottom surface portion and thinner sidewall metal-nitride portions. The thicker metal-nitride liner bottom surface portion improves heat insulation and provides for high resistance/low power switching and reduced amorphous phase change material volumes.
A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.
Examples described herein provide a computer-implemented method that includes training a machine learning model. The model is trained by generating a set of training queries using at least one of a query workload and relationships between tables in a database, building a query graph for each of the set of training queries, computing, for each training query of the set of training queries, a selectivity based at least in part on the query graph, and building, based at least in part on the set of training queries, an initial join result distribution as a collection of query graphs.
Deriving insights from time series data can include receiving subject matter expert (SME) input characterizing one or more aspects of a time series. A model template that specifies one or more components of the time series can be generated by translating the SME input using a rule-based translator. A machine learning model based on the model template can be a multilayer neural network having one or more component definition layers, each configured to extract one of the one or more components from time series data input corresponding to an instantiation of the time series. With respect to a decision generated by the machine learning model based on the time series data input, a component-wise contribution of each of the one or more components to the decision can be determined. An output can be generated, the output including the component-wise contribution of at least one of the one or more components.
G06N 3/0442 - Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
63.
TRANSFORMING AN APPLICATION INTO A MICROSERVICE ARCHITECTURE
A system transforms an application for a distributed computing environment is provided. The system comprises one or more memories, and at least one processor coupled to the one or more memories. The system analyzes a description of user intent to extract information for transforming the application. The extracted information indicates functionalities for the distributed computing environment. A plurality of software artifacts of the application are mapped to the functionalities. The plurality of software artifacts form different groups of software artifacts. Remaining software artifacts of the application are assigned into the different groups based on a remaining software artifact corresponding to a mapped software artifact of a group. The different groups correspond to microservices for the distributed computing environment. The microservices for the distributed computing environment are presented based on the different groups.
An apparatus comprising a backside power distribution network; a backside power rail joined to the backside power distribution network; and a backside contact via that couples at least one front end of line transistor to the backside power rail; wherein the backside contact via comprises a pillar based memory device.
A semiconductor device and methods forming the device is disclosed. The semiconductor device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and a top electrode (136,236) on the MTJ stack. At least one of the bottom electrode and the top electrode (136,236) includes doped SiGeSn.
A controller obtains data stored in one or more data structures generated based on a defined task to be performed for a selected event. The data includes a set of constraints for the defined task. One or more task solutions generated for the defined task using the provided data are obtained. A determination is made as to whether the one or more task solutions include a task solution that satisfies one or more defined criteria. Based on determining that the one or more task solutions do not include the task solution that satisfies the one or more defined criteria, the set of constraints is automatically adjusted to provide an adjusted set of constraints. The adjusted set of constraints is to be automatically provided to a solution generator to be used to obtain the task solution that satisfies the one or more defined criteria.
A computer implemented method includes receiving a list of areas on a subject tape to be read, wherein each area of the list of areas is indicated by a first record number and a last record number corresponding to the area, identifying parameters of a tape drive configured to read the subject tape, wherein the identified parameters of the tape drive contribute to a speed with which the tape drive can read the list of areas, creating a directed graph of the areas on the subject tape based on the identified parameters, wherein the directed graph indicates how long the tape drive will take to read the areas on the subject tape, and determining a fastest reading order of the areas on the subject tape, based, at least in part, on the directed graph and the identified parameters. A computer program product and computer system are also disclosed.
A method, computer system, and a computer program product for ontology adaptation is provided. The present invention may include constructing a process ontology for an industrial floor. The present invention may include generating a digital twin of the industrial floor. The present invention may include performing a simulation of the digital twin using the process ontology. The present invention may include generating one or more new process ontologies based on inefficiencies identified during the simulation. The present invention may include providing one or more recommendations to a user.
G06Q 10/0637 - Strategic management or analysis, e.g. setting a goal or target of an organisation; Planning actions based on goals; Analysis or evaluation of effectiveness of goals
69.
VIRTUAL MACHINE FAILOVER WITH DISAGGREGATED SHARED MEMORY
According to an aspect, a computer-implemented method includes operating a program on a virtual machine on a first device having a local cache memory. Based on a determination that an epoch timer has not expired, aspects include writing one or more updates to the local cache memory and transmitting evicted items from the local cache memory to a shared memory device that is separate from the first device. Based on a determination that an epoch timer has expired, aspects include flushing the local cache memory to the shared memory device, transmitting a virtual CPU state of the virtual machine to the shared memory device, and resetting the epoch timer.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
70.
HETEROGENEOUS GATE ALL AROUND DIELECTRIC THICKNESS
A semiconductor includes a first GAA FET (303) and second GAA FET (305). The second GAA FET includes a first gate dielectric (391) and second gate dielectric (472) within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor (392) within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor (395) within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A 3D compute-in-memory accelerator system (100) and method for efficient inference of Mixture of Expert (MoE) neural network models. The system includes a plurality of compute-in-memory cores (102), each in-memory core including multiple tiers of in-memory compute cells (106). One or more tiers of in-memory compute cells correspond to an expert sub-model of the MoE model. One or more expert sub¬ models are selected (106A) for activation propagation based on a function-based routing (115), the tiers of the corresponding experts being activated based on this function. In one embodiment, this function is a hash-based tier selection function used for dynamic routing of inputs and output activations. In embodiments, the function is applied to select a single expert or multiple experts with input data- based or with layer-activation-based MoEs for single tier activation. Further, the system is configured as a multi-model system with single expert model selection or with a multi-model system with multi-expert selection.
G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
G06G 7/16 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for multiplication or division
A voltage source watchdog comprising a passive device is placed in series between a voltage source and a load. The passive device includes an electromigration (EM) joint of known materials that will create an electromigration void after a specified amount of current passes through the EM joint. After a known amount of current as passed through, a void is created and a voltage will no longer be sensed, thus providing a sure safety mode situation. When the voltage source is a battery, the battery life may be extended by selectively enabling voltage measurement operations for the proposed watchdog.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/62 - Protection against overcurrent or overload, e.g. fuses, shunts
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
73.
LOW LOSS TRAVELLING WAVE PARAMETRIC DEVICES USING PLANAR CAPACITORS
A travelling wave parametric device (TWPD) and a method of manufacturing a TWPD, which includes forming a superconducting junction (160) on a substrate. Trenches are etched away through a metal surface and into a layer of dielectric material. The trenches define a plurality of fingers positioned in an interdigitated arrangement of capacitors defined by a metal and a dielectric material (160) that remains from the etched away metal surface and the layer of dielectric material.
A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
75.
GENERATING DC OFFSETS IN FLUX-TUNABLE TRANSMONS WITH PERSISTENT CURRENT LOOPS
A quantum circuit device (200) includes a qubit chip including a plurality of qubits (220) and a plurality of flux tunable couplers (225). A plurality of fixed frequency qubits are arranged in in a lattice structure, wherein each pair of the plurality of fixed frequency qubits is coupled to one flux tunable coupler. A wiring layer is coupled to the qubit chip, and the wiring layer includes a loop (210) constructed of a superconducting material that is inductively coupled to the flux tunable couplers. A flux bias line (205) is constructed of a superconducting material that is different than the superconducting material of the loop, wherein the flux bias line is inductively coupled to both the loop and the flux tunable couplers.
A method, computer system, and computer program product for self-development of resources are provided. The method may include receiving data relating to an activity and a first robotic device assigned to perform the activity. The method may also include creating a knowledge corpus of a second set of one or more robotic devices capable of performing the activity. The method may further include executing a digital twin simulation of a digital twin model of the first robotic device performing the activity. The method may also include in response to determining the first robotic device is unable to complete the activity without incident, identifying within the second set of one or more robotic devices a most comparable robotic device to the first robotic device. The method may further include predicting a modification of the first robotic device. The method may also include attaching one or more resources printed by a 3D printer to the first robotic device.
An IC memory device includes a substrate and an array of memory cells on the substrate. Each memory cell includes at least one memory cell transistor in a layer of the device adjacent to the substrate. In the same layer, the device also includes a plurality of shunt transistors. The device also includes a buried metal signal rail, which is disposed between the array of memory cells and the plurality of shunt transistors in a buried layer that is embedded into the substrate below the transistors. The device also includes single-layer vias, which are in same layer as the transistors and electrically connect the memory cell transistors to the shunt transistors through the buried metal signal rail.
A grain-boundary self-aligned resistive memory structure is provided enabling the closely-packed formation of multiple, oxide-based, ReRAM elements in parallel, each with its own compliance resistor. The structure is capable of forming multiple filaments, one per element, with the aim of reducing the variability in the composite ReRAM cell.
A method for acoustic damping of sound clips includes identifying an audio clip for a location of a user in an environment and fragmenting the audio clip into a plurality of sound clips. The method further includes, responsive to determining at least one sound clip from the audio clip requires acoustic damping, performing the acoustic damping on the at least one sound clip, where a damping ratio for the at least one sound clip is altered. The method further includes responsive to determining to stitch the plurality of sound clips, stitching the plurality of sounds clips to form the audio clip, where the plurality of sound clips includes the at least one sound clip with the acoustic damping. The method further includes displaying a visual representation of the audio clip with the plurality of sound clips.
xyy cladded channels, Si channels, or the like) (382, 386, 390). The GAA FETs may have different channel structures, such as relatively different channel lengths. The heterogenous channels may provide improved GAA FET device performance by allowing an ability to tune or adjust channel mobility of GAA FETs in similar region types in different locations or when utilized in different applications.
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.
A non-volatile memory (NVM) structure is provided including a proximity heater or a localized heater that is configured to generate Joule heating to increase temperature of a ferroelectric material layer of a ferroelectric memory device higher than a Currie temperature of the ferroelectric material layer. The Joule heating is trigged when tampering in the NVM structure is detected and as a result of the Joule heating memory erasure can occur.
A semiconductor structure having improved performance is provided that includes a local enlarged via-to-backside power rail (VBPR) contact structure which connects a source/drain region of one field effect transistor (FET) to a backside power rail.
Techniques and couplers for managing coupling between qubits are presented. A first tuneable coupler qubit (TCQ) can comprise a first frequency mode and a second frequency mode. A second TCQ can comprise a third frequency mode and a fourth frequency mode. First TCQ can be selectively coupled to a first qubit based on the first frequency mode and selectively coupled to the second TCQ based on the second and third frequency modes. Second TCQ can be selectively coupled to a second qubit based on the fourth frequency mode. When certain respective magnetic fluxes are applied to first and second TCQs, ZZ interaction between the first and second qubits can be suppressed. When respective modified magnetic fluxes are applied to first and second TCQs to excite respective frequency modes, coupling can occur, and ZZ interaction and an entangled gate can be created between the first and second qubits.
A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.
A semiconductor structure including a fin of a vertical transistor structure, a top source drain region on a top side of the fin, a bottom source drain region on a bottom side of the fin, and a backside contact below and contacting the bottom source drain region.
A device comprises a data quantum bit, a first quantum bit coupler, a second quantum bit coupler, and an auxiliary quantum bit. The first quantum bit coupler is coupled to the data quantum bit. The second quantum bit coupler is coupled to the first quantum bit coupler. The auxiliary quantum bit is coupled to the second quantum bit coupler. The first quantum bit coupler is configured to operate in a state to suppress interaction between the data quantum bit and the auxiliary quantum bit. The first quantum bit coupler and the second quantum bit coupler are each configured to operate in a respective state to enable interaction between the data quantum bit and the auxiliary quantum bit and entangle a state of the data quantum bit with a state of the auxiliary quantum bit.
A method for minimizing data transfer and storage utilization on cloud object storage systems is disclosed. In one embodiment, such a method replicates a file from a production system to a cloud object storage system. The method determines whether a number of hard links associated with the file is greater than one. In the event the number is greater than one, the method creates, on the cloud object storage system, a special object for the file and associates the file with the special object. Upon creating a hard link on the production system in association with the file, the method replicates the hard link from the production system to the cloud object storage system without replicating data associated with the file. A metadata reference to the special object is added to the hard link on the cloud object storage system. A corresponding system and computer program product are also disclosed.
Container data sharing is provided. A second container of a cluster of containers is started to process a service request in response to detecting a failure of a first container processing the service request. The service request and data generated by the first container that failed stored on a physical external memory device is accessed. The service request and the data generated by the first container that failed is loaded on the second container from the physical external memory device via a dedicated hardware link for high-speed container failure recovery.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
90.
COLLABORATIVE COMPUTATION ACROSS BLOCKCHAIN NETWORKS
A system and method for a multi-party computation (MPC) is provided. In implementations, a method includes identifying a blockchain network and a computing device to perform an MPC based on an index; generating an MPC request including a function to be performed by the blockchain network and the computing device, data required for the function, and a verification policy defining a verification protocol to be performed by the blockchain network and the computing device; sending the MPC request to the blockchain network and the computing device; and receiving responses from a representative computing node of the blockchain network and the computing device, wherein each of the responses includes: an output of an MPC protocol performed by the blockchain network and the computing device to jointly compute the function while keeping the inputs private from one another and private from the computing system; and a proof based on the verification policy.
A computer-implemented method, system and computer program product for applying hypervisor-based containers to a cluster of a container orchestration system. A container runtime of a worker node in the cluster of the container orchestration system issues a request to create a sandbox environment to store a pod containing one or more containers. Upon creating the sandbox environment for each pod to improve isolation, a network tunnel is created between the worker node and the sandbox environment without packet encapsulation in which the sandbox environment shares the same Internet Protocol (IP) address as the other end of the network tunnel in the worker node. Packets may then be routed (forwarded) from the worker node to the sandbox environment via the network tunnel using source routing. By utilizing such source routing, packet looping is prevented. In this manner, hypervisor-based containers may be applied to a cluster of a container orchestration system.
A semiconductor interconnect structure comprises a substrate, a plurality of metal lines disposed relative to the substrate and a plurality of first and second caps disposed on the metal lines wherein the first caps comprise a first dielectric material and the second caps comprise a second dielectric material different from the first dielectric material.
Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.
A semiconductor structure includes a first field-effect transistor having a first back side source/drain contact, a second back side source/drain contact, and a first power line and a first signal line each connected to the first back side source/drain contact and the second back side source/drain contact, respectively. The semiconductor structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor having a first front side source/drain contact, a second front side source/drain contact, and a first power line and a first signal line each connected to the first front side source/drain contact and the second front side source/drain contact, respectively.
H01L 23/528 - Layout of the interconnection structure
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
A semiconductor device includes a ferroelectric random-access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed to attain its ferroelectric phase by an induced current flow and heating process. The current flow may be induced though a temporary wire that causes heating of the FeRAM cell. The resulting heating or anneal of the ferroelectric dielectric may crystalize the ferroelectric dielectric to embody or result in having ferroelectric properties. The induced current flow and heating process is substantially local to the FeRAM cell, and to ferroelectric dielectric therein, as opposed to a global heating or annealing process in which the entire semiconductor device, or a relatively larger region of semiconductor device, is heated to the requisite annealing temperature of ferroelectric dielectric.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
A semiconductor structure is provided in which a phase change memory (PCM) device region including a PCM is located in a back side of a wafer. A PCM device back side source/drain contact structure connects the PCM to a first source/drain structure of a first field effect transistor (FET) that is present in a front side of the wafer, the second source/drain structure of the first FET is connected to a front side BEOL structure by a front side source/drain contact structure. A logic device region and/or an analog device region can be located laterally adjacent to the PCM device region. A back side power distribution network can be present in the logic device region and/or an analog device region.
An example operation may include one or more of receiving a message from an agent installed at a data replication server, the message comprising a status identifier of a checksum validation of a data replication operation, identifying a latency value associated with the data replication server, determining whether a data loss has occurred based on the status identifier of the checksum validation and the latency value, and in response to a determination that the data loss has occurred, transmitting a notification of the data loss to a computing system associated with the data replication server.
Provisioning business functions is provided. A runtime binary activation code is sent to a nodal edge server that has a needed runtime binary for a set of edge devices to perform a business function. A secure shell protocol connection with root operating system access is established to the nodal edge server that has the needed runtime binary to execute the runtime binary activation code.
A serverless computing-based, continuous gateway watch of a data store for data change process is provided. The process includes the gateway interface of the computing environment receiving a watch request from a user system to monitor the data store for data change. Based on receiving the watch request, the gateway interface invokes a serverless setup service to establish a connection between the gateway interface and the data store of the computing environment to be monitored for data change. Based on receiving, at the gateway interface, a data change indication from the data store, the gateway interface invokes a serverless message process service to mutate the data change indication from the data store into a mutated data change message indicative of a data change at the data store for return to the user system pursuant to the watch request, with the serverless message process service terminating thereafter.
Provided is a damper system for an electronic equipment rack. The damper system may include an electronic equipment rack, a battery back-up unit, and a plurality of rails disposed within the electronic equipment rack. The battery back-up unit is slidably secured to the plurality of rails and tuned to dampen seismic oscillations of the electronic equipment rack during an earthquake. The battery back-up unit is also able to provide power to the electronic equipment disposed in the rack during a power outage.
patents
