09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware and recorded and downloadable computer
software for information technology analysis and database
management; computer hardware and recorded and downloadable
computer software for application development; computer
hardware and recorded and downloadable computer software for
cloud computing; recorded and downloadable computer hardware
and computer software for artificial intelligence; computer
hardware and recorded and downloadable computer software for
cognitive computing; computer servers; recorded and
downloadable computer software for managing hardware,
software and processes that exist within an information
technology environment; computer systems combining hardware
and recorded and downloadable software for management and
analysis of data and instructional manuals sold as a unit
with these products; computer systems, namely, computer
hardware and recorded and downloadable computer software for
developing and integrating artificial intelligence, namely,
machine learning, deep learning and natural language
processing which is capable of collecting, organizing and
analyzing data; computer systems, namely, computer hardware
and recorded and downloadable computer software for
integrating Natural Language Processing (NLP), Computational
Linguistics (CL), Information Retrieval (IR) and Machine
Learning (ML) which is capable of understanding general
human queries; recorded and downloadable electronic
publications on computer media, namely, user manuals,
guides, brochures, information sheets, written presentations
and teaching materials, in the field of computers, computer
networks, computer storage, computer operating systems,
information technology, database management, cloud
computing, artificial intelligence, blockchain technology
and quantum computing. Software as a service (SaaS) services featuring software for
data management; software as a service (SaaS) services
featuring software for cloud computing; software as a
service (SaaS) services featuring software for artificial
intelligence; software as a service (SaaS) services
featuring software for cognitive computing; software as a
service (SaaS) services featuring software for blockchain
technology; software as a service (SaaS) services featuring
software for quantum computing and quantum programming;
software as a service (SaaS) services featuring software for
constructing, analyzing and running quantum programs and
quantum algorithms; software as a service (SaaS) services
featuring software for developing and testing quantum
algorithms; computer system integration services; computer
technology consultation services; consulting services in the
field of design, selection, implementation and use of
computer hardware, recordable and downloadable software and
software as a service (SaaS) systems for third parties;
technical support services, namely, troubleshooting in the
nature of diagnosing problems with computer hardware,
computer servers, recorded and downloadable computer
software and software as a service (SaaS); computer system
design services for third parties; computer system analysis;
interconnection of computer hardware and recorded and
downloadable software, namely, integration of computer
systems and networks; services for testing computers,
servers, computer hardware, recorded and downloadable
computer software and software as a service (SaaS) to ensure
proper functioning; installation, updating and maintenance
of recorded and downloadable computer software; computer
programming for third parties; consulting services in the
field of artificial intelligence; consulting services in the
field of blockchain technology; consulting services in the
field of information technology; consulting services in the
field of data management; consulting services in the field
of cloud computing; consulting services in the field of
quantum computing; consulting services in the field of
software as a service (SaaS); computer services, namely,
integration of private and public cloud computing
environments comprising integrated computer hardware and
recorded and downloadable software network services for
dynamic provisioning, virtualization and consumption
metering of computer resources; providing virtual computer
systems and virtual computer environments through cloud
computing; design and development of recorded and
downloadable computer software for cloud storage of data;
cloud hosting provider services; electronic storage of data
and recovery of computer data; data security services.
09 - Scientific and electric apparatus and instruments
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware for quantum computing; computer software
for quantum computing; computer hardware and computer
software for data processing in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; downloadable
electronic publications in the nature of books, brochures,
information sheets, instruction manuals, presentations,
instructional and teaching materials, press releases,
newsletters, reviews, technical reports, teaching material
and training material in the field of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; computer
hardware and software enabling access to a quantum computer;
downloadable software for constructing, analyzing, testing,
programming and running programs, algorithms, instruction
languages and applications on a quantum computer;
downloadable computer software for converting a computer
code to read on a quantum computer; user interfaces, namely,
keyboards, electronic control panels and touchscreens for
controlling and reading information from a quantum computer;
downloadable computer software for simulating a quantum
computer; downloadable software for using quantum computers
in applications. Educational services, namely, conducting and organizing
courses, seminars, conferences, webinars and workshops in
the fields of quantum computing, quantum science, quantum
materials, quantum devices and quantum research; training
services in the fields of quantum computing, quantum
science, quantum materials, quantum devices and quantum
research. Computer services, namely, computer programming, computer
system integration services, software development and
computer systems analysis in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; computer
consulting services, namely, advice with respect to
software, advice in the field of cloud computing and
computer programming advice in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations, and quantum computing; technical
support services, namely, troubleshooting with respect to
computer systems and diagnosing computer hardware and
software problems in the fields of information technology,
cloud computing, artificial intelligence, computer
simulations and quantum computing; computer programming for
third parties in the fields of information technology, cloud
computing, artificial intelligence, computer simulations and
quantum computing; software and computer hardware design
services for quantum computing; quantum computing services,
namely, computing using different physical phenomena, such
as overlaying, entanglement and interference for storing and
processing data and information; consultancy in the field of
quantum computing, namely, information technology from
different physical phenomena, such as overlaying,
entanglement and interference for storing and processing
data and information; designing computer hardware and
software for cognitive computing; consultancy in the field
of cognitive computing, namely, simulating human thought
processes in a computerized model; research, development and
advisory services relating to information technology, cloud
computing, artificial intelligence, computer simulations and
quantum computing.
09 - Scientific and electric apparatus and instruments
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware for quantum computing; computer software
for quantum computing; computer hardware and computer
software for data processing in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; downloadable
electronic publications in the nature of books, brochures,
information sheets, instruction manuals, presentations,
instructional and teaching materials, press releases,
newsletters, reviews, technical reports, teaching material
and training material in the field of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; computer
hardware and software enabling access to a quantum computer;
downloadable software for constructing, analyzing, testing,
programming and running programs, algorithms, instruction
languages and applications on a quantum computer;
downloadable computer software for converting a computer
code to read on a quantum computer; user interfaces, namely,
keyboards, electronic control panels and touchscreens for
controlling and reading information from a quantum computer;
downloadable computer software for simulating a quantum
computer; downloadable software for using quantum computers
in applications. Educational services, namely, conducting and organizing
courses, seminars, conferences, webinars and workshops in
the fields of quantum computing, quantum science, quantum
materials, quantum devices and quantum research; training
services in the fields of quantum computing, quantum
science, quantum materials, quantum devices and quantum
research. Computer services, namely, computer programming, computer
system integration services, software development and
computer systems analysis in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; computer
consulting services, namely, advice with respect to
software, advice in the field of cloud computing and
computer programming advice in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations, and quantum computing; technical
support services, namely, troubleshooting with respect to
computer systems and diagnosing computer hardware and
software problems in the fields of information technology,
cloud computing, artificial intelligence, computer
simulations and quantum computing; computer programming for
third parties in the fields of information technology, cloud
computing, artificial intelligence, computer simulations and
quantum computing; software and computer hardware design
services for quantum computing; quantum computing services,
namely, computing using different physical phenomena, such
as overlaying, entanglement and interference for storing and
processing data and information; consultancy in the field of
quantum computing, namely, information technology from
different physical phenomena, such as overlaying,
entanglement and interference for storing and processing
data and information; designing computer hardware and
software for cognitive computing; consultancy in the field
of cognitive computing, namely, simulating human thought
processes in a computerized model; research, development and
advisory services relating to information technology, cloud
computing, artificial intelligence, computer simulations and
quantum computing.
09 - Scientific and electric apparatus and instruments
41 - Education, entertainment, sporting and cultural services
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware for quantum computing; computer software
for quantum computing; computer hardware and computer
software for data processing in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; downloadable
electronic publications in the nature of books, brochures,
information sheets, instruction manuals, presentations,
instructional and teaching materials, press releases,
newsletters, reviews, technical reports, teaching material
and training material in the field of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; computer
hardware and software enabling access to a quantum computer;
downloadable software for constructing, analyzing, testing,
programming and running programs, algorithms, instruction
languages and applications on a quantum computer;
downloadable computer software for converting a computer
code to read on a quantum computer; user interfaces, namely,
keyboards, electronic control panels and touchscreens for
controlling and reading information from a quantum computer;
downloadable computer software for simulating a quantum
computer; downloadable software for using quantum computers
in applications. Educational services, namely, conducting and organizing
courses, seminars, conferences, webinars and workshops in
the fields of quantum computing, quantum science, quantum
materials, quantum devices and quantum research; training
services in the fields of quantum computing, quantum
science, quantum materials, quantum devices and quantum
research. Computer services, namely, computer programming, computer
system integration services, software development and
computer systems analysis in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations and quantum computing; computer
consulting services, namely, advice with respect to
software, advice in the field of cloud computing and
computer programming advice in the fields of information
technology, cloud computing, artificial intelligence,
computer simulations, and quantum computing; technical
support services, namely, troubleshooting with respect to
computer systems and diagnosing computer hardware and
software problems in the fields of information technology,
cloud computing, artificial intelligence, computer
simulations and quantum computing; computer programming for
third parties in the fields of information technology, cloud
computing, artificial intelligence, computer simulations and
quantum computing; software and computer hardware design
services for quantum computing; quantum computing services,
namely, computing using different physical phenomena, such
as overlaying, entanglement and interference for storing and
processing data and information; consultancy in the field of
quantum computing, namely, information technology from
different physical phenomena, such as overlaying,
entanglement and interference for storing and processing
data and information; designing computer hardware and
software for cognitive computing; consultancy in the field
of cognitive computing, namely, simulating human thought
processes in a computerized model; research, development and
advisory services relating to information technology, cloud
computing, artificial intelligence, computer simulations and
quantum computing.
A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.
H01L 43/12 - Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H01L 27/22 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate using similar magnetic field effects
H01L 43/02 - Devices using galvano-magnetic or similar magnetic effects; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof - Details
Techniques are described with respect to a system, method, and computer product for generating relevance alerts. An associated method includes analyzing a multi-party discussion based on a generated profile associated with a user and assigning at least one relevance value associated with the user to the multi-party discussion based on the analysis and an amount of multi-party discussion participation associated with the user. The method further includes generating an alert for the user to participate in the multi-party discussion in response to determining the relevance value exceeding a relevance threshold associated with the multi-party discussion.
An integrated circuit communication architecture is provided and includes a clock lane, a clock divider, and a first de-skew circuit. The clock lane is configured to send a clock signal at a first rate from a first chip to a second chip. The clock divider is on the second chip and is configured to receive the clock signal sent via the clock lane and to create and send a first divided clock signal and a second divided clock signal from the received clock signal. The divided clock signals are sent at reduced rates compared to the first rate. The clock divider maintains current mode logic properties for the divided clock signals. The first de-skew circuit is configured to receive and process the divided clock signals to allow for sampling of data transmitted from the first chip to the second chip.
A computer-implemented method, in accordance with one embodiment, includes monitoring contextual information of a vehicle during operation thereof. A determination is made that a condition is met to project, by a vehicle-based projection system mounted to the vehicle, a projection indicative of a contextual condition associated with the vehicle. In response to the determination that the condition is met, the projection indicative of the contextual condition is projected.
A method of providing a surrogate program for a program endpoint includes: obtaining, by a processor set, a set of plural input/output pairs generated using the program endpoint; generating, by the processor set, transformations based on the input/output pairs; generating, by the processor set, a model that classifies inputs of the input/output pairs to ones of the transformations based on parameters of one or more strings of the inputs; receiving, by the processor set, a new input; selecting, by the processor set and using the model, one of the transformations based on parameters of one or more strings of the new input; and generating, by the processor set, a new output by applying the selected one of the transformations to the new input.
In an approach to improve the generation of a virtual object in a three-dimensional virtual environment, embodiments of the present invention identify a virtual object to be generated in a three-dimensional virtual environment based on a natural language utterance. Additionally, embodiments generate the virtual object based on a CLIP-guided Generative Latent Space (CLIP-GLS) analysis, and monitor usage of the generated virtual object in the three-dimensional virtual space. Moreover, embodiments infer human perception data from the monitoring, and generate a utility score for the virtual object based on the human perception data.
A method includes identifying a cluster of users with a plurality of devices, where each user from the cluster of users is associated with at least one device from the plurality of devices. The method also includes identifying an authorized user from the cluster of users to delegate role assignments to a remaining portion of the cluster of users and receiving, from the authorized user, a first role assignment for a first user from the remaining portion of the cluster of users. In response to receiving, from the first user, an audio command, the method also includes determining whether the first user is authorized to provide the audio command to the intelligent virtual assistant based on the first role assignment. In response to determining the first user is authorized to provide the audio command, the method also includes performing the audio command from the first user.
An integrated circuit is presented including a protection diode including a plurality of first gates and a plurality of first source/drain (S/D) contacts and a device under test (DUT) including a plurality of second gates and a plurality of second S/D contacts, the DUT being electrically connected to the protection diode by either at least one gate contact or at least on CA contact or at least one buried power rail (BPR). The protection diode is electrically connected to the DUT by middle-of-line (MOL) layers for gate oxide protection before M1 formation.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
The invention provides for a method, computer program product, and computer system for a training platform for training a user on an application. The method provides training content to a training platform interface at a user browser, wherein the training content includes instructions for a user on interaction with an application and provides access to an application instance at the training platform interface for user interaction with the application instance. The method further provides a session of an application instance hosted by an application node for the duration of a training session. The method may further determine a training content and an application from user input received at the user browser and broadcasting a message to find a free application instance of the application. The method may further select an application instance from one or more responses from application nodes based on defined selection factors.
A semiconductor structure includes a power distribution structure disposed on a first wafer, an interconnect structure disposed on the first wafer and a second wafer, and at least one decoupling capacitor connected between the power distribution structure and the interconnect structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
16.
SUFFICIENCY ASSESSMENT OF MACHINE LEARNING MODELS THROUGH MAXIMUM DEVIATION
Techniques regarding determining sufficiency of one or more machine learning models are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in memory. The computer executable components can comprise a measurement component that measures maximum deviation of a supervised learning model from a reference model over a certification set and an analysis component that determines sufficiency of the supervised learning model based at least in part on the maximum deviation.
A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 23/528 - Layout of the interconnection structure
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A method, system, and computer program product for circuit design automation. The method identifies a set of circuit components for a proposed circuit design. A subset of circuit components is selected to generate an initial topology for the proposed circuit design. A set of subsequent topologies are iteratively generated by a heuristic search algorithm based on the subset of circuit components and the initial topology. A set of valid topologies of the set of subsequent topologies are determined by a circuit simulator based on the subset of circuit components and a set of connections within the set of subsequent topologies. The method generates the proposed circuit design from the set of valid topologies.
A voltage source watchdog comprising a passive device is placed in series between a voltage source and a load. The passive device includes an electromigration (EM) joint of known materials that will create an electromigration void after a specified amount of current passes through the EM joint. After a known amount of current as passed through, a void is created and a voltage will no longer be sensed, thus providing a sure safety mode situation. When the voltage source is a battery, the battery life may be extended by selectively enabling voltage measurement operations for the proposed watchdog.
Method, computer program product, and computer system are provided. Traffic is collected against a NoSQL database by an activity collector. A database transaction log is periodically extracted and analyzed. The collected traffic and the analyzed database transaction log are input to building a knowledge base of database access patterns. Current traffic is captured and used to compute an activity threshold. Traffic is directed to a workload processor based on the activity threshold. Traffic is directed to an intensive insert/update/delete (IUD) processor in response to the activity threshold exceeding a configured threshold. A plurality of temporary shards is generated along with an adaptive key and adaptive index in the plurality of temporary shards. The intensive IUD processor traffic is re-directed to the plurality of temporary shards while the activity threshold exceeds the configured threshold.
A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Embodiments of the invention are directed to computer-implemented methods of analyzing a web-based software application. A non-limiting example of the computer implemented method includes generating, using a processor system, a set of to-be-tested element-event pairs of the web-based software application. A set of compatibility tests is received at the processor system, where the set of compatibility tests is operable to perform compatibility testing of a corresponding set of element-event pairs. A comparison is performed between the set of to-be-tested element-event pairs and the corresponding set of element-event pairs. A compatibility testing recommendation is generated based at least in part on a result of the comparison.
Techniques are provided for performing an RFID-based localization and mapping of an environment. In one embodiment, the techniques involve generating identifying information of a first virtual object based on a RFID tag scan, retrieving a first virtual object model or a first object model data based on the identifying information of the first virtual object, generating display data of the first virtual object model or the first object model data relative to a position of an augmented reality system, and rendering the first virtual object model or the first object model data on a display based on the display data.
According to an aspect, a computer-implemented method includes operating a program on a virtual machine on a first device having a local cache memory. Based on a determination that an epoch timer has not expired, aspects include writing one or more updates to the local cache memory and transmitting evicted items from the local cache memory to a shared memory device that is separate from the first device. Based on a determination that an epoch timer has expired, aspects include flushing the local cache memory to the shared memory device, transmitting a virtual CPU state of the virtual machine to the shared memory device, and resetting the epoch timer.
A semiconductor structure is presented including a backside contact of a nanosheet transistor positioned on a silicon (Si) layer of a wafer and a dielectric liner disposed between the backside contact and the Si layer such that the dielectric liner is located below gate spacers of the nanosheet transistor. The backside contact is closer to a backside of the wafer than a frontside of the wafer. The dielectric liner is vertically aligned with the gate spacers and the dielectric liner is vertically aligned with inner spacers of a nanosheet stack of the nanosheet transistor.
A semiconductor device includes a substrate; a set of first transistors positioned on an upper surface of the substrate, each of the set of first transistors comprising a first gate and a first dielectric; an insulating layer positioned on an upper surface of the set of first transistors; and a set of second transistors positioned over the set of first transistors and with the set of first transistors on an upper surface of the insulating layer, each of the set of second transistors having a second gate and a second dielectric; wherein each of the first dielectrics is connected to a sidewall of each of a corresponding first gate; and wherein each of the second dielectrics is connected to the insulating layer.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 23/528 - Layout of the interconnection structure
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
A computer implemented method for certifying robustness of image classification in a neural network is provided. The method includes initializing a neural network model. The neural network model includes a problem space and a decision boundary. A processor receives a data set of images, image labels, and a perturbation schedule. Images are drawn from the data set in the problem space. A distance from the decision boundary is determined for the images in the problem space. A re-weighting value is applied to the images. A modified perturbation magnitude is applied to the images. A total loss function for the images in the problem space is determined using the re-weighting value. A confidence level of the classification of the images in the data set is evaluated for certifiable robustness.
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/774 - Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting
Using exported data of a machine learning model and a model training environment specification, a resource usage specification and a code module usage specification of the model are identified. A code module installation specification is determined from a code module requirements specification and a target execution environment specification. The code modules specified by the code module installation specification are caused to be installed in the target execution environment. Using data of the updated target execution environment, the updated target execution environment is validated for execution of the model. Execution of the model in the updated target execution environment is simulated. The model is deployed in the updated target execution environment responsive to the simulating being successful.
Techniques for improving switching properties of phase change memory devices by boron surface passivation of the phase change memory material are provided. In one aspect, a phase change memory device includes: one or more phase change memory cells, each having a phase change material between a bottom electrode and a top electrode; and a boron-containing and nitrogen-containing bilayer on sidewalls of the phase change material to protect the phase change material from exposure to oxygen. An ovonic threshold switch can be implemented between the bottom electrode and the top electrode, in series with the phase change material. A method of fabricating the present phase change memory devices is also provided.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
30.
Anonymous Leaderboard Based on Non-Fungible Tokens
An anonymous leaderboard for a monitored computing environments is provided. In response to an entity registering with the monitored computing environment (MCE), an encrypted identity and a dynamic non-fungible token (NFT) are generated for the registered entity, where the dynamic NFT has an associated blockchain technology data structure. The blockchain technology data structure is associated with the encrypted identity. A progress element notification is received from the MCE in response to the entity satisfying criteria for a predefined progress element associated with the MCE. In response, a static NFT, corresponding to the predefined progress element, is generated and stored as a block in the blockchain technology data structure. An entry in an anonymous leaderboard output is generated based on the blockchain technology data structure, where the entry identifies the entity by the encrypted identity.
A63F 13/798 - Game security or game management aspects involving player-related data, e.g. identities, accounts, preferences or play histories for assessing skills or for ranking players, e.g. for generating a hall of fame
A system and method are used to record and present a training video for a software component. The method displays the video recording. The video recording comprises: a display element of the software component, and first recorder activity data (FRAD) of recorder user interface (UI) input activity data (RUIIAD) at a FRAD time with video frame data of the video recording. The method further comprises receiving, during the displaying, viewer UI actions from a UI of the viewing device and converting them to viewer UI input activity data based on viewer interactions with the display element of the software component. Then, first viewer activity data (FVAD) is determined at a FVAD time of the video frame that corresponds to the FRAD, where the FRAD time and the FVAD time differ. Responsive to the determining, the method moves the video recording from the FVAD time to the FRAD time.
G09B 5/06 - Electrically-operated educational appliances with both visual and audible presentation of the material to be studied
G06F 3/0354 - Pointing devices displaced or positioned by the user; Accessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
G06F 3/0482 - Interaction with lists of selectable items, e.g. menus
An apparatus for guidance and retention of integrated circuit boards includes a first structure configured to receive a first integrated circuit board and guide the first integrated circuit board for coupling to a substrate. The apparatus further includes a second structure configured to be removably coupled to the first structure. The second structure includes a first spring member configured to apply a first compressive force to the first integrated circuit board.
A semiconductor structure is presented including a first memory array and a second memory array directly connected to the first memory array by nanosheet stacks and backside contacts. The first and second memory arrays collectively define a double-sided memory array on a complementary metal oxide semiconductor (CMOS) wafer. The nanosheet stacks separate the first memory array from the second memory array so that two different types of memory devices are integrated together into a single CMOS chip.
H01L 27/105 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
A computer-implemented method for filtering search engine results for a user is provided. The method includes maintaining a filtration layer that is opted into by a search engine and a client device. The method further includes building a user search interaction model, operatively coupled to the filtration layer, based on a user's profile and historic search results by performing a topic analysis on a user's interactions with the historic search results and selecting a subset of relevant topics based on respective amounts of user interaction. The user interaction includes interactions on a plurality of different devices. The method also includes filtering search results produced for a particular user search query on the client device using the user search interaction model and the filtration layer.
Systems and methods for operating a beamforming circuit are described. A processor can activate a transmitting element among a plurality of transmitting elements of a beamforming circuit. The processor can activate a receiving element among a plurality of receiving elements of a beamforming circuit. The processor can receive a direct current (DC) signal that represents phase and amplitude of the activated transmitting element and the activated receiving element. The processor can adjust a setting of the beamforming circuit to receive additional DC signals that represent phases and amplitudes of the activated transmitting element and the activated receiving element under the adjusted setting. The processor can determine calibration values for the beamforming circuit based on the DC signal and the additional DC signals.
H04B 7/08 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
H04B 1/30 - Circuits for homodyne or synchrodyne receivers
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A method for utilizing augmented reality for positioning vehicles is disclosed. In one embodiment, such a method enables a customer to visualize, by way of an augmented reality device, a desired position of a vehicle selected to arrive at a designated pickup spot. This may include visualizing, by way of the augmented reality device, the desired position within an environment surrounding the pickup spot. The desired position may include one or more of a location and orientation of the vehicle and may be selected to optimize loading of passengers and/or cargo into the vehicle. The method documents the desired position and communicates the desired position to a ride-hailing service to enable the vehicle to be placed in accordance with the desired position upon arriving at the designated pickup spot. A corresponding system and computer program product are also disclosed.
A thermal radiation shield interface for cryogenic systems includes a first element with a distal, free end. Flanges project from the distal, free end of the first element. A second element also includes a distal, free end. Flanges project from the distal, free end of the second element. The flanges of the first element and the flanges of the second element are positioned in an interleaved arrangement to cover an opening between the first element and the second element shielding the opening from radiation leakage.
An interconnect structure for connecting an upper wiring line to a lower wiring line includes a via connecting a lower portion of the upper wiring line with an upper surface of the lower wiring line and a wrap-around via portion formed integrally with the via, the wrap-around portion extending along and electrically contacting a portion of the sides of the lower wiring line.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
An example operation may include one or more of ingesting data records from a plurality of external data sources via a plurality of API calls, generating a plurality of digital footprints for a plurality of users, respectively, which have access to a common finite space, wherein each digital footprint includes a respective health value of a respective user generated based on ingested data records of the user, identifying a user from among the plurality of users which is about to enter the common finite space, in response to identifying the user, determining a cumulative safety value for the common finite space based on the digital footprint of the identified user and a digital footprint of one or more other users already present within the common finite space, and transmitting an alert to a computing system based on the determined cumulative safety value for the common finite space.
A computer-implemented method for resolving a potential loss of sale, is disclosed. The computer-implemented method includes determining a potential lost sale and an item associated with the potential lost sale. The computer-implemented method further includes determining a reason for the potential lost sale of the item. The computer-implemented method further includes determining one or more substitute items for the item based, at least in part, on the determined reason for the potential lost sale of the item. The computer-implemented method further includes presenting the one or more determined substitute items to a user.
An embodiment for monitoring machine learning models to detect and rectify model drift using governance. The embodiment may receive a plurality of machine learning models and register the plurality of machine learning models to a governance dashboard. The embodiment may automatically monitor the received plurality of machine learning models to identify factors used by each of the received plurality of machine learning models and generate corresponding clusters of similar machine learning models. The embodiment may automatically detect an incorrect decision made by a target machine learning model and then automatically calculate a correlation score between the target machine learning model and machine learning models within an associated corresponding cluster of similar machine learning models. The embodiment may, in response to detecting a correlation score above a threshold, automatically determine and output a cluster reinforcement recommendation.
A computer-implemented method, a computer system and a computer program product select enterprise assets for migration to open cloud storage. The method includes identifying an asset on a server. The method also includes determining whether the asset contains sensitive information. The method further includes obtaining a migration cost for the asset based on asset attributes. In addition, the method includes calculating a migration score for the asset based on whether the asset contains the sensitive information, access rules for the asset, an asset handling history, and the migration cost. Lastly, the method includes selecting the asset for migration to open cloud storage when the migration score of the asset is above a threshold.
One or more systems, devices, computer program products and/or computer-implemented methods of use provided herein relate to a process to facilitate multi-lingual query interpretation. A system can comprise a memory that stores computer executable components, and a processor that executes the computer executable components stored in the memory, wherein the computer executable components can comprise an annotation component that generates one or more language invariant signals, an interpretation component that generates a complete query intent using the one or more language invariant signals, and a translation component that processes the complete query intent to an executable backend query to facilitate multi-lingual query interpretation. In one or more embodiments, the translation component can be operatively connected with the interpretation component to generate a zero-shot transfer of the one or more language invariant signals.
Information received from a graphical user interface (GUI) and a list of user-curated command line patterns are received by an auto-wrapper system, wherein the auto-wrapper system is associated with an analytics workflow service. A module including a parameter space having one or more parameters and options used in the list of user-curated command line patterns is generated, by the auto-wrapper system, wherein content for each parameter is derived from the parameter's presence in the list of user-curated command line patterns combined with the information received from a GUI.
Aspects of the present disclosure relate to use-based security challenge authentication. Usage frequency metrics for features of an electric device can be collected over time. A set of critical features can be determined based on the collected usage frequency metrics, where each critical feature has a usage frequency exceeding a usage frequency threshold. A determination can be made whether a condition is met for use-based authentication. In response to determining that the condition is met for use-based authentication, a use-based security challenge can be generated using a critical feature, the use-based security challenge based on use frequency of the critical feature. The generated use-based security challenge can be presented to the user. A response to the use-based security challenge can be received. A sufficiency of the response to the use-based security challenge can be determined. Access to the electronic device can be authorized based on a sufficiency of the response.
Translating applications to a target language includes extracting program integrated information (PII) to be translated and creating translation context datasets based on interpretation of accessibility information associated with particular strings of PII. Translation pairs include PII and corresponding context datasets for context-based translation of application components. A two-stage index contains PII strings for first stage lookup and context datasets for distinguishing duplicate PII strings as a second stage lookup. Real-time translation is facilitated by the two-stage index, which is established by translation pairs and resulting translations.
A lower set of semiconductor channel layers, an upper set of semiconductor channel layers, a lower dielectric layer adjacent to the lower set of semiconductor channel layers, the lower dielectric layer includes a first polarity stress on the lower set of semiconductor channel layers, and an upper dielectric layer adjacent to the upper set of semiconductor channel layers, the lower dielectric layer includes a second polarity stress on the upper set of semiconductor channel layers with opposite polarity stress of the first polarity stress. Forming a lower stack of nanosheet layers and an upper stack of nanosheet layers, forming a lower dielectric layer adjacent to the lower stack of nanosheet layers, the lower dielectric layer includes a first polarity stress, and forming an upper dielectric layer adjacent to the upper stack of nanosheet layers, the upper dielectric layer includes a second polarity stress with opposite polarity.
A compliant counter-flow cold plate for component cooling includes a manifold body configured to be thermally coupled to a heat generating component and configured to be compliant under a distributed pressure load, and a plurality of expanding channels within the manifold body. At least one of the plurality of expanding channels extends from an inlet portion of the manifold body to an outlet portion of the manifold body.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
F28F 13/08 - Arrangements for modifying heat transfer, e.g. increasing, decreasing by affecting the pattern of flow of the heat-exchange media by varying the cross-section of the flow channels
An example operation may include one or more of acquiring, by a retailer node, an inventory data from a supplier node over a blockchain network, receiving, by the retailer node, outstanding orders data of the supplier node, generating, by the retailer node, an order distribution policy based on the inventory data and the outstanding orders data, and executing a smart contract to order goods from the supplier node based on the ordering policy.
A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
51.
INTEGRATED CIRCUIT CHIP WITH BACKSIDE POWER DELIVERY AND MULTIPLE TYPES OF BACKSIDE TO FRONTSIDE VIAS
A semiconductor device that includes a first via connecting a backside of the semiconductor device to a frontside of the semiconductor device, and a second via connecting the backside of the semiconductor device to the frontside of the semiconductor device. The first via and the second via are directly connected to at least one different wiring level on the frontside or the backside.
To limit resistance variability across a resistive random-access memory (RRAM) call, the disclosure includes an RRAM cell with a resistance spreading layer within the RRAM cell between the top and bottom electrodes of the RRAM cell. The resistance spreading layer is in series with and has no impedance with a filament forming layer of the RRAM cell. The resistance spreading layer may be below the filament forming layer or the resistance spreading layer may be above the filament forming layer. The resistance spreading layer may further be in series with and has no impedance with the bottom electrode or the top electrode.
H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
53.
SUB-EUV PATTERNING HEATERS FOR BAR MUSHROOM CELL PCM
A phase change material (PCM) memory cell having a metal heater element of sub-EUV dimension. The PCM memory cell includes a bottom electrode of a metal-containing material, a memory cell structure including a phase change material; and a metal heater element of sub-extreme ultraviolet (sub-EUV) dimension situated between and electrically connecting the bottom electrode and PCM memory cell structure. The metal heater element is formed of a circular via structure of sub-EUV dimension and has a seamless metal-nitride fill material. The circular via structure of sub-extreme ultraviolet (sub-EUV) dimension further includes a metal-nitride liner of sub-EUV dimension, the metal-nitride liner of sub-EUV dimension including a thicker metal-nitride liner bottom surface portion and thinner sidewall metal-nitride portions. The thicker metal-nitride liner bottom surface portion improves heat insulation and provides for high resistance/low power switching and reduced amorphous phase change material volumes.
Information received from a graphical user interface (GUI) and a list of user-curated command line patterns are received by an auto-wrapper system, wherein the auto-wrapper system is associated with an analytics workflow service. A module including a parameter space having one or more parameters and options used in the list of user-curated command line patterns is generated, by the auto-wrapper system, wherein content for each parameter is derived from the parameter's presence in the list of user-curated command line patterns combined with the information received from a GUI.
Aspects of the present disclosure relate generally to software development environments and, more particularly, to systems, computer program products, and methods of automating software development, security, and operations (DevSecOps). For example, a computer- implemented method includes receiving, by a processor, a plurality of infrastructure as code files specifying a configuration of a runtime environment for a deployable image of source code in a continuous integration and continuous delivery pipeline for a cloud platform; generating, by the processor, compliance code for at least one file of the plurality of infrastructure as code files; building, by the processor, the deployable image of the source code in the continuous integration and continuous delivery pipeline according to the configuration specified by the plurality of infrastructure as code files and the compliance code; and deploying, by the processor, an instance of the image in the runtime environment.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
56.
EXPERIENCE BASED DISPATCH OF REGULATED WORKLOADS IN A CLOUD ENVIRONMENT
Mechanisms are provided for dispatching requests to service instances based on data storage boundaries. A request specifying an identity is received and dispatched to a service instance of a data storage boundary, where each data storage boundary is defined by a regulation or policy restricting data storage of specific types of data to computing devices within a specified boundary. A feedback response, specifying a target location, is received from the service instance in response to determining that the service instance cannot access the data because the data is associated with a different data storage boundary. A dynamic dispatch rule specifying the identity and the target location is generated and a subsequent request specifying the identity is processed by executing this dynamic dispatch rule to dispatch the subsequent request directly to a service instance associated with the target location.
A nanosheet diode includes a bookend structure and a central structure. The bookend includes a first semiconductor that is doped as one of the anode and the cathode of the diode, and includes a left block, a right block, and a first stack of spaced-apart nanosheets that horizontally connect the left and right blocks. The central structure includes a second semiconductor that is doped as the other of the anode and the cathode of the diode, and includes a front block, a rear block, and a second stack of nanosheets that are interleaved crosswise into spaces between the first stack of spaced-apart nanosheets and that horizontally connect the front and rear blocks. The bookend structure directly contacts top, bottom, and end surfaces of the second stack of nanosheets of the central structure.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/329 - Multistep processes for the manufacture of devices of the bipolar type, e.g. diodes, transistors, thyristors the devices comprising one or two electrodes, e.g. diodes
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region (28) located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region (46) located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure (32) located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure (52) located adjacent to at least one of the second source/drain regions of at one of the second FETs.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Described are techniques for corroborating anomalous behavior. The techniques include training devices included in an Internet of Things (IoT) mesh network to independently identify occurrences of anomalous behavior in a proximate physical environment. The techniques further include receiving event data from at least a portion of the devices in the IoT mesh network corresponding to a time window, where the event data reports occurrences of at least one type of anomalous behavior. The techniques further include corroborating the at least one type of anomalous behavior to determine that the occurrences of the at least one type of anomalous behavior indicate an anomalous event that meets a reporting threshold for providing notice of the anomalous event. The techniques further include generating a notification regarding the anomalous event.
Provided is a computer-implemented method, system, and computer program product for displaying information to a pedestrian using a visual indicator. A processor may detect that a vehicle is approaching a pedestrian. The processor may determine that the pedestrian is unable to see the approaching vehicle. The processor may display an indication that the vehicle is approaching the pedestrian on an object the pedestrian can currently view.
According to one embodiment, a method, computer system, and computer program product for selective image processing. The embodiment may include receiving a digital image for selective image processing. The embodiment may include identifying a context of the selective image processing. The embodiment may include performing object detection within the received digital image to identify one or more depicted objects based on the identified context. The embodiment may include overlaying, on at least one portion of the received digital image, one or more bounding boxes which encompass relative positions of the identified one or more depicted objects. The embodiment may include performing the selective image processing exclusively within the one or more overlaid bounding boxes.
G06V 10/22 - Image preprocessing by selection of a specific region containing or referencing a pattern; Locating or processing of specific regions to guide the detection or recognition
G06T 11/20 - Drawing from basic elements, e.g. lines or circles
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 20/20 - Scenes; Scene-specific elements in augmented reality scenes
An embodiment includes generating a caller list of callers that issue requests for calling a designated program at runtime. The embodiment also includes generating an authorized caller list of authorized callers allowed to call the designated program, wherein the authorized callers are selected from among callers on the caller list. The embodiment also includes generating an authorization key for each of the authorized callers that the designated program will require as a condition for completing call requests.
G06F 21/56 - Computer malware detection or handling, e.g. anti-virus arrangements
G06F 21/51 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
A semiconductor structure comprises a first nanosheet stack comprising one or more first nanosheet channel layers and a first dielectric isolation layer over the one or more first nanosheet channel layers, a second nanosheet stack comprising one or more second nanosheet channel layers and a second dielectric isolation layer over the one or more second nanosheet channel layers, and a gate dielectric layer disposed over a top surface of one of the first dielectric isolation layer and the second dielectric isolation layer.
A computer-implemented method, system and computer program product for improving the performance of a program that manipulates two vectors of data. It is determined whether the program contains one of the following patterns: a first pattern corresponding to v0.rearrange(s, v1); a second pattern corresponding to v0.blend(v1, m); and a third pattern corresponding to v0.rearrange(s).blend(v1.rearrange(s), m). Upon identifying code written as the first pattern in the program, the first pattern is rewritten and replaced with the second or third pattern if the execution time of the program with the second or third pattern is less than the execution time of the program with the first program. In a similar manner, upon identifying code written as the second or third pattern in the program, the second or third pattern is rewritten and replaced with the first pattern if the execution time of the program can be improved.
A method includes, in response to receiving an incoming service request and establishing a call chain of pods of a service mesh network, setting a retry locker parameter to a locked state for each pod in the call chain. A locked retry locker parameter prevents the pod from initiating retries of a service request. The method includes, in response to determining that a pod in the call chain is unavailable, setting the retry locker parameter to an unlocked state for a previous pod just prior to the pod that is unavailable. The unlocked state allows a retry to the pod that is unavailable. In response to the previous pod reaching a retry limit, the method includes setting the retry locker parameter to unlocked for each pod in the call chain and sending a service termination message to a service requester.
According to one embodiment, a method, computer system, and computer program product for biometric mixed-reality emotional modification is provided. The present invention may include collecting, by a plurality of biosensors, biometric information on a user during a mixed-reality session, wherein the biometric information comprises biomarkers; identifying, by one or more machine learning models, a mental state of the user based on the biometric information; and responsive to determining that the mental state does not match an intended emotion associated with a mixed-reality experience, modifying the mixed-reality experience with one or more virtual content elements.
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G16H 40/63 - ICT specially adapted for the management or administration of healthcare resources or facilities; ICT specially adapted for the management or operation of medical equipment or devices for the operation of medical equipment or devices for local operation
According to one embodiment, a method, computer system, and computer program product for selectively recording meetings is provided. The embodiment may include initiating a digital meeting. The embodiment may also include determining two or more rule sets, including one or more local rule sets, for selectively recording the digital meeting, wherein each rule set includes one or more rules. The embodiment may further include recording one or more recordings of the digital meeting according to each local rule set.
One or more systems, devices, computer program products and/or computer-implemented methods provided herein relate to determining veracity of answers generated by machine comprehension question and answer models. According to an embodiment, a machine comprehension component can generate a first answer to a query by extracting the first answer from a passage of text corpus. The text corpus alteration component can alter the text corpus one or more times to produce one or more altered text corpora. The machine comprehension component can further extract one or more additional answers to the query from the altered text corpora. A comparison component can determine a veracity score for the first answer based on one or more comparisons of the first answer with the one or more additional answers.
At least one computer processor can replace visual words of an unsupervised machine learning classification model with visual objects of an image. At least two co-occurring single visual objects adjacent to each other in pixels of the image can be combined to obtain a compound visual object. The unsupervised machine learning classification model can be augmented to model the image as a mixture of subjects, where each subject is represented through placements of the visual objects in a mixture of concentric spheres centering on a mixture of intersections on a mixture of horizontal layers. At least one processor can learn latent relationships between the placements of the visual objects in a three-dimensional space depicted in the image and image semantics. Learning the latent relationships trains the unsupervised machine learning classification model to perform image subject classification through the placements of the visual objects in a new image.
G06V 10/26 - Segmentation of patterns in the image field; Cutting or merging of image elements to establish the pattern region, e.g. clustering-based techniques; Detection of occlusion
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 20/70 - Labelling scene content, e.g. deriving syntactic or semantic representations
70.
COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) APPARATUS WITH SELF-ALIGNED BACKSIDE CONTACT
A CMOS apparatus includes an n-doped field effect transistor (nFET); and a p-doped field effect transistor (pFET), each of which has a source structure and a drain structure. A common backside drain contact, which is disposed at the backside surface of the nFET and the pFET, electrically connects the nFET drain structure and the pFET drain structure to a backside interconnect layer.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
An integrated circuit structure includes a memory cell and multiple transistors therein. The multiple transistors are formed using channels including a stack having alternating layers of conductive semiconductor material and layers of other material that are insulative. Two or more of the multiple transistors have a same number of layers of the conductive semiconductor material in corresponding channel regions but have different numbers of active layers and inactive layers of the conductive semiconductor material. An active layer is a layer forming a channel in the channel region that is electrically coupled to S/D regions in a corresponding transistor, while a floating layer is a layer in the channel region electrically isolated from the S/D regions in the corresponding transistor. Methods for forming the integrated circuit structure are disclosed.
An embodiment includes analyzing text content of a user query to identify via natural language processing (NLP) a query topic. The embodiment maps the query topic to a topic cluster at a node of a hierarchical model of a text database. The embodiment generates query demand data indicative of demand for the topic cluster based on user queries. The embodiment identifies the topic cluster as a topic-cache candidate based on the query demand data. The embodiment compares an amount of memory required for storing text associated with the first topic cluster to available cache memory. The embodiment caches the text of the topic cluster candidate upon determining that there is sufficient available cache memory space.
A method for selecting an application and associated operational guidance to utilize on a mobile device is disclosed. In one embodiment, such a method identifies a selected environment of interest. Within the selected environment, the method identifies one or more applications that are commonly utilized by users within the selected environment and documents the one or more applications. The method detects physical entry of a particular user into the selected environment and, in response to detecting the entry, automatically notifies the particular user of the one or more applications that are commonly utilized within the selected environment. In certain embodiments, the method enables the user to quickly launch the one or more applications and/or provides operational guidance to the user with regard to using the one or more applications. A corresponding system and computer program product are also disclosed.
Mechanisms are provided for dispatching requests to service instances based on data storage boundaries. A request specifying an identity is received and dispatched to a service instance of a data storage boundary, where each data storage boundary is defined by a regulation or policy restricting data storage of specific types of data to computing devices within a specified boundary. A feedback response, specifying a target location, is received from the service instance in response to determining that the service instance cannot access the data because the data is associated with a different data storage boundary. A dynamic dispatch rule specifying the identity and the target location is generated and a subsequent request specifying the identity is processed by executing this dynamic dispatch rule to dispatch the subsequent request directly to a service instance associated with the target location.
Provided are a computer program product, system, and method for pre-processing a table in a document for natural language processing (NLP). A graphical user interface (GUI) provides a representation of table items in a table in a document including a set of a main element comprising an entity whose value is to be extracted, a conditional element that refines the entity, and a value element comprising a value for the entity. Graphical controls are rendered in the GUI to enable a user to select an element from the table to be the main element, conditional element, and value element. The set of the main element, conditional element, and value element are updated with the user selected element to form a modified set. The modified set of the main element, conditional element, and the value element are provided to an NLP engine to perform natural language processing.
Decentralized bilevel optimization techniques for personalized learning over a heterogenous network are provided. In one aspect, a decentralized learning system includes: a distributed machine learning network with multiple nodes, and datasets associated with the nodes; and a bilevel learning structure at each of the nodes for optimizing one or more features from each of the datasets using a decentralized bilevel optimization solver, while maintaining distinct features from each of the datasets. A method for decentralized learning is also provided.
A method for parallel connection for device transactions includes stablishing a first connection to perform a transaction by a client device. The method also includes identifying a plurality of available connections supported by the client device to perform the transaction. The method also includes initializing the plurality of available connections to perform the transaction, wherein each available connection represents a parallel connection to the first connection. The method also includes identifying at least one potential connectivity issue with the first connection based on a comparison between historical network data for the first connection and current network data for the first connection. The method also includes performing a handoff of the transaction between the first connection and a second connection from the plurality of available connections.
A computer-implemented method for dynamically reconfiguring a control plane of a radio access network. The computer-implemented method includes generating a self-awareness matrix of a radio access network (RAN) that comprises a plurality of E2 nodes, the self-awareness matrix comprises a plurality of records for each respective E2 node from the plurality of E2 nodes, a first record corresponding to a first E2 node comprises, for the first E2 node, one or more attributes of the control plane of the RAN, the first E2 node being assigned to a first Near-Real-Time RAN Intelligent Controller (near-RT RIC). The method further includes, in response to the first record satisfying a predetermined condition based on the one or more attributes of the control plane reconfiguring the control plane of the RAN.
A method, computer program, and computer system are provided for text summarization that maintains emotional content. Data corresponding to text to be summarized and a target emotion to be maintained in the text to be summarized is received. The target emotion is encoded as an emotion probability vector. One or more words that correspond to the target emotion that is encoded in the emotion probability vector are identified from a dictionary. A text summary to be associated with the text to be summarized is generated based on the one or more identified words.
A computer-implemented method for addressing conflicts in a radio access network (RAN) includes generating, by a non-Real-Time RAN Intelligent Controller (non-RT RIC), a policy for a near-Real-Time RAN Intelligent Controller (near-RT RIC) by analyzing an activity log of several xApps, which are being executed by the near-RT RIC. The method further includes sending, by the non-RT RIC the policy to the near-RT RIC to cause the near-RT RIC, in response to receiving a request from an xApp from the several xApps to update a parameter of the RAN. The policy specifies an update the parameter based on the policy allowing the xApp to update the parameter. The policy further specifies maintaining the parameter unchanged based on the policy restricting the xApp to update the parameter.
A semiconductor device includes first source/drain (S/D) epitaxy and a second S/D epitaxy and a gate contact. The device also includes a back end of the line (BEOL) layer connected electrically connected to the first S/D epitaxy and the gate contact on a top side of the device and a wafer that carries the BEOL layer and is on the top side of the device. The device also includes a backside trench epitaxy formed through and contacting portions of the second S/D epitaxy and a backside power distribution network electrically coupled to the backside trench epitaxy and disposed on the bottom of the device.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device and formation thereof. The semiconductor device includes a first via in a metal layer, wherein the first via is a single damascene structure. The semiconductor device further includes a second via in the metal level, wherein the second via is a dual damascene structure.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A computer-implemented method for determining container information associated with detected container mutation events is disclosed. The computer-implemented method includes: determining that a system call event to a host operating system includes a call to join a namespace and execute a parent process inside the namespace; determining that the namespace is associated with an existing container; responsive to determining that the namespace is associated with an existing container, determining that the system call event further includes a call to execute a child process inside the namespace; and responsive to determining that the system call event further includes a call to execute a child process inside the namespace: designating the child process as a mutation event to the existing container, and determining container information associated with the mutation event to the existing container. A corresponding computer system and computer program product are also disclosed.
A computer implemented method includes receiving a list of areas on a subject tape to be read, wherein each area of the list of areas is indicated by a first record number and a last record number corresponding to the area, identifying parameters of a tape drive configured to read the subject tape, wherein the identified parameters of the tape drive contribute to a speed with which the tape drive can read the list of areas, creating a directed graph of the areas on the subject tape based on the identified parameters, wherein the directed graph indicates how long the tape drive will take to read the areas on the subject tape, and determining a fastest reading order of the areas on the subject tape, based, at least in part, on the directed graph and the identified parameters. A computer program product and computer system are also disclosed.
Embodiments of the present invention are directed to the implantation of composite tunnel field effect transistors (TFETs) in a nanosheet process. In a non-limiting embodiment of the invention, a first source or drain region is formed having a first composition and a first doping type. A second source or drain region is formed having a second composition and a second doping type opposite the first doping type. A first composite channel structure is formed between the first source or drain region and the second source or drain region. The first composite channel structure includes a first nanosheet trimmed to expose extension portions of the first source or drain region and extension portions of the second source or drain region. The first composite channel structure further includes a first channel epitaxy wrapping around the trimmed first nanosheet. The first channel epitaxy is connected laterally to the extension portions.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Computer-implemented methods for autonomous identification of rouge devices in a communications network are provided. Aspects include collecting connection trace data including connection characteristics for each of a plurality of mobile devices in communication with a communications network and aggregating the connection trace data. Aspects also include determining performance characteristics for each of a plurality of groups of the plurality of mobile devices, wherein each of the plurality of groups corresponds to mobile devices having a type approval code and comparing the performance characteristics for each of the plurality of groups. Based on a determination that the performance characteristics of one of the plurality of groups deviate from the performance characteristics of a remaining set of the plurality of groups by more than a first threshold amount, aspects include designating the type approval code associated with the one of the plurality of groups as a rogue type approval code.
A semiconductor device includes a backside power rail; a transistor source/drain structure that has a backside facing the backside power rail and has a frontside facing away from the backside power rail; and a via disposed between and electrically connecting the backside power rail and the source/drain structure. The via includes a buried portion that is disposed between the backside power rail and the backside of the transistor source/drain structure. A part of the buried portion overlaps and contacts at least a part of the backside of the source/drain structure. The via also includes a side portion that is electrically connected with the buried portion and extends along a vertical side of the source/drain structure between the frontside and the backside; and a top portion that is electrically connected with the side portion and covers at least a part of the frontside of the source/drain structure.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An embodiment includes identifying, during a video conference attended by a first attendee, other attendees of the video conference. The embodiment renders a virtual meeting environment including virtual representations of the other attendees, where the rendering includes accessing relationship characteristic data indicative of relationships between the first attendee and other attendees. The embodiment calculates positions for virtual representations of the other attendees in the first attendee's virtual field of view based on the relationship characteristic data. The embodiment also detects simultaneous speech from two of the other attendees and, in response, directs the individual speech from each of the other attendees to respective audio channels.
Embodiments include super via placement in the development of an integrated circuit. Aspects of the invention include obtaining a power distribution network for the integrated circuit (IC) IC, wherein the PDN includes a plurality of metal vias each configured to connect adjacent metal layers of a plurality of metal layers. Aspects also include placing one or more cells on each metal layer of the IC and identifying a power demand associated with each of the one or more cells. Aspects further include updating the PDN, based on the power demand associated with each of the one or more cells, to replace at least two of the plurality of metal vias with a super via that is configured to connect non-adjacent metal layers of the plurality of metal layers.
H01L 23/528 - Layout of the interconnection structure
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A disclosed technique enables a tree of transactions between entities which may be a first entity and a second entity. The technique may be implemented at a transaction recipient, which can be one of the entities or an external actor, such as a certifier. The transaction recipient accesses two transactions, including a first and second transaction, and two respective secrets, including a first and second secret. The first transaction originates from the first entity, while the second transaction originates from the second entity. The first and second transaction are obfuscated based on the first secret and the second secret, respectively. The first transaction is logically connected to the second transaction. The transaction recipient further de-obfuscates the two transactions using the two respective secrets, and cryptographically signs at least a part of the second transaction to obtain a signature, prior to allowing the second entity to access the obtained signature.
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentials; Review and approval of payers, e.g. check of credit lines or negative lists
91.
CONTEXT AWARE INVOLVING MOBILE PHONE WITH VEHICLE TO ENHANCE VEHICLE TO VEHICLE COMMUNICATION NETWORK STRENGTH
A method comprising establishing a local communication network among and between a plurality of onboard vehicle computers respectively located in a plurality of vehicles, polling the vicinity of each vehicle to determine a set of qualified mobile device(s) that meet the following criteria: (i) the qualified mobile device is located within one of the vehicles of the plurality of vehicles, (ii) the qualified mobile device is configured and equipped to join the local network, and (iii) the qualified mobile device consents to join the local network, and adding the set of qualified mobile device(s) to the local network.
The present invention provides semiconductor structures. The semiconductor structures may include a peripheral complimentary metal-oxide semiconductor (CMOS) substrate, a first vertical NAND cell on a first side of the CMOS substrate, and a second vertical NAND cell on a second side of the CMOS substrate opposite the first side.
H01L 27/11573 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by the peripheral circuit region
H01L 27/11529 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by the peripheral circuit region of memory regions comprising cell select transistors, e.g. NAND
An electronic component includes a first trace configured to transmit a first signal and a second trace configured to transmit a second signal. The electronic component further includes a layer of conductive material separated from the first and second traces by a layer of insulative material. The electronic component further includes a first vertical wall formed in direct contact with the layer of conductive material. The electronic component further includes a second vertical wall formed in direct contact with the layer of conductive material. The second vertical wall is separated from the first vertical wall by a void, and the void extends between the first trace and the second trace.
Deriving insights from time series data can include receiving subject matter expert (SME) input characterizing one or more aspects of a time series. A model template that specifies one or more components of the time series can be generated by translating the SME input using a rule-based translator. A machine learning model based on the model template can be a multilayer neural network having one or more component definition layers, each configured to extract one of the one or more components from time series data input corresponding to an instantiation of the time series. With respect to a decision generated by the machine learning model based on the time series data input, a component-wise contribution of each of the one or more components to the decision can be determined. An output can be generated, the output including the component-wise contribution of at least one of the one or more components.
A semiconductor structure is provided that includes a first FET device region including a plurality of first FETs, each first FET of the plurality of first FETs includes a first source/drain region located on each side of a functional gate structure. A second FET device region is stacked above the first FET device region and includes a plurality of second FETs, each second FET of the plurality of second FETs includes a second source/drain region located on each side of a functional gate structure. The structure further includes at least one first front side contact placeholder structure located adjacent to one of the first source/drain regions of at least one the first FETs, and at least one second front side contact placeholder structure located adjacent to at least one of the second source/drain regions of at one of the second FETs.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks overlying the first via level; a second via level forming a first top jumper overlying the first set of two or more first metallization tracks; and a second metallization track overlying the second via level.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Techniques for sidewall passivation and removal of redeposited materials and processing damage from phase change memory materials are provided. In one aspect, a phase change memory device includes: one or more phase change memory cells, where each of the phase change memory cells includes a phase change material between a bottom electrode and a top electrode; and a carbon and oxygen-containing passivation layer on sidewalls of the phase change material. An ovonic threshold switch can also be present between the bottom and top electrodes, in series with the phase change material, and the carbon and oxygen-containing passivation layer can also be present on sidewalls of the ovonic threshold switch. A method of fabricating the present phase change memory devices is also provided.
H01L 45/00 - Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
H01L 27/24 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
Semiconductor structures such as, for example, stacked nanosheet devices, having enhanced gate resistance are provided. The enhanced gate resistance is obtained by providing a shunting material pillar in the structure and along a sidewall (or opposing sidewalls) of at least one gate structure. The shunting material pillar has a resistivity that is lower than a resistivity of the gate structure that it is laterally adjacent to.
A semiconductor device including an interleaved/nested structure of subtractive interconnects and damascene interconnects. The semiconductor device includes a subtractive-etched interconnect wiring level having subtractive interconnects and a damascene interconnect wiring level having damascene interconnects. The subtractive-etched interconnect wiring level includes first electrodes that have a first potential second electrodes that have a second potential different from the first potential, with the second electrodes generated to interleave the first electrodes. The semiconductor also includes a damascene interconnect wiring level that includes other first electrodes having the first potential, and other second electrodes having the second potential. In the damascene interconnect wiring level, the other second electrodes are also interleaved by the other first electrodes.
H01L 23/528 - Layout of the interconnection structure
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A computer-implemented process for training a neural network includes the following operations. Return data received from a return channel is evaluated against a threshold. Based upon the threshold being satisfied, the return data is validated, and the return data is cognitive processed to generate a return insight. Using the neural network and based upon the return insight, a corrective action is generated. The neural network is trained using feedback generated based upon the corrective action. The threshold is then updated using the neural network.