Intel Corporation

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1.

EXITLESS GUEST TO HOST NOTIFICATION

      
Application Number 18285212
Status Pending
Filing Date 2021-06-25
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Wang, Wei
  • Tian, Kun
  • Neiger, Gilbert
  • Sankaran, Rajesh
  • Mallick, Asit
  • Tsai, Jr-Shian
  • Pan, Jacob Jun
  • Ergin, Mesut

Abstract

Embodiments of exitless guest to host (G2H) notification are described. In some embodiments, G2H is provided via an instruction. An exemplary processor includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode; and execution processing resources to execute the decoded single instruction according to the at least the opcode to cause an exitless guest to host notification from a virtual processor to a physical or virtual processor.

IPC Classes  ?

  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

2.

APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER

      
Application Number 18444379
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Wigton, Michelle M.
  • Munshi, Kambiz R.
  • Gu, Zhongyao Linda
  • Rashid, Mohammad M.
  • Lau, Victor
  • Ling, Jing

Abstract

Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • H10B 12/00 - Dynamic random access memory [DRAM] devices

3.

POWER SPECTRAL DENSITY LIMIT FOR 6 GHZ

      
Application Number 18542332
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Cariou, Laurent
  • Ouzieli, Ido
  • Cordeiro, Carlos
  • Yaghoobi, Hassan
  • Kenney, Thomas J.

Abstract

This disclosure describes systems, methods, and devices related to power spectral density (PSD) limit. A device may generate a frame comprising one or more elements to be sent to a first station device, wherein the frame is to be sent using a 6 GHz band. The device may include in the frame, information associated with a PSD limit on a per bandwidth size basis of the 6 GHz band. The device may cause to send the frame to the first station device.

IPC Classes  ?

  • H04W 52/34 - TPC management, i.e. sharing limited amount of power among users or channels or data types, e.g. cell loading
  • H04W 52/32 - TPC of broadcast or control channels
  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
  • H04W 52/52 - Transmission power control [TPC] using AGC [Automatic Gain Control] circuits or amplifiers

4.

RECEIVER-BASED PRECISION CONGESTION CONTROL

      
Application Number 18439459
Status Pending
Filing Date 2024-02-12
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Pan, Rong
  • Yebenes Segura, Pedro
  • Penaranda Cebrian, Roberto
  • Southworth, Robert
  • Musleh, Malek
  • Lee, Jeongkeun
  • Kim, Changhoon

Abstract

Examples described herein relate to a network agent, when operational, to: receive a packet, determine transmit rate-related information for a sender network device based at least on operational and telemetry information accumulated in the received packet, and transmit the transmit rate-related information to the sender network device. In some examples, the network agent includes a network device coupled to a server, a server, or a network device. In some examples, the operational and telemetry information comprises: telemetry information generated by at least one network device in a path from the sender network device to the network agent.

IPC Classes  ?

  • H04L 45/74 - Address processing for routing
  • G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
  • H04L 45/00 - Routing or path finding of packets in data switching networks
  • H04L 47/12 - Avoiding congestion; Recovering from congestion

5.

APPARATUS AND METHOD FOR SEAMLESS CONTAINER MIGRATION FOR GRAPHICS PROCESSORS AND ASSOCIATED DEVICES

      
Application Number 18543463
Status Pending
Filing Date 2023-12-18
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Wang, Zhenyu Z
  • Zhao, Xinda
  • Zhang, Owen

Abstract

Apparatus and method for migrating a container including graphics processor state. One embodiment of an apparatus comprises: a first graphics processor coupled to a first system memory; execution circuitry of the graphics processor to execute graphics operations of processes grouped into a plurality of containers, the execution circuitry to be shared by the plurality of containers; and a first container migration engine to migrate a first container of the plurality of containers to a second graphics processor coupled to a second system memory, the first container migration engine to freeze operation of the first container at a specified execution point defined by a first container state including process-visible state data and driver-visible state data, the first container migration engine to transmit the first container state to a second container migration engine associated with the second graphics processor and second system memory, the second container migration engine to restore the first container to the specified execution point using the process-visible state data and the driver-visible state data.

IPC Classes  ?

  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

6.

METHODS AND APPARATUS TO ASSIGN WORKLOADS BASED ON EMISSIONS ESTIMATES

      
Application Number 18542370
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Guim Bernat, Francesc
  • Kumar, Karthik
  • Thyagaturu, Akhilesh S.
  • Metsch, Thijs
  • Hoban, Adrian

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes programmable circuitry to at least: obtain a first response associated with an estimate of emissions to be produced by execution of a workload on first hardware; obtain a second response associated with an estimate of emissions to be produced by execution of the workload on second hardware; and assign one of the first or the second hardware to execute the workload based on the first response and the second response, the assigned one of the first or the second hardware to at least one of utilize more time or more memory to execute the workload than the other of the first or the second hardware.

IPC Classes  ?

  • G06Q 30/018 - Certifying business or products
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

7.

UPLINK IMPACT ON PUCCH SCELL ACTIVATION DELAY

      
Application Number 18288109
Status Pending
Filing Date 2022-10-20
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Li, Hua
  • Zhang, Meng
  • Chervyakov, Andrey
  • Huang, Rui
  • Bolotin, Iiya

Abstract

A computer-readable storage medium stores instructions to configure a UE for Scell activation in a 5G NR network, and to cause the UE to perform operations including decoding a first MAC CE received from a base station on a PDSCH. The first MAC CE includes a PUCCH SCell activation command. A second MAC CE is decoded, which includes PL-RS configuration information. DL activation process is performed within a pre-configured activation time starting at a first slot of the first MAC CE reception. The availability of a PL-RS is determined based on the PL-RS configuration information. CSLRS measurements are performed in response to the PUCCH SCell activation command. The CSLRS measurements include a path loss calculation performed within an extended time period starting after the DL activation process and having a duration based on the availability of the PL-RS.

IPC Classes  ?

8.

LIGHT DETECTION AND RANGING SYSTEMS

      
Application Number 18552927
Status Pending
Filing Date 2022-03-18
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Ain-Kedem, Liron
  • Rahamim, Gilad
  • Kroizer, Ahuva
  • Medlinsky, Avi

Abstract

A light detection and ranging system is provided. The light detection and ranging system includes a LIDAR scanning mirror; a processor configured to control the LIDAR scanning mirror; a first position sensor configured to determine a first position and a second position sensor configured to detect a second position of the LIDAR scanning mirror. The processor is configured to determine whether an eye-safety criterion is met based on the first position and the second position, and control light output of the LIDAR system based on whether the eye-safety criterion is met.

IPC Classes  ?

  • G01S 7/481 - Constructional features, e.g. arrangements of optical elements
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01S 7/497 - Means for monitoring or calibrating
  • G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles

9.

ALLOCATION OF ACCESS TO A CHIPLET ACROSS AN INTERCONNECT SWITCH

      
Application Number 18080635
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Guim Bernat, Francesc
  • Carranza, Marcos
  • Doshi, Kshitij
  • Smith, Ned
  • Kumar, Karthik

Abstract

Techniques and mechanisms to allocate functionality of a chiplet for access by one or more processor cores which are coupled to remote processor via a network switch. In an embodiment, a composite chip communicates with the switch via a Compute Express Link (CXL) link. The switch receives capability information which identifies both a chiplet of the composite chip, and a functionality which is available from a resource of that chiplet. Based on the capability information, the switch provides an inventory of chiplet resources. In response to an allocation request, the switch accesses the inventory to identify whether a suitable chiplet resource is available. Based on the access, the switch configures a chip to enable an allocation of a chiplet resource. In another embodiment, the chiplet resource is allocated at a sub-processor level of granularity, and disables access to the chiplet resource by one or more local processor cores.

IPC Classes  ?

10.

OPTIMIZED INTEGRATED CIRCUIT FOR QUANTUM COMPILATION AND EXECUTION

      
Application Number 18078781
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Matsuura, Anne
  • Khalate, Pradnya Laxman
  • Premaratne, Shavindra
  • Daraeizadeh, Sahar
  • Schmitz, Albert
  • Wu, Xin-Chuan
  • Mladenov, Todor
  • Barnett, Brandon

Abstract

Apparatus and method for compiling and executing hybrid classical-quantum programs. For example, one embodiment of an apparatus comprises: a host processor to perform a partial compilation on hybrid quantum-classical source code to generate one or more sequential blocks of quantum operations; a quantum compiler accelerator to receive compilation work offloaded by the host processor including the one or more sequential blocks of quantum operations, the quantum compiler to perform optimization operations to optimize runtime execution of one or more of the quantum operations in view if a quantum accelerator architecture to generate optimized quantum operations; and a quantum execution accelerator having the quantum accelerator architecture to execute the optimized quantum operations to manipulate a state of one or more qubits, to measure a state of the one or more qubits, and to provide measurement data indicating the state to the host processor.

IPC Classes  ?

  • G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers

11.

INTEGRATED CIRCUIT (IC) DEVICE WITH MULTI-PITCH PATTERN FABRICATED THROUGH CROSS-LINKABLE BLOCK COPOLYMER

      
Application Number 18064352
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Han, Eungnak
  • Gstrein, Florian
  • Singh, Gurpreet

Abstract

A cross-linkable diblock copolymer can facilitate multi-pitch patterning for forming an IC device. The IC device may include a metal layer with different pitches. The metal layer may include a first region having a first pitch and a second region having a second pitch that is greater than the first pitch. The cross-linkable diblock copolymer may be deposited over the metal layer. The portion of the diblock copolymer over the second region may be exposed to light (e.g., UV), which causes cross-linking of functional groups in the diblock copolymer. The cross-linking may form a structure that includes an amorphous phase of the diblock copolymer. The structure may be over and aligned with the second region of the metal layer. After the structure is formed, the diblock copolymer over the first region may self-assemble and form lamellar structures that are aligned with metal lines and insulative structures in the first region.

IPC Classes  ?

  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/8234 - MIS technology
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

12.

DETERMINATION OF GAZE POSITION ON MULTIPLE SCREENS USING A MONOCULAR CAMERA

      
Application Number 18584782
Status Pending
Filing Date 2024-02-22
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Sunray, Elad
  • Rudoy, Dmitry
  • Levy, Noam

Abstract

Systems and methods for real-time, efficient, monocular gaze position determination that can be performed in real-time on a consumer-grade laptop. Gaze tracking can be used for human-computer interactions, such as window selection, user attention on screen information, gaming, augmented reality, and virtual reality. Gaze position estimation from a monocular camera involves estimating the line-of-sight of a user and intersecting the line-of-sight with a two-dimensional (2D) screen. The system uses a neural network to determine gaze position within about four degrees of accuracy while maintaining very low computational complexity. The system can be used to determine gaze position across multiple screens, determining which screen a user is viewing as well as a gaze target area on the screen. There are many different scenarios in which a gaze position estimation system can be used, including different head poses, different facial expressions, different cameras, different screens, and various illumination scenarios.

IPC Classes  ?

  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06T 3/60 - Rotation of a whole image or part thereof
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
  • G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration

13.

ROOTS OF TRUST IN INTELLECTUAL PROPERTY (IP) BLOCKS IN A SYSTEM ON A CHIP (SOC)

      
Application Number 18064546
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Doshi, Kshitij
  • Smith, Ned M.
  • Poornachandran, Rajesh
  • Cheruvu, Sunil K.
  • Palmer, David W.

Abstract

The technology described herein includes a plurality of intellectual property (IP) blocks; and a host IP block, the host IP block including a primary root of trust (RoT) IP block (PRIB) coupled to the plurality of IP blocks, to receive a request from a computing system to establish a secure communications session with a selected one of a plurality of intellectual property (IP) blocks, authenticate and attest the computing system, sign evidence of the PRIB with a PRIB key, send the signed evidence of the PRIB to the computing system, and establish the secure communications session between the computing system and the selected IP block if the PRIB is trusted by the computing system based at least in part on the signed evidence of the PRIB.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • H04L 9/08 - Key distribution

14.

HUMAN POSTURE DETECTION

      
Application Number 18064519
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Pearce, David
  • Stanhill, David

Abstract

A user computing device includes a camera sensor and a depth sensor. Image data generated by the camera captures an image of a user of the user computing device and is provided as an input to a first machine learning model trained to determine a feature set associated with posture of the user from the image data. Depth data generated by the depth sensor contemporaneously with generation of the image data is provided as input to a second machine learning model along with the first feature set to generate a second feature set as an output of the second machine learning model based on the depth data and the first feature set. The posture of the user is determined from the second feature set to provide feedback to the user.

IPC Classes  ?

  • G06V 40/10 - Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 40/60 - Static or dynamic means for assisting the user to position a body part for biometric acquisition

15.

PREFERRED APP REGISTRATION IN MEC DUAL DEPLOYMENTS

      
Application Number 18288005
Status Pending
Filing Date 2022-08-31
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Sabella, Dario
  • Shailendra, Samar
  • Filippou, Miltiadis

Abstract

Various approaches are provided for enabling Edge Dual Deployment (EDD). EDD includes Multi-access edge computing (MEC) Dual Deployments (MDD) initialization performed as a preliminary step before the actual registration, as a mechanism to allow the two platforms (EES and MEC platform) to communicate directly. MDD establishment is a dual registration mechanism of the edge application in the EDD environment. MDD update and closing are analogous registration update and de-registration processes, with both sub-cases.

IPC Classes  ?

  • H04L 67/289 - Intermediate processing functionally located close to the data consumer application, e.g. in same machine, in same home or in same sub-network
  • H04L 67/51 - Discovery or management thereof, e.g. service location protocol [SLP] or web services

16.

METHOD AND APPARATUS TO BATCH PACKET FRAGMENTS PRIOR TO ENTRANCE INTO A PROCESSING CORE QUEUE

      
Application Number CN2022136666
Publication Number 2024/119325
Status In Force
Filing Date 2022-12-05
Publication Date 2024-06-13
Owner INTEL CORPORATION (USA)
Inventor
  • Devassykutty Pullokaran, Joy
  • Tang, Zhijun
  • Aimangala Nagaraja Setty, Ravikumar
  • Khandelwal, Deepak
  • Chidambaram, Rajakumar
  • Vincent Solomon, Joseph Maria Jaison
  • Chintalapalle, Balaji
  • Koduri, Satya Venkata Naga Harish
  • Gujjar, Abhinandan
  • Jing, Yiming
  • Wang, Xiao
  • Wang, Dong
  • Zhang, Pan
  • Guo, Junfeng

Abstract

An apparatus is described. An apparatus includes first circuitry to determine a particular processing core amongst a plurality of processing cores for an IP fragment based at least in part on the IP fragment's IP fragmentation ID. The apparatus includes second circuitry to enqueue the IP fragment for the particular processing core.

IPC Classes  ?

17.

VISUAL QUALITY ENHANCEMENT IN CLOUD GAMING BY 3D INFORMATION-BASED SEGMENTATION AND PER-REGION RATE DISTORTION OPTIMIZATION

      
Application Number CN2022137282
Publication Number 2024/119404
Status In Force
Filing Date 2022-12-07
Publication Date 2024-06-13
Owner INTEL CORPORATION (USA)
Inventor
  • He, Fan
  • Lin, Yunbiao
  • Panneer, Selvakumar

Abstract

This disclosure describes systems, methods, and devices related to enhanced gaming visual quality. A device may identify one or more first Gbuffers received from a game, wherein the one or more first Gbuffers are associated with a first frame of the game. The device may analyze the one or more first Gbuffers. The device may segment the one or more first Gbuffers into a plurality of regions. The device may perform a per-region rate distortion optimization (PRRDO). The device may optimize a quality of the frame based on the PRRDO.

IPC Classes  ?

  • H04N 19/127 - Prioritisation of hardware or computational resources

18.

METHODS AND APPARATUS FOR A WIRELESS COMMUNICATION DEVICE TO ENABLE A BODY PROXIMITY SENSING OPERATION

      
Application Number 18063143
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Meyuhas, Gil
  • Kogos, Noam
  • Langer, Adiel

Abstract

Methods and apparatus are provided to control a body proximity sensing operation. An apparatus for a wireless communication device, the apparatus may include an interface to a radio frequency (RF) transceiver, and processing circuitry configured to: monitor one or more transmit power limitation parameters used to limit transmit power of transmissions of RF communication signals, and cause, based on a first transmit power limit including a monitored transmit power limitation parameter and a second transmit power limit, the RF transceiver to perform a body proximity sensing operation.

IPC Classes  ?

  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
  • H04W 52/28 - TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission

19.

PHOTONIC INTEGRATED CIRCUIT PACKAGE SUBSTRATE WITH VERTICAL OPTICAL COUPLERS

      
Application Number 18078871
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Liu, Changhua
  • May, Robert A.
  • Nie, Bai

Abstract

An integrated circuit (IC) package substrate comprises an upper surface, a lower surface opposite the upper surface, and an outer side surface extending between the upper surface and the lower surface. At least one optical path is in a plane of the IC package substrate, and at least one vertical optical coupler at an upper or lower surface of the IC package substrate is optically coupled to the optical path.

IPC Classes  ?

  • G02B 6/42 - Coupling light guides with opto-electronic elements

20.

STREAMLINING PROTOCOL LAYERS PROCESSING, AND SLOTLESS OPERATION

      
Application Number 18529625
Status Pending
Filing Date 2023-12-05
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Hamidi-Sepehr, Fatemeh
  • Narasimha, Murali
  • Zhang, Yujian
  • Emara, Mustafa
  • Li, Qian

Abstract

A non-transitory computer-readable storage medium stores instructions for execution by one or more processors of user equipment (UE). The instructions cause the UE to encode a scheduling request (SR) for transmission to a base station during one of a plurality of SR occasions. The SR includes an indication based on a size of an uplink (UL) data packet. Control information received from the base station in response to the SR is decoded. The control information includes a scheduling grant based on the size of the UL data packet. The UL data packet is encoded for transmission using the scheduling grant. The UL data packet is encoded for transmission using the scheduling grant.

IPC Classes  ?

  • H04W 72/0446 - Resources in time domain, e.g. slots or frames
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network

21.

ANTENNA DESIGN AND ARRANGEMENT METHODOLOGIES FOR SAR AND POWER DENSITY HUMAN EXPOSURE OPTIMIZATION

      
Application Number 18063100
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • El Hajj, Walid
  • Roman, John
  • Asrih, Nawfal

Abstract

Methods of arranging and designing antennas to optimize electromagnetic field distributions in the near-field region of an antenna to optimize parameters such as electric field (E-field), magnetic field (H-field), specific absorption rate (SAR), power density (PD), etc. while ensuring specific performance of the antenna in the far-field region in terms of gain, efficiency, radiation pattern, etc.

IPC Classes  ?

  • H01Q 1/24 - Supports; Mounting means by structural association with other equipment or articles with receiving set
  • G01R 29/08 - Measuring electromagnetic field characteristics

22.

BWP-BASED OPERATIONS FOR REDCAP USER EQUIPMENTS

      
Application Number 18279382
Status Pending
Filing Date 2022-03-22
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Chatterjee, Debdeep
  • Xiong, Gang
  • Islam, Toufiqul
  • Li, Yingyang

Abstract

A computer-readable storage medium stores instructions to configure a UE for Reduced Capability (RedCap) operation in a 5G NR network, and to cause the UE to perform operations. The operations include decoding a master information block (MIB) to determine a control resource set (CORESET) and a common search space (CSS): decoding a system information block (SIB) in a physical downlink shared channel (PDSCH) scheduled by a downlink control information (DCI) format, the DCI format received based on the CORESET and the CSS: determining an additional CORESET within a separate initial DE BWP using the SIB: and performing reception of a physical downlink control channel (PDCCH) in a PDCCH Type1 Common Search Space (CSS) set or a PDSCH associated with Random Access (RA) procedure in the separate initial DE BWP.

IPC Classes  ?

  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 74/0833 - Random access procedures, e.g. with 4-step access

23.

INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TESTING

      
Application Number 18389625
Status Pending
Filing Date 2023-12-19
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Rao, Valluri R.
  • Morrow, Patrick
  • Mehandru, Rishabh
  • Ingerly, Doug
  • Jun, Kimin
  • O'Brien, Kevin
  • Fischer, Paul
  • Liao, Szuya S.
  • Block, Bruce

Abstract

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

IPC Classes  ?

  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • G01R 1/073 - Multiple probes
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/66 - Types of semiconductor device

24.

TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION

      
Application Number 18542308
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor Bernat, Francesc Guim

Abstract

Technologies for dynamic accelerator selection include a compute sled. The compute sled includes a network interface controller to communicate with a remote accelerator of an accelerator sled over a network, where the network interface controller includes a local accelerator and a compute engine. The compute engine is to obtain network telemetry data indicative of a level of bandwidth saturation of the network. The compute engine is also to determine whether to accelerate a function managed by the compute sled. The compute engine is further to determine, in response to a determination to accelerate the function, whether to offload the function to the remote accelerator of the accelerator sled based on the telemetry data. Also the compute engine is to assign, in response a determination not to offload the function to the remote accelerator, the function to the local accelerator of the network interface controller.

IPC Classes  ?

  • H04L 9/08 - Key distribution
  • B25J 15/00 - Gripping heads
  • G06F 1/18 - Packaging or power distribution
  • G06F 1/20 - Cooling means
  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/28 - Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel
  • G06F 9/44 - Arrangements for executing specific programs
  • G06F 9/4401 - Bootstrapping
  • G06F 9/445 - Program loading or initiating
  • G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
  • G06F 12/14 - Protection against unauthorised use of memory
  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 13/40 - Bus structure
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
  • G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F 16/11 - File system administration, e.g. details of archiving or snapshots
  • G06F 16/22 - Indexing; Data structures therefor; Storage structures
  • G06F 16/23 - Updating
  • G06F 16/2453 - Query optimisation
  • G06F 16/2455 - Query execution
  • G06F 16/248 - Presentation of query results
  • G06F 16/25 - Integrating or interfacing systems involving database management systems
  • G06F 16/901 - Indexing; Data structures therefor; Storage structures
  • G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
  • G06F 30/34 - Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06Q 10/0631 - Resource planning, allocation, distributing or scheduling for enterprises or organisations
  • G06Q 30/0283 - Price estimation or determination
  • G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C 29/36 - Data generation devices, e.g. data inverters
  • G11C 29/38 - Response verification devices
  • G11C 29/44 - Indication or identification of errors, e.g. for repair
  • H04L 9/40 - Network security protocols
  • H04L 41/0213 - Standardised network management protocols, e.g. simple network management protocol [SNMP]
  • H04L 41/0668 - Management of faults, events, alarms or notifications using network fault recovery by dynamic selection of recovery network elements, e.g. replacement by the most appropriate element after failure
  • H04L 41/0677 - Localisation of faults
  • H04L 41/0893 - Assignment of logical groups to network elements
  • H04L 41/0896 - Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
  • H04L 41/14 - Network analysis or design
  • H04L 41/5019 - Ensuring fulfilment of SLA
  • H04L 41/5025 - Ensuring fulfilment of SLA by proactively reacting to service quality change, e.g. by reconfiguration after service quality degradation or upgrade
  • H04L 45/28 - Routing or path finding of packets in data switching networks using route fault recovery
  • H04L 45/7453 - Address table lookup; Address filtering using hashing
  • H04L 47/11 - Identifying congestion
  • H04L 47/125 - Avoiding congestion; Recovering from congestion by balancing the load, e.g. traffic engineering
  • H04L 49/00 - Packet switching elements
  • H04L 49/351 - Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
  • H04L 49/40 - Constructional details, e.g. power supply, mechanical construction or backplane
  • H04L 49/9005 - Buffering arrangements using dynamic buffer space allocation
  • H04L 67/1001 - Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers
  • H04L 67/1008 - Server selection for load balancing based on parameters of servers, e.g. available memory or workload
  • H04L 69/12 - Protocol engines
  • H04L 69/22 - Parsing or analysis of headers
  • H04L 69/32 - Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
  • H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
  • H05K 7/14 - Mounting supporting structure in casing or on frame or rack
  • H05K 7/18 - Construction of rack or frame
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

25.

PATH SELECTION FOR PACKET TRANSMISSION

      
Application Number 18424376
Status Pending
Filing Date 2024-01-26
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Agrawal, Anurag
  • Fingerhut, John Andrew
  • Ding, Xiaoyan
  • Zhang, Song

Abstract

Examples described herein relate to a network interface device comprising a multi-stage programmable packet processing pipeline circuitry to determine a path to transmit a packet based on relative network traffic transmitted via multiple paths. In some examples, determine a path to transmit a packet is based on Deficit Round Robin (DRR). In some examples, the programmable packet processing pipeline circuitry includes: a first stage to manage two or more paths, wherein a path of the two or more paths of the first stage is associated with two or more child nodes, a second stage to manage two or more paths, wherein a path of the two or more paths of the second stage is associated with two or more child nodes, and at least one child node is associated with the determined path.

IPC Classes  ?

  • H04L 47/628 - Queue scheduling characterised by scheduling criteria for service slots or service orders based on packet size, e.g. shortest packet first
  • H04L 45/24 - Multipath
  • H04L 49/00 - Packet switching elements

26.

INTEGRATED PHOTONIC DEVICE AND ELECTRONIC DEVICE ARCHITECTURES

      
Application Number 18080152
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Nad, Suddhasattwa
  • Marin, Brandon
  • Ecton, Jeremy
  • Duan, Gang
  • Pietambaram, Srinivas

Abstract

Apparatuses, systems, assemblies, and techniques related to integrating photonics integrated circuit devices and electronic integrated circuit devices into an assembly or module are described. An integrated module includes a photonics integrated circuit device within an opening of a glass core substrate and an electronic integrated circuit device direct bonded to the photonics integrated circuit device. An optical waveguide is within or on the glass core substrate and has a terminal end edge coupled to the photonics integrated circuit device within the opening.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons

27.

DYNAMIC HARDWARE INTEGRITY AND/OR REPLAY PROTECTION

      
Application Number 18266379
Status Pending
Filing Date 2020-12-26
First Publication Date 2024-06-13
Owner INTEL CORPORATION (USA)
Inventor Chhabra, Siddhartha

Abstract

Techniques for dynamically configurable Scalable Memory Integrity and Enhanced Reliability, Availability, and Serviceability (SMIRAS) are described. A SMIRAS based system may be enabled to use an integrity-based metadata organization, a replay protection-based metadata organization, or a combination of both metadata organizations.

IPC Classes  ?

  • G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 21/60 - Protecting data

28.

EQUALIZING AND TRACKING SPEAKER VOICES IN SPATIAL CONFERENCING

      
Application Number 18078051
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Cherukkate, Sumod
  • Beltman, Willem
  • Hanchate, Mallari
  • Potluri, Srikanth
  • Manepalli, Sangeeta
  • Srivastav, Abhishek

Abstract

This disclosure describes systems, methods, and devices related to user tracking. A device may identify metadata comprising depth sensing information and camera information received from an in-room device located at a first location having a first camera. The device may perform face recognition on one or more in-room users. The device may calculate a distance of a first in-room user based on the metadata and a first number of pixels across the face of the first in-room user. The device may calculate a distance between the first in-room user and a second in-room user based on the metadata and the first number of pixels across the face of the first in-room user and a number of pixels across the face of the second in-room user.

IPC Classes  ?

  • G10L 21/0364 - Speech enhancement, e.g. noise reduction or echo cancellation by changing the amplitude for improving intelligibility
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06T 7/50 - Depth or shape recovery
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
  • H04R 1/32 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired directional characteristic only

29.

SCELL DORMANCY SWITCHING WITH SCELL-PCELL CROSS-CARRIER SCHEDULING

      
Application Number 18278749
Status Pending
Filing Date 2022-05-11
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Han, Seunghee
  • Li, Yingyang
  • Wang, Yi

Abstract

An apparatus and system are described to support secondary cell (SCell) dormancy switching when cross-carrier scheduling (CCS) from SCell to primary cell (PCell) transmission is supported are described. A physical downlink control channel (PDCCH) transmission on the sSCell has a downlink control information format (DCI) format 0_1 or 1_1 containing a SCell dormancy indication field and a CIF are used to indicate CCS and SCell dormancy switching to deactivate the SCell. The CIF value is either 0 or indicates the PCell and may depend on whether physical downlink shared channel (PDSCH) transmission is scheduled. The DCI triggers bandwidth part (BWP) switching for the PCell to indicate to the UE to switch to monitoring UE-specific search space sets on the PCell instead of on the SCell.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling

30.

CRYPTOGRAPHIC DATA PROCESSING USING A DMA ENGINE

      
Application Number 18442457
Status Pending
Filing Date 2024-02-15
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Doshi, Kshitij Arun
  • Qureshi, Uzair
  • Mosur, Lokpraveen
  • Fleming, Patrick
  • Doyle, Stephen
  • Keating, Brian Andrew
  • Smith, Ned M.

Abstract

A computing device includes a direct memory access (DMA) engine coupled to a memory, a network interface, and processing circuitry. The processing circuitry is to perform a secure exchange with a second computing device to negotiate a shared encryption key, based on a request for data received via the network interface from the second computing device. The DMA engine is to retrieve the data from a storage location based on an encryption command. The encryption command indicates the storage location. The DMA engine is to encrypt the data based on the shared encryption key to generate encrypted data, and store the encrypted data in the memory.

IPC Classes  ?

  • H04L 9/40 - Network security protocols
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
  • G06F 21/60 - Protecting data

31.

INTEGRATION OF FINFET AND GATE-ALL-AROUND DEVICES

      
Application Number 18077394
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Jun, Hwichan
  • Bouche, Guillaume

Abstract

Techniques to form semiconductor devices that include both finFET and gate-all-around (GAA) devices on same substrate. The finFET and GAA devices may have different gate oxide thicknesses and/or shallow trench isolation (STI) thicknesses, along with coplanar channel regions. In an example, a first semiconductor device includes a finFET structure with a first gate structure around or otherwise on a semiconductor fin while a second semiconductor device includes a GAA structure with a second gate structure around or otherwise on a plurality of semiconductor bodies (e.g., nanoribbons). The first gate structure includes a first gate dielectric and a first gate electrode (e.g., conductive material such as workfunction material and/or gate fill metal) and the second gate structure includes a second gate dielectric and a second gate electrode. The first gate dielectric includes a first gate oxide layer that is thicker than a second gate oxide layer of the second gate dielectric.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

32.

MECHANISM TO OVERRIDE STANDBY POWER IN LARGE MEMORY CONFIGURATION OF WORKSTATIONS TO ELIMINATE THE NEED TO INCREASE POWER OF STANDBY POWER RAIL

      
Application Number 18077131
Status Pending
Filing Date 2022-12-07
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Tan, Chuen Ming
  • Gopalakrishnan, Venkataramani
  • Tuljapurkar, Aneesh
  • Somayaji, Vishwanath
  • Yasmin, Tabassum

Abstract

Embodiments herein relate to a circuit which allows the re-use of an existing power supply units having main power rails and an auxiliary power rail, while supporting large memory configurations in a sleep state to avoid data loss. A processor determines whether a power requirement of memory modules in a computing device exceeds an available power of the auxiliary power rail. If this is the case, the processor asserts an override signal which is used by a logic circuit to force the power supply to remain on in the sleep state. A set of switches disconnect the main rails from other components which can be turned off in the sleep state. A select circuit selects one of the main rails to power the memory modules.

IPC Classes  ?

  • G06F 1/3225 - Monitoring of peripheral devices of memory devices
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system

33.

PHYSICAL-LAYER CELL IDENTIFIER (PCI) CONFIGURATION AND MOBILITY ROBUSTNESS OPTIMIZATION FOR FIFTH GENERATION SELF-ORGANIZING NETWORKS (5G SON)

      
Application Number 18397802
Status Pending
Filing Date 2023-12-27
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Chou, Joey
  • Yao, Yizhi

Abstract

Methods, systems, and storage media are described for physical-layer cell identifier (PCI) configuration and Mobility Robustness Optimization (MRO). In particular, some embodiments may be directed to fifth-generation self-organizing network (5G SON) solutions such as the management of distributed physical-layer cell identifier (PCI) configuration, centralized PCI configuration, and MRO. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • H04W 24/04 - Arrangements for maintaining operational condition
  • H04L 61/5046 - Resolving address allocation conflicts; Testing of addresses
  • H04W 8/26 - Network addressing or numbering for mobility support
  • H04W 24/10 - Scheduling measurement reports
  • H04W 84/18 - Self-organising networks, e.g. ad hoc networks or sensor networks

34.

APPARATUS AND METHOD FOR ELECTROLESS SURFACE FINISHING ON GLASS

      
Application Number 18065250
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Darmawikarta, Kristof
  • Cho, Steve S.
  • Tanaka, Hiroki
  • Chen, Haobo
  • Duan, Gang
  • Marin, Brandon Christian
  • Nad, Suddhasattwa
  • Pietambaram, Srinivas V.

Abstract

Apparatus and methods for electroless surface finishing on glass. A planarization process is performed on buildup dielectric and/or solder resist to create a flatter, more planar, upper surface for a substrate having a glass layer. Planarity is characterized by having surface variations of less than about 5 microns, as measured by recesses and/or protrusions. The planar surface enables finishing the substrate surface with an electroless NiPdAu process.

IPC Classes  ?

  • H01L 23/15 - Ceramic or glass substrates
  • C23C 18/16 - Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, i.e. electroless plating
  • C23C 18/18 - Pretreatment of the material to be coated
  • C23C 18/48 - Coating with alloys
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

35.

LOW Z-HEIGHT, GLASS-REINFORCED PACKAGE WITH EMBEDDED BRIDGE

      
Application Number 18080612
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Duan, Gang
  • Manepalli, Rahul
  • Pietambaram, Srinivas
  • Marin, Brandon
  • Nad, Suddhasattwa
  • Ecton, Jeremy

Abstract

An integrated circuit (IC) package comprises a first IC die having first metallization features, a second IC die having second metallization features, and a third IC die having third metallization features. A glass layer is between the third IC die and both of the first IC die and the second IC die. A plurality of first through vias extend through the glass layer, coupling the third metallization features with first ones of the first metallization features and with first ones of the second metallization features. A plurality of second through vias extend through the glass layer. A dielectric material is around the third die and a package metallization is within the dielectric material. The package metallization is coupled to at least one of the first, second, or third IC die, and terminating at a plurality of package interconnect interfaces.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

36.

MULTI-PITCH PATTERNING THROUGH ONE-STEP FLOW

      
Application Number 18064362
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Rajeeva, Bharath Bangalore
  • Chandhok, Manish
  • Singh, Gurpreet
  • Huggins, Kevin
  • Han, Eungnak
  • Gstrein, Florian
  • Radosavljevic, Marko

Abstract

An IC device may include a first conductive structure in a first section and a second conductive structure in a second section. The second conductive structure is in parallel with the first conductive structure in a first direction. A dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. The first conductive structure may be coupled to a channel region of a transistor. The second conductive structure may be coupled to a channel region of another transistor. A first structure comprising a first dielectric material may be over the first conductive structure. A second structure comprising a second dielectric material may be over the second section. A third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

37.

TECHNIQUES TO ALLOCATE MEMORY FOR IN-LINE OR IN-BAND ERROR CORRECTION CONTROL

      
Application Number 18078984
Status Pending
Filing Date 2022-12-11
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Shankar, Vaibhav
  • Radjai, Amir Ali
  • Rajendran, Jaishankar
  • Binboga, Evrim
  • Kodali, Prashant

Abstract

Examples include techniques associated with allocating memory capacity of a memory partitioned to include a first region arranged to include in-line or in-band error correction control (IBECC) memory and a second region arranged to include non-IBECC memory. The first and second regions can be re-sized based on usage of either region reaching a threshold.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G11C 29/54 - Arrangements for designing test circuits, e.g. design for test [DFT] tools

38.

CHEMICAL MECHANICAL POLISHING OF CARBON HARD MASK

      
Application Number 18077658
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Prince, Matthew J.
  • Shrivastava, Amitesh
  • Hafez, Walid M.
  • Jain, Anurag A.
  • Ding, Gary
  • Hegde, Sharath
  • Kilroy, Caitlin M.
  • Kim, Inki

Abstract

Techniques are provided herein to use a chemical mechanical polishing (CMP) process to polish carbon hard mask (CHM) for a variety of useful semiconductor fabrication applications. In one example, a CMP process that uses a silica-based slurry is used to polish CHM formed over gate trenches of different widths, such that the CHM can recess to substantially the same height within the gate trenches of different widths. In another example, CHM may be deposited over groups of fins or a backbone structure and polished using a CMP process with a silica-based slurry to ensure a planar top surface of CHM over the groups of fins or backbone structure.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device

39.

SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX OPERATIONS

      
Application Number 18444254
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Valentine, Robert
  • Charney, Mark J.
  • Ould-Ahmed-Vall, Elmoustapha
  • Baum, Dan
  • Sperber, Zeev
  • Corbal, Jesus
  • Toll, Bret L.
  • Sade, Raanan
  • Yanover, Igor
  • Gebil, Yuri
  • Rappoport, Rinat
  • Shwartsman, Stanislav
  • Adelman, Menachem
  • Rubanovich, Simon

Abstract

Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 7/485 - Adding; Subtracting
  • G06F 7/487 - Multiplying; Dividing
  • G06F 7/76 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 17/16 - Matrix or vector computation

40.

UNIFIED ENCRYPTION ACROSS MULTI-VENDOR GRAPHICS PROCESSING UNITS

      
Application Number 18065611
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Yudha, Ardhi Wiratama Baskara
  • Lal, Reshma

Abstract

An apparatus comprises a local computer readable memory, a compute processor comprising one or more processing resources to execute a compute process, and a cryptographic processor to prefetch encrypted compute data for the compute processor and decrypt the compute data prior to making the compute data accessible to the compute processor.

IPC Classes  ?

41.

FAN OUT PACKAGE WITH INTEGRATED PERIPHERAL DEVICES AND METHODS

      
Application Number 18587331
Status Pending
Filing Date 2024-02-26
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Keser, Lizabeth
  • Waidhas, Bernd
  • Ort, Thomas
  • Wagner, Thomas

Abstract

A semiconductor device and method of including peripheral devices into a package is disclosed. In one example, a peripheral device includes a passive device such as a capacitor or an inductor. Examples are shown that include a peripheral device that is substantially the same thickness as a die or a die assembly. Examples are further shown that use this configuration in a fan out process to form semiconductor devices.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

42.

DATA FUNCTIONS AND PROCEDURES IN THE NON-REAL TIME RADIO ACCESS NETWORK INTELLIGENT CONTROLLER

      
Application Number 18553552
Status Pending
Filing Date 2022-06-06
First Publication Date 2024-06-13
Owner INTEL CORPORATION (USA)
Inventor
  • Ying, Dawei
  • Ruan, Leifeng
  • Ding, Zongrui
  • Li, Qian
  • Han, Jaemin
  • Wu, Geng

Abstract

This disclosure describes systems, methods, and devices related to data functions. A device may identify a first request received from a data consumer non-RT RIC application (rApp), wherein the first request is received over an R1 termination interface. The device may cause to send a first response to the data consumer rApp in response to the first request. The device may identify a data producer rApp by checking a data catalog in order to satisfy the first request. The device may cause to send a notification frame to the data consumer rApp over the R1 termination interface indicating that data will be delivered to the data consumer rApp.

IPC Classes  ?

  • H04W 4/60 - Subscription-based services using application servers or record carriers, e.g. SIM application toolkits
  • H04W 8/18 - Processing of user or subscriber data, e.g. subscribed services, user preferences or user profiles; Transfer of user or subscriber data

43.

MOBILE RADIO TERMINAL DEVICE, COMMUNICATION DEVICE FOR CONFIGURING A MOBILE RADIO TERMINAL DEVICE, AND METHODS FOR CONFIGURING A MOBILE RADIO TERMINAL DEVICE

      
Application Number 18063091
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Das, Sajal Kumar
  • Srinivasareddy, Madhukiran
  • Thakur, Jayprakash
  • Tamrakar, Maruti
  • Hanchate, Mallari
  • Aagiru, Vamshi Krishna
  • Prabha, Abhijith
  • Gupta, Sagar
  • Hegde, Mythili

Abstract

A mobile radio terminal device may include a processor configured to receive information that one or more antennas of the mobile radio terminal device are in proximity of a human body part of a user of the mobile radio terminal device, modify a transmission configuration of the mobile radio terminal device based on the received information, and generate a message representing the changed transmission configuration.

IPC Classes  ?

  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04W 52/28 - TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission

44.

TECHNOLOGIES FOR MANAGING CACHE QUALITY OF SERVICE

      
Application Number 18394888
Status Pending
Filing Date 2023-12-22
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Gasparakis, Iosif
  • Bhandaru, Malini K.
  • Sunku, Ranganath

Abstract

Technologies for managing cache quality of service (QoS) include a compute node that includes a network interface controller (NIC) configured to identify a total amount of available shared cache ways of a last level cache (LLC) of the compute node and identify a destination address for each of a plurality of virtual machines (VMs) managed by the compute node. The NIC is further configured to calculate a recommended amount of cache ways for each workload type associated with VMs based on network traffic to be received by the NIC and processed by each of the VMs, wherein the recommended amount of cache ways includes a recommended amount of hardware I/O LLC cache ways and a recommended amount of isolated LLC cache ways usable to update a cache QoS register that includes the recommended amount of cache ways for each workload type. Other embodiments are described herein.

IPC Classes  ?

  • H04L 41/5003 - Managing SLA; Interaction between SLA and QoS
  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
  • G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
  • H04L 43/08 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
  • H04L 47/70 - Admission control; Resource allocation
  • H04L 67/568 - Storing data temporarily at an intermediate stage, e.g. caching

45.

SPECIFIC ABSORPTION RATE MANAGEMENT AND SELECTION OF LINK RATE CONSIDERING SPECIFIC ABSORPTION RATE PARAMETERS

      
Application Number 18063094
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Intel Corporation (USA)
Inventor
  • Aagiru, Vamshi Krishna
  • Ananda, Nithesha
  • Ap, Santhosh
  • Chatterjee, Abir
  • Das, Sajal Kumar
  • El Hajj, Walid
  • Kogos, Noam
  • Langer, Adiel
  • Meyuhas, Gil
  • Rubin, Amir
  • Shachar, Michael
  • Shetty, Nidhi P.
  • Srinivasareddy, Madhukiran
  • Velasco, Ricardo

Abstract

Devices with radiating antennas are subject to various regulations designed to limit the absorption of radiofrequency energy in a human body part in close proximity to a radiating antenna. Various conventional strategies are available for management of transmissions to comply with these regulations; however, each of these conventional strategies has drawbacks, such as a negative effect on the wireless link. Various strategies are disclosed herein to comply with the requisite regulations while maintaining the wireless link. In addition, strategies are presented to select wireless link rates, taking into account limitations that may be in place to satisfy the necessary regulations.

IPC Classes  ?

  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
  • H04W 52/22 - TPC being performed according to specific parameters taking into account previous information or commands
  • H04W 76/28 - Discontinuous transmission [DTX]; Discontinuous reception [DRX]

46.

UPLINK POSITIONING REFERENCE SIGNAL (UL-PRS) ADAPTATIONS AND EXTENSIONS FOR SENSING IN JOINT COMMUNICATION AND SENSING SYSTEMS

      
Application Number US2023082297
Publication Number 2024/123677
Status In Force
Filing Date 2023-12-04
Publication Date 2024-06-13
Owner INTEL CORPORATION (USA)
Inventor
  • Hamidi-Sepehr, Fatemeh
  • Hewavithana, Thushara
  • Lehne, Mark
  • Li, Qian
  • Chatterjee, Debdeep

Abstract

Various embodiments herein relate to identifying, by a user equipment (UE), an uplink positioning reference signal (UL-PRS) resource based on a 5G NR Sounding Reference Signal (SRS), wherein the UL-PRS resource is related to sensing to be performed during a sensing operation, wherein a UL-PRS resource includes a plurality of UL-PRS symbols. The UE may further generate a cellular transmission that includes a symbol repetition interval (SRI) based on the UL-PRS resource. The UE may further transmit the cellular transmission during performance of the sensing operation. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling

47.

XEON

      
Application Number 233200300
Status Pending
Filing Date 2024-06-11
Owner Intel Corporation (USA)
NICE Classes  ? 00 - No classifiable goods/services

Goods & Services

(1) Artificial intelligence computers; artificial intelligence PCs; artificial intelligence supercomputers; computer hardware and software for machine learning, deep learning, natural language generation, statistical learning, supervised learning, un-supervised learning, data mining, predictive analytics, and inferencing; neural networks; edge computing hardware and software featuring artificial intelligence, machine learning, and deep learning; computer hardware to support artificial intelligence, machine learning, deep learning, cognitive computing, data mining, computer vision, predictive analytics, and inferencing; hardware and software for artificial intelligence and systems for autonomous navigation of motor vehicles and power management of EVs; hardware and software for artificial intelligence for use in semiconductor manufacturing systems; software using artificial intelligence for machine learning; artificial intelligence platforms comprised of computer hardware and software for high performance computing and distributed computing; computer hardware and software for artificial intelligence high performance computing; hardware and software for processing, generating, understanding, and analyzing natural language; computer hardware for use in large language models and artificial intelligence; downloadable and recorded software for use in large language models and artificial intelligence machine-based systems that generate outputs such as predictions or content based on inferencing; computer hardware and software to enable the programming or training of a device; downloadable and recorded software to interpret data using automated processing designed to approximate cognitive abilities, make predictions or inferences; machine-based cognitive architectures and neural networks; artificial neural networks; software and hardware for creating and generating images from text of speech

48.

Technologies for reduction of memory effects in a capacitor for qubit gate control

      
Application Number 17827570
Grant Number 12009813
Status In Force
Filing Date 2022-05-27
First Publication Date 2024-06-11
Grant Date 2024-06-11
Owner Intel Corporation (USA)
Inventor
  • Subramanian, Sushil
  • Pellerano, Stefano
  • Mladenov, Todor
  • Park, Jongseok
  • Patra, Bishnu Prasad

Abstract

Technologies for the reduction of memory effects in a capacitor are disclosed. In the illustrative embodiment, a companion chip is connected to a quantum processor. The companion chip provides voltages to gates of qubits on the quantum processor. The companion chip includes an array of capacitors that can be charged to a voltage based on a voltage to be applied to a gate of the quantum processor. The capacitors in the array of capacitors are connected to the gate one at a time, charging up a parasitic capacitance. As more capacitors are switched, the voltage on the gate approaches a target voltage with an exponentially-decreasing voltage error.

IPC Classes  ?

  • H03K 17/92 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of superconductive devices
  • G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
  • H03M 1/66 - Digital/analogue converters
  • H10N 60/10 - Junction-based devices

49.

XEON

      
Serial Number 98592986
Status Pending
Filing Date 2024-06-10
Owner Intel Corporation ()
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

artificial intelligence computers; artificial intelligence PCs; artificial intelligence supercomputers; computer hardware and software for machine learning, deep learning, natural language generation, statistical learning, supervised learning, un-supervised learning, data mining, predictive analytics, and inferencing; neural networks; edge computing hardware and software featuring artificial intelligence, machine learning, and deep learning; computer hardware to support artificial intelligence, machine learning, deep learning, cognitive computing, data mining, computer vision, predictive analytics, and inferencing; hardware and software for artificial intelligence and systems for autonomous navigation of motor vehicles and power management of EVs; hardware and software for artificial intelligence for use in semiconductor manufacturing systems; software using artificial intelligence for machine learning; artificial intelligence platforms comprised of computer hardware and software for high performance computing and distributed computing; computer hardware and software for artificial intelligence high performance computing; hardware and software for processing, generating, understanding, and analyzing natural language; computer hardware for use in large language models and artificial intelligence; downloadable and recorded software for use in large language models and artificial intelligence machine-based systems that generate outputs such as predictions or content based on inferencing; computer hardware and software to enable the programming or training of a device; downloadable and recorded software to interpret data using automated processing designed to approximate cognitive abilities, make predictions or inferences; machine-based cognitive architectures and neural networks; artificial neural networks; software and hardware for creating and generating images from text of speech

50.

ANALOG-TO-DIGITAL CONVERTER SYSTEM, RECEIVER, BASE STATION, MOBILE DEVICE AND METHOD FOR ANALOG-TO-DIGITAL CONVERSION

      
Application Number 18553212
Status Pending
Filing Date 2021-06-25
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Camponeschi, Matteo
  • Molina, Albert
  • Rajamani, Kannan
  • Clara, Martin

Abstract

An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

IPC Classes  ?

  • H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
  • H03M 1/10 - Calibration or testing
  • H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging

51.

ENHANCED SERVICE FUNCTION CHAINING IN NEXT GENERATION CELLULAR NETWORKS

      
Application Number 18553240
Status Pending
Filing Date 2022-05-03
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Zongrui
  • Li, Qian
  • Liao, Ching-Yu
  • Stojanovski, Alexandre Saso
  • Palat, Sudeep
  • Luetzenkirchen, Thomas
  • Kolekar, Abhijeet
  • Bangolae, Sangeetha
  • Heo, Youn Hyoung
  • Tong, Xiaopeng

Abstract

This disclosure describes systems, methods, and devices related to service function chaining in wireless networks. A communications system may include a communication control function to select one or multiple communication service functions associated with establishing service function chaining (SFC) services for telecommunications; a service orchestration and chaining function (SOCF) to establish the SFC services; and a service orchestration exposure function (SOEF) to expose the SFC services to an application function (AF) of the system.

IPC Classes  ?

  • H04L 45/0377 - Routes obligatorily traversing service-related nodes for service chaining
  • H04L 45/50 - Routing or path finding of packets in data switching networks using label swapping, e.g. multi-protocol label switch [MPLS]

52.

CROSS-CARRIER SCHEDULING WITH DIFFERENT CELL NUMEROLOGIES

      
Application Number 18283066
Status Pending
Filing Date 2022-07-05
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Li, Yingyang
  • Wang, Yi
  • Xiong, Gang
  • Lee, Daewon
  • Chatterjee, Debdeep

Abstract

A computer-readable storage medium stores instructions to configure a UE for cross-carrier scheduling of data transmissions in a 5G NR and beyond wireless network, and to cause the UE to perform operations including decoding configuration signaling received from a base station. The configuration signaling indicates a first numerology parameter for a scheduling cell of the base station and a second numerology parameter for a scheduled cell of the base station. DCI is received via a PDCCH of the scheduling cell. The DCI schedules a DL data transmission in the scheduled cell of the base station. The DL data transmission is received via a PDSCH of the scheduled cell when a difference between the first numerology parameter and the second numerology parameter is smaller than or equal to a pre-configured numerology threshold value. The UE refrains from decoding the DL data transmission when the difference is greater than the threshold value.

IPC Classes  ?

  • H04W 72/1273 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of downlink data flows
  • H04L 1/1812 - Hybrid protocols; Hybrid automatic repeat request [HARQ]
  • H04L 27/26 - Systems using multi-frequency codes
  • H04W 72/0457 - Variable allocation of band or rate
  • H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling

53.

SINGLE TRP AND MULTIPLE TRP DYNAMIC SWITCHING FOR SINGLE DCI BASED PUSCH TRANSMISSIONS

      
Application Number 18549805
Status Pending
Filing Date 2022-05-03
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Davydov, Alexei
  • Mondal, Bishwarup
  • Han, Dong

Abstract

Various embodiments herein relate to a technique to be performed by a user equipment (UE) in a cellular network. The technique may include identifying, in a downlink control information (DCI) received from a first transmission and reception point (TRP), an indication of whether the UE is to operate in accordance with a single-TRP physical uplink shared channel (PUSCH) mode or a multi-TRP PUSCH mode: identifying, based on the indication, one or more resources for PUSCH transmission; and transmitting, based on the indication and the one or more resources, a first repetition of the PUSCH transmission and a second repetition of the PUSCH transmission. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04W 72/044 - Wireless resource allocation based on the type of the allocated resource
  • H04W 72/1273 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of downlink data flows

54.

OUT-OF-ORDER HANDLING FOR TBOMS SCHEDULING IN 5G NR

      
Application Number 18287707
Status Pending
Filing Date 2022-11-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Xiong, Gang
  • Li, Yingyang
  • Wang, Yi

Abstract

A UE configured for operation in a 5GNR system may decode a first DCI scheduling a first PUSCH transmission with transport-block processing over multiple slots (TBoMS) and a second DCI scheduling a second PUSCH transmission with TBoMS. The UE may check timing relations of the scheduled first and second PUSCH transmissions with TBoMS for validity. When the timing relations are valid, the UE may transmit the first PUSCH transmission in multiple slots in accordance with the first DCI and may transmit the second PUSCH transmission in multiple slots in accordance with the second DCI. The first DCI may be received in a first PDCCH and the second DCI may be received in a second PDCCH. When the first PDCCH ends at a first symbol and the UE is scheduled to start the first PUSCH transmission with TBoMS at a second symbol, the second PUSCH transmission with TBoMS is not expected to be scheduled to start earlier than an end of the first PUSCH transmission with TBoMS when the second PDCCH that scheduled the second PUSCH transmission with TBoMS ends at a symbol later than the first symbol.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 1/1822 - Automatic repetition systems, e.g. Van Duuren systems involving configuration of automatic repeat request [ARQ] with parallel processes
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling

55.

METHODS AND APPARATUS FOR POWER HEADROOM REPORTING FOR MULTIPLE TRANSMISSION RECEPTION POINT (MULTI-TRP) TRANSMISSIONS

      
Application Number 18553322
Status Pending
Filing Date 2022-05-11
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Han, Dong
  • Mondal, Bishwarup
  • Heo, Youn Hyoung
  • Wang, Guotong
  • Zhang, Yujian
  • Davydov, Alexei
  • Han, Seunghee

Abstract

The disclosure is directed to systems and methods systems and methods for a user equipment and a power headroom report including detecting a triggering of a plurality of pathloss references from a plurality of transmission reception points (TRPs) between activation of successive power headroom reporting instances: tracking a power headroom concurrently for the plurality of TRPs during multiple transmission reception point (mTRP) operation to enable power headroom reporting for each respective TRP: tracking power headroom concurrently for each TRP of the plurality of TRPs in use during mTRP operation upon detection of the triggering of the plurality of pathloss references: and providing a power headroom determination and a power headroom report to each of the plurality of TRPs in use during mTRP operation based on the triggered plurality of pathloss references.

IPC Classes  ?

  • H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
  • H04W 52/08 - Closed loop power control
  • H04W 52/24 - TPC being performed according to specific parameters using SIR [Signal to Interference Ratio] or other wireless path parameters
  • H04W 52/42 - TPC being performed in particular situations in systems with time, space, frequency or polarisation diversity

56.

A memory device, a memory module, a computing system, a method for erasing a memory portion of a memory device and a method for generating an erase request

      
Application Number 18547910
Status Pending
Filing Date 2021-03-26
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Liu, Shuo
  • Dong, Yao Zu
  • Huang, Qing
  • Li, Kevin Yufu
  • Yao, Yipeng
  • Yu, Jie

Abstract

A memory device comprises an input interface configured to receive an erase request indicating a memory portion to be erased and control circuitry configured to trigger erasing information stored by memory cells of at least a part of the indicated memory portion of the memory device by writing a predefined pattern into the memory cells during an automatic refresh cycle.

IPC Classes  ?

  • G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
  • G11C 11/408 - Address circuits
  • G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches

57.

OPTICAL FIBER POSITIONING APPARATUS

      
Application Number 18553361
Status Pending
Filing Date 2022-06-28
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Laming, Richard
  • Psaila, Nicholas D.

Abstract

An apparatus for positioning one or more optical fibers relative to the apparatus, comprises a body comprising material, and one or more fiber alignment structures defined in the material of the body, wherein each fiber alignment structure is configured to accommodate a corresponding optical fiber, and wherein each fiber alignment structure is configured to induce one or more bends along the corresponding optical fiber. When an optical fiber is located in such a fiber alignment structure, the optical fiber may be forced into contact with the fiber alignment structure in one or more known regions so that the corresponding optical fiber is located at a more predictable position relative to the corresponding fiber alignment structure in the one or more known regions than is the case for known fiber alignment structures. The location of the corresponding optical fiber at a more predictable position may improve the optical coupling efficiency achievable between the optical fiber and an optical component and/or a photonic chip.

IPC Classes  ?

  • G02B 6/42 - Coupling light guides with opto-electronic elements

58.

METHODS AND APPARATUS TO PERFORM MIXED RADIX FAST FOURIER TRANSFORM (FFT) CALCULATIONS ON GRAPHICS PROCESSING UNITS (GPUs)

      
Application Number 18553185
Status Pending
Filing Date 2021-06-24
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Wang, Bin
  • Peng, Bo
  • Wang, Xiaoyun

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed for mixed radix fast Fourier transform (FFT) calculations of graphics processing units (GPUs). An example apparatus disclosed herein includes at least one memory, machine readable instructions in the apparatus, and at least one processor circuitry to execute the machine readable instructions to at least factorize input data to identify one or more radix-r blocks for the parallel mixed radix calculation, perform at least one of a decimal-to-base or a base-to-base conversion of the input data prior to a bit reverse routine, the bit reverse routine to yield an output data set, cause a lookup table to be loaded into a memory structure based on a lookup table length, the lookup table populated with the output data set, and perform the parallel mixed radix calculation of the one or more radix-r blocks using the lookup table loaded into the memory structure.

IPC Classes  ?

  • G06F 7/49 - Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix

59.

ACCELERATING PARA-VIRTUALIZATION OF A NETWORK INTERFACE USING DIRECT MEMORY ACCESS (DMA) REMAPPING

      
Application Number 18388505
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Zhou, Yigang
  • Liang, Cunming

Abstract

An example electronic apparatus is for accelerating a para-virtualization network interface. The electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. The guest includes a plurality of virtual machines. The host includes a plurality of virtual function devices. The virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. The communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. The electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. The electronic apparatus further includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping.

IPC Classes  ?

  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 13/24 - Handling requests for interconnection or transfer for access to input/output bus using interrupt
  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal

60.

METHODS AND APPARATUS TO MANAGE TELEMETRY DATA IN COMPUTING SYSTEMS

      
Application Number 18399569
Status Pending
Filing Date 2023-12-28
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Bhandaru, Malini K.
  • Smith, Ned M.
  • Cheruvu, Sunil K.
  • Tarkhanyan, Anahit
  • Agerstam, Mats

Abstract

Systems, apparatus, articles of manufacture, and methods are disclosed to monitor telemetry data in computing system. An example apparatus includes interface circuitry to obtain telemetry data; computer readable instructions; and programmable circuitry to instantiate: aggregation circuitry to analyze the telemetry data using an artificial intelligence model to detect an event; and action controller circuitry to: determine a telemetry collection resolution associated with the event; and instruct a telemetry collection operation associated with the telemetry data to adjust collection of the telemetry data according to the determined telemetry collection resolution.

IPC Classes  ?

  • H04L 41/147 - Network analysis or design for predicting network behaviour
  • H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

61.

NETWORK FOR STRUCTURE-BASED TEXT-TO-IMAGE GENERATION

      
Application Number 18400561
Status Pending
Filing Date 2023-12-29
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Xiong, Peixi
  • Jain, Nilesh

Abstract

Technology as described herein provides for generating an image via a generator network, including extracting structural relationship information from a text prompt, wherein the structural relationship information includes sentence features and token features, generating encoded text features based on the sentence features and on relation-related tokens, wherein the relation-related tokens are identified based on parsing text dependency information in the token features, and generating an output image based on combining, via self attention and cross-attention layers, the encoded text features and encoded image features from an input image canvas. Embodiments further include applying a gating function to modify image features based on text features. The self attention and cross-attention layers can be applied via a cross-modality network, the gating function can be applied via a residual gating network, and the relation-related tokens can be further identified via an attention matrix.

IPC Classes  ?

62.

IMPORTANCE-AWARE MODEL PRUNING AND RE-TRAINING FOR EFFICIENT CONVOLUTIONAL NEURAL NETWORKS

      
Application Number 18411542
Status Pending
Filing Date 2024-01-12
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Yao, Anbang
  • Guo, Yiwen
  • Chen, Yurong

Abstract

Systems, apparatuses and methods may provide for conducting an importance measurement of a plurality of parameters in a trained neural network and setting a subset of the plurality of parameters to zero based on the importance measurement. Additionally, the pruned neural network may be re-trained. In one example, conducting the importance measurement includes comparing two or more parameter values that contain covariance matrix information.

IPC Classes  ?

  • G06N 3/082 - Learning methods modifying the architecture, e.g. adding, deleting or silencing nodes or connections
  • G06F 18/241 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

63.

TMD INVERTED NANOWIRE INTEGRATION

      
Application Number 18414290
Status Pending
Filing Date 2024-01-16
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • O'Brien, Kevin P.
  • Naylor, Carl
  • Dorow, Chelsey
  • Maxey, Kirby
  • Gosavi, Tanay
  • Penumatcha, Ashish Verma
  • Shivaraman, Shriram
  • Lin, Chia-Ching
  • Lee, Sudarat
  • Avci, Uygar E.

Abstract

Embodiments disclosed herein comprise semiconductor devices with two dimensional (2D) semiconductor channels and methods of forming such devices. In an embodiment, the semiconductor device comprises a source contact and a drain contact. In an embodiment, a 2D semiconductor channel is between the source contact and the drain contact. In an embodiment, the 2D semiconductor channel is a shell.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

64.

PACKAGE WITH UNDERFILL CONTAINMENT BARRIER

      
Application Number 18415268
Status Pending
Filing Date 2024-01-17
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Jain, Rahul
  • Lee, Kyu Oh
  • Alur, Siddharth K.
  • Jen, Wei-Lun K.
  • Mehta, Vipul V.
  • Dhall, Ashish
  • Chavali, Sri Chaitra J.
  • Manepalli, Rahul N.
  • Alur, Amruthavalli P.
  • Vadlamani, Sai

Abstract

An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

65.

METHODS AND APPARATUS TO FACILITATE COLLABORATIVE LEARNING IN A MULTI-SENSOR ENVIRONMENT

      
Application Number 18415588
Status Pending
Filing Date 2024-01-17
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Mudgal, Priyanka
  • Mcmillan, Caleb Mark
  • Wouhaybi, Rita Hanna
  • Yarvis, Mark David
  • Williams, Jennifer
  • Pisharody, Greeshma

Abstract

Methods, apparatus, systems, and articles of manufacture to facilitate collaborative learning in a multi-sensor environment are disclosed. An example computer readable medium comprises instructions at least one programmable circuit to after determining that first data from a first device conflicts with second data from a second device: validate the first device based on third data from a validated device; and mitigate the second device based on the third data.

IPC Classes  ?

66.

DYNAMIC MEMORY RECONFIGURATION

      
Application Number 18432859
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Ray, Joydeep
  • Cooray, Niranjan
  • Maiyuran, Subramaniam
  • Koker, Altug
  • Surti, Prasoonkumar
  • George, Varghese
  • Andrei, Valentin
  • Appu, Abhishek
  • Garcia, Guadalupe
  • K, Pattabhiraman
  • Kim, Sungye
  • Kumar, Sanjay
  • Marolia, Pratik
  • Ould-Ahmed-Vall, Elmoustapha
  • Ranganathan, Vasanth
  • Sadler, William
  • Striramassarma, Lakshminarayanan

Abstract

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

IPC Classes  ?

  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
  • G06F 7/58 - Random or pseudo-random number generators
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
  • G06F 12/0871 - Allocation or management of cache space
  • G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
  • G06F 12/0882 - Page mode
  • G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 12/0893 - Caches characterised by their organisation or structure
  • G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
  • G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
  • G06F 12/1009 - Address translation using page tables, e.g. page table structures
  • G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
  • G06F 17/16 - Matrix or vector computation
  • G06F 17/18 - Complex mathematical operations for evaluating statistical data
  • G06N 3/08 - Learning methods
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management
  • G06T 15/06 - Ray-tracing
  • H03M 7/46 - Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind

67.

DUAL METAL GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

      
Application Number 18439225
Status Pending
Filing Date 2024-02-12
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Leib, Jeffrey S.
  • Hu, Jenny
  • Dasgupta, Anindya
  • Hattendorf, Michael L.
  • Auth, Christopher P.

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/8234 - MIS technology
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 10/00 - Static random access memory [SRAM] devices

68.

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING EMBEDDED GESNB SOURCE OR DRAIN STRUCTURES

      
Application Number 18440526
Status Pending
Filing Date 2024-02-13
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Bomberger, Cory
  • Murthy, Anand
  • Ghose, Susmita
  • Chouksey, Siddharth

Abstract

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.

IPC Classes  ?

  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/167 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form further characterised by the doping material
  • H01L 29/32 - Semiconductor bodies having polished or roughened surface the imperfections being within the semiconductor body
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

69.

OPTICAL MODE CONVERTOR

      
Application Number 18496672
Status Pending
Filing Date 2023-10-27
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Frish, Harel
  • Seddighian, Pegah
  • Magruder, Kelly
  • Dosunmu, Olufemi

Abstract

Embodiments relate to an apparatus that includes: an input stage with an input Si slab height, an input Si waveguide height, and an input height difference between the input Si slab height and the input Si waveguide height; an output stage with an output Si slab height that is different from the input Si slab height, an output Si waveguide height that is different from the input Si waveguide height, and an output height difference between the output Si slab height and the output Si waveguide height that is different from the input height difference; and a transition stage positioned between the input stage and the output stage, wherein the transition stage has a transition Si slab height, a transition Si waveguide height, and a transition height difference between the transition Si slab height and the transition Si waveguide height. Other embodiments may be described and/or claimed.

IPC Classes  ?

70.

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERATIONS FOR MACHINE LEARNING

      
Application Number 18528340
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Kaul, Himanshu
  • Anders, Mark A.
  • Mathew, Sanu K.
  • Yao, Anbang
  • Ray, Joydeep
  • Tang, Ping T.
  • Strickland, Michael S.
  • Chen, Xiaoming
  • Shpeisman, Tatiana
  • Appu, Abhishek R.
  • Koker, Altug
  • Sinha, Kamal
  • Vembu, Balaji
  • Galoppo Von Borries, Nicolas C.
  • Nurvitadhi, Eriko
  • Barik, Rajkishore
  • Lin, Tsung-Han
  • Ranganathan, Vasanth
  • Jahagirdar, Sanjeev

Abstract

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 17/16 - Matrix or vector computation
  • G06N 3/044 - Recurrent networks, e.g. Hopfield networks
  • G06N 3/045 - Combinations of networks
  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N 3/08 - Learning methods
  • G06N 20/00 - Machine learning
  • G06T 15/00 - 3D [Three Dimensional] image rendering
  • G09G 5/393 - Arrangements for updating the contents of the bit-mapped memory

71.

STRUCTURE AND PROCESS FOR WARPAGE REDUCTION

      
Application Number 18060574
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Yeon, Hong Seung
  • He, Liang
  • Bryks, Whitney
  • Han, Jung Kyu
  • Duan, Gang

Abstract

The present disclosure is directed to a semiconductor carrier platform having a support panel with a top surface and a bottom surface, with the top surface providing a working surface for assembling IC packages using panel-level packaging technology. In an aspect, a backside molding layer may be positioned on the bottom surface of the support panel to prevent or correct any panel warpage. In another aspect, a removable film may be positioned between the bottom surface of the support panel and the backside molding layer to allow the support panel to be readily cleaned and reused.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

72.

TOOL ANOMALY IDENTIFICATION DEVICE AND METHOD FOR IDENTIFYING TOOL ANOMALIES

      
Application Number 18060576
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Rahman, Mohammad Mamunur
  • Tickoo, Omesh
  • Ahuja, Nilesh
  • Genc, Ergin U
  • Troiano, Julianne
  • Ndiour, Ibrahima

Abstract

A method for identifying a tool anomaly of an printed circuit board (PCB) manufacturing process comprising a plurality of phases, the method comprising the steps of: obtaining image data of at least one tool of the PCB manufacturing process; inputting the image data to a machine learning module, the machine learning module configured to perform the following steps: extracting, from the image data, a tool feature image data of the at least one tool; classifying the image data into a phase of the plurality of phases; and determining, based on the classified image data and the tool feature image data, an anomaly state of the at least one tool.

IPC Classes  ?

  • G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)

73.

IN-SITU UV CURE PLACEMENT TOOL FOR ROOM TEMPERATURE CHIP/GLASS DEVICE ATTACHMENT

      
Application Number 18060577
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Liu, Minglu
  • Kanaoka, Yosuke
  • Han, Jung Kyu
  • Duan, Gang
  • Lin, Ziyin

Abstract

The present disclosure relates to a system. The system may include a stage configured to support a substrate. The system may also include a bondhead configured to press a device against the substrate. The system may further include a light source configured to emit UV light towards the stage.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • B32B 37/12 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives

74.

DRY METHOD FOR METAL-DEFINED PAD FORMATION

      
Application Number 18060578
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Ndukum, Tchefor
  • Turan, Deniz
  • Li, Yonggang

Abstract

The present disclosure generally relates to a method. The method may include providing a substrate and forming a seed layer on the substrate. The method may further include forming a first metal layer on selected portions of the seed layer to form exposed portions of the seed layer. The method may also include scanning a laser beam across the substrate to remove the exposed portions of the seed layer to form exposed portions of the substrate.

IPC Classes  ?

  • B23K 26/40 - Removing material taking account of the properties of the material involved
  • B23K 26/0622 - Shaping the laser beam, e.g. by masks or multi-focusing by direct control of the laser beam by shaping pulses
  • B23K 26/082 - Scanning systems, i.e. devices involving movement of the laser beam relative to the laser head

75.

SUBSTRATE ARCHITECTURE FOR ENHANCED ELECTROSTATIC CHUCKING

      
Application Number 18060592
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Candadai, Aaditya Anand
  • Haehn, Nicholas
  • Wang, Ao
  • Bryks, Whitney
  • Pietambaram, Srinivas

Abstract

The present disclosure is directed to a semiconductor panel providing a laminated structure and a plurality of electrically isolated structures distributed throughout the laminated structure to increase an attraction between the laminated structure and an electrostatic chuck. In an aspect, the electrically isolated structures are positioned in spaces in the semiconductor panel without electrically active devices and interconnects. In yet another aspect, the present method provides a semiconductor panel and forming a plurality of electrically isolated structures in selected positions on the semiconductor panel and an electrostatic chuck configured to carry an electrostatic charge for producing an electrostatic force at its top surface, placing the semiconductor panel on the electrostatic chuck, and activating the electrostatic chuck to induce polarization at the top surface to produce an attractive force having a greater magnitude at the positions with the plurality of electrically isolated structures.

IPC Classes  ?

  • H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings

76.

THERMOCOMPRESSION BONDING TOOL FOR PANEL-LEVEL THERMO-COMPRESSION BONDING

      
Application Number 18060596
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Liu, Minglu
  • Gunawan, Andrey
  • Duan, Gang
  • Cetegen, Edvin
  • Wang, Yuting
  • Kaya, Mine
  • Srinivasan, Kartik
  • Oka, Mihir
  • Tripathi, Anurag

Abstract

The present disclosure is directed to an apparatus having a bond head configured to heat and compress a semiconductor package assembly, and a bonding stage configured to hold the semiconductor package assembly, wherein the bonding stage comprises a ceramic material including silicon and either magnesium or indium.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

77.

METHOD FOR PANEL-LEVEL THERMO-COMPRESSION BONDING

      
Application Number 18060617
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Liu, Minglu
  • Gunawan, Andrey
  • Duan, Gang

Abstract

The present disclosure is directed to a thermocompression bonding tool having a bond head with a surface for compression and heating and a sensor, a stage for compression and heating, and a controller, and a method for its use for chip gap height and alignment control. For chip gap height and alignment control, the controller is provided with a recipe displacement and temperature profile and measured offsets.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices

78.

POLYMERIC FILMS AS AN ADHESIVE PROMOTION/BUFFER LAYER AT GLASS-DIELECTRIC OR METAL-DIELECTRIC INTERFACES

      
Application Number 18061126
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Mohammadighaleni, Mahdi
  • Bryks, Whitney M.
  • Kaviani, Shayan
  • Stacey, Joshua J.
  • Heaton, Thomas S.

Abstract

In one embodiment, an integrated circuit apparatus (e.g., package substrate) includes a polymeric layer between a metal and a dielectric or between a metal and a glass. The polymeric layer may be conformally deposited using a vacuum-based vapor deposition technique, e.g., initiated chemical vapor deposition (iCVD).

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C23C 16/02 - Pretreatment of the material to be coated

79.

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

      
Application Number 18061181
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Chen, Haobo
  • Shan, Bohan
  • Arrington, Kyle J.
  • Darmawikarta, Kristof
  • Duan, Gang
  • Ecton, Jeremy D.
  • Feng, Hongxia
  • Guo, Xiaoying
  • Lin, Ziyin
  • Marin, Brandon Christian
  • Pietambaram, Srinivas V.
  • Xu, Dingying

Abstract

In one embodiment, an integrated circuit package substrate includes a core layer comprising a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer, the build-up layer comprising metal vias within a dielectric material and electrically connected to the metal vias of the core layer. The dielectric material includes Silicon, Oxygen, and at least one of Boron or Phosphorus.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/64 - Impedance arrangements
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H05K 1/02 - Printed circuits - Details
  • H05K 1/03 - Use of materials for the substrate
  • H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 3/46 - Manufacturing multi-layer circuits

80.

Microelectronic Assembly Including Interconnect Bridges with Through Vias Embedded Therein

      
Application Number 18061188
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Ecton, Jeremy D.
  • Marin, Brandon Christian
  • Pietambaram, Srinivas V.
  • Ibrahim, Tarek A.
  • Nad, Suddhasattwa
  • Duan, Gang
  • Chen, Haobo
  • Tanaka, Hiroki

Abstract

A microelectronic assembly includes a substrate comprising: a panel including glass and defining an opening therein; an interconnect bridge (IB) in the opening and including interconnect pathways and IB through vias (IBTVs); and electrically conductive structures at a lower surface of the substrate to electrically couple the substrate to another component, at least some of the electrically conductive structures coupled to the IBTVs to form respective vertical electrical connections between the lower surface of the substrate and an upper surface of the substrate; and an electronic component (EC) layer on the upper surface of the substrate, the EC layer including a first active EC (AEC) and a second AEC electrically coupled to one another through the interconnect pathways, at least one of the first AEC or the second AECs further electrically coupled to one or more of the at least some of the electrically conductive structures.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

81.

INTEGRATED CIRCUIT PACKAGE ARCHITECTURES WITH CORE AND/OR BUILD-UP LAYERS COMPRISING SPIN-ON GLASS (SOG)

      
Application Number 18061283
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Bryks, Whitney M.
  • Mohammadighaleni, Mahdi
  • Stacey, Joshua J.

Abstract

In one embodiment, an integrated circuit package substrate includes a core layer comprising Silicon and Oxygen and a plurality of metal vias electrically coupling a first side of the core layer and a second side of the core layer opposite the first side. The package substrate further includes a build-up layer on the first side of the core layer. The build-up layer includes metal pads and metal traces within a dielectric material that are electrically connected to the metal vias of the core layer, the dielectric material comprising Silicon, Oxygen, and at least one of Boron or Phosphorus.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

82.

INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS

      
Application Number 18073213
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Lilak, Aaron D.
  • Phan, Anh
  • Mehandru, Rishabh
  • Cea, Stephen M.
  • Morrow, Patrick
  • Kavalieros, Jack T.
  • Weber, Justin
  • Berrada, Salim

Abstract

Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.

IPC Classes  ?

  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

83.

GATE-ALL-AROUND DEVICES WITH DIFFERENT GATE OXIDE THICKNESSES

      
Application Number 18074814
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Jun, Hwichan
  • Bouche, Guillaume

Abstract

Techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. A first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. The first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. The first gate oxide layer is thicker than the second gate oxide layer. A high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer.

IPC Classes  ?

  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

84.

SYMMETRIC DUMMY BRIDGE DESIGN FOR FLI ALIGNMENT IMPROVEMENT

      
Application Number 18075360
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Liu, Minglu
  • Wu, Yang
  • Wang, Yuting
  • Ross, Lawrence
  • Kaya, Mine
  • Duan, Gang
  • Cetegen, Edvin
  • Aguinaga, Alexander

Abstract

Embodiments disclosed herein include package architectures. In an embodiment, the package architecture comprises a package substrate, a first bridge in the package substrate, where the first bridge includes conductive routing, and a second bridge in the package substrate. In an embodiment, the package architecture further comprises a third bridge in the package substrate, where the second bridge and the third bridge are positioned symmetrically about the first bridge.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

85.

LINED CONDUCTIVE STRUCTURES FOR TRENCH CONTACT

      
Application Number 18076130
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Ganesan, Krishna
  • Alazizi, Ala
  • Lakhani, Ankit Kirit
  • Sun, Peter P.
  • Paredes, Diana Ivonne

Abstract

Lined conductive via structures for trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures over corresponding ones of a plurality of vertical stacks of horizontal nanowires. The integrated circuit structure also includes a plurality of conductive trench contact structures alternating with the plurality of gate structures, each of the plurality of conductive contact structures having an upper portion over a lower portion, the upper portion of each of the plurality of conductive trench contact structures having a length between ends. The integrated circuit structure also includes a dielectric liner in lateral contact with sides along the length of the upper portion of each of the plurality of conductive contact structures, wherein the dielectric liner is not in contact with the ends of the upper portion of each of the plurality of conductive contact structures.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/786 - Thin-film transistors

86.

DYNAMIC VOLTAGE REGULATOR SENSING FOR CHIPLET-BASED DESIGNS

      
Application Number 18076352
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Thigle, Vikrant
  • Mathiyalagan, Vijay Anand
  • Haridass, Anand
  • Chandrasekhar, Arun
  • Pasdast, Gerald

Abstract

Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.

IPC Classes  ?

  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc

87.

SYSTEM, METHOD AND APPARATUS FOR FILTERING CONFIGURATION ACCESSES TO UNIMPLEMENTED DEVICES

      
Application Number CN2022135770
Publication Number 2024/113295
Status In Force
Filing Date 2022-12-01
Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Xu, Tao
  • Guo, Changpeng

Abstract

In one embodiment, an apparatus includes a filter to receive a first configuration read access request and direct the first configuration read access request to a first root port, and receive a second configuration read access request and prevent the second configuration read access request from being sent to a second root port, where a destination of the first configuration read access request is an implemented device of a system and a destination of the second configuration read access request is an unimplemented device of the system. The apparatus also includes a storage to store an identification of implemented devices and unimplemented devices. Other embodiments are described and claimed.

IPC Classes  ?

  • G06F 13/20 - Handling requests for interconnection or transfer for access to input/output bus

88.

Apparatuses, Methods, Computer Systems and Computer-Readable Media For Generating and Using Random Values

      
Application Number 18391788
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Horovitz, Dan
  • Horn, Alon
  • Blum Shem-Tov, Ilil
  • Hasarfaty, Shai
  • Novick, David

Abstract

Various examples of the present disclosure relate to apparatuses, methods, computer systems and computer-readable media for generating and using random values. Some aspects of the present disclosure relate to an apparatus for a computer system, the apparatus comprising memory circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to determine different canary values for corresponding different threads of a program, and start the thread of the program, with the determined canary value being used as stack canary for the thread of the program.

IPC Classes  ?

  • G06F 7/58 - Random or pseudo-random number generators

89.

Concept for Erasing User Data

      
Application Number 18391707
Status Pending
Filing Date 2023-12-21
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Mountain, Highland Mary
  • Llorens, Hector
  • Binder, Garritt

Abstract

Some aspects of the present disclosure relate to an apparatus for a computer system, the apparatus comprising processor circuitry to provide, via an interface of a firmware of the computer system, an option to erase user data of the computer system, and erase, after the option has been triggered, the user data of the computer system, wherein erasing the user data of the computer system comprises erasing user data managed by a non-operating system component of the computer system and erasing user data managed by an operating system of the computer system.

IPC Classes  ?

  • G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules

90.

TIME DOMAIN RESTRICTION FOR CHANNEL STATE INFORMATION REFERENCE SIGNAL CONFIGURATION

      
Application Number 18553279
Status Pending
Filing Date 2022-05-10
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Hua
  • Zhang, Meng
  • Chervyakov, Andrey
  • Huang, Rui

Abstract

This disclosure describes systems, methods, and devices related to channel state information reference signal (CSI-RS) configuration. A device may establish a first measurement window for a first CSI-RS associated with a first type of measurement in a measurement object (MO). The device may identify a measurement gap associated a second type of measurement. The device may perform adjustment to avoid a collision between the first measurement window and the measurement gap. The device may detect the first CSI-RS within the first measurement window.

IPC Classes  ?

  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 24/10 - Scheduling measurement reports

91.

SYSTEMS, DEVICES, AND METHODS FOR ADAPTING TRAFFIC TO PRIORITIZED VEHICLE ROUTES

      
Application Number 18556367
Status Pending
Filing Date 2021-09-24
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Jha, Satish
  • Sivanesan, Kathiravetpillai
  • Alam, S M Iftekharul
  • Chen, Kuilin Clark
  • Doshi, Kshitij
  • Gomes Baltar, Leonardo
  • Guim Bernat, Francesc
  • Merwaday, Arvind
  • Mueck, Markus Dominik
  • Sehra, Suman A.
  • Sharma Banjade, Vesh Raj
  • Tan, Soo Jin

Abstract

The disclosure relates to systems, methods, and devices for managing traffic through a road segment and/or intersection. The traffic management system may place traffic objects in a collaboration group for coordinating movements in the road segment and/or intersection in response to a received indication that an emergency vehicle has a planned route that includes the road segment and/or intersection. The traffic management system may determine a movement plan for each traffic object in the collaboration group based on received measurements about the road segment and the planned route of the emergency vehicle. The traffic management system may control a transmitter to send the movement plan to each traffic object in the collaboration group.

IPC Classes  ?

  • G08G 1/087 - Override of traffic control, e.g. by signal transmitted by an emergency vehicle
  • G01C 21/34 - Route searching; Route guidance
  • G08G 1/00 - Traffic control systems for road vehicles
  • G08G 1/09 - Arrangements for giving variable traffic instructions

92.

Firmware Apparatus, Device, Method and Computer Program

      
Application Number 18570132
Status Pending
Filing Date 2021-12-09
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Jayakumar, Sarathy
  • You, Zijian
  • Gopalakrishnan, Karthik
  • Kaneda, Erik
  • Williams, Dan

Abstract

Various examples relate to a firmware apparatus (10), firmware device, firmware method, and computer program for a computer system (100) comprising processing circuitry (105), and to a corresponding computer system (100). The firmware apparatus (10) comprises an interface (12) for accessing functionality of the firmware apparatus (10) from an operating system of the computer system (100). The firmware apparatus (10) comprises control circuitry (14), configured to identify one or more processing functionalities being supported by the processing circuitry (105) of the computer system (100), provide information on the one or more processing functionalities via the interface (12) to a user mode interface of the operating system of the computer system (100), and provide access to the one or more processing functionalities for application programs being executed in the operation system, the access being based on the information on the one or more processing functionalities provided to the user mode interface.

IPC Classes  ?

  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores

93.

SOUNDING REFERENCE SIGNAL CONFIGURATION FOR ANTENNA SWITCHING AND CARRIER SWITCHING

      
Application Number 18549325
Status Pending
Filing Date 2022-03-15
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Wang, Guotong
  • Davydov, Alexei

Abstract

Systems, apparatuses, methods, and computer-readable media are provided for SRS configuration for antenna switching and/or carrier switching. The described techniques may be used in multi-TRP and/or single TRP communication. Also described are techniques for beam configuration for SRS with antenna switching. For example, embodiments provide techniques for beam configuration/update for SRS antenna switching considering the beam change signaling received during the antenna switching procedure. Other embodiments may be described and claimed.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal

94.

ENHANCED SERVICE CLASSIFICATION FOR SERVICE FUNCTION CHAINING IN NEXT GENERATION CELLULAR NETWORKS

      
Application Number 18553425
Status Pending
Filing Date 2022-05-26
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Zongrui
  • Li, Qian
  • Stojanovski, Alexandre Saso
  • Palat, Sudeep
  • Luetzenkirchen, Thomas
  • Kolekar, Abhijeet
  • Liao, Ching-Yu
  • Bangolae, Sangeetha
  • Heo, Youn Hyoung
  • Tong, Xiaopeng

Abstract

This disclosure describes systems, methods, and devices related to service function chaining classification in wireless networks. A communications network system may include a first cellular network device configured to: receive service data adaptation protocol (SDAP) data from a user equipment (UE) device, the SDAP data comprising a SDAP header; identify a service chaining function (SFC) service identifier of the SDAP header; determine that the SFC service identifier is indicative of a SFC service profile, the SFC service profile indicative of quality of service (QOS) traffic characteristics; identify a SFC traffic flow associated with the SFC service identifier; and transmit the SDAP data to a second cellular network device; and wherein the second cellular network device is configured to: receive the SDAP data from the first cellular network device; and transmit the SDAP data to a service function of the system.

IPC Classes  ?

  • H04L 45/655 - Interaction between route computation entities and forwarding entities, e.g. for route determination or for flow table update
  • H04L 69/22 - Parsing or analysis of headers
  • H04W 40/02 - Communication route or path selection, e.g. power-based or shortest path routing

95.

OPTICAL COUPLER WITH DIFFERENT WAVEGUIDE MATERIALS

      
Application Number 18521734
Status Pending
Filing Date 2023-11-28
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Su, Tiehui
  • Vulovic, Boris M.
  • Qian, Wei
  • Magruder, Kelly
  • Seddighian, Pegah
  • Lin, Wenhua
  • Frish, Harel
  • Gautam, Nutan

Abstract

Embodiments herein relate to a chip comprising: a silicon substrate, a first waveguide that includes silicon and nitrogen, and a second waveguide that includes silicon. A portion of the first waveguide may overlap a portion of the second waveguide. An oxide layer may be coupled with a face of the silicon substrate. A first portion of the oxide layer between the silicon substrate and the first waveguide may have a thickness that is greater than a thickness of a second portion of the oxide layer that is between the second waveguide and the oxide layer. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • G02B 6/125 - Bends, branchings or intersections
  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

96.

ENHANCEMENTS TO TIME-SENSITIVE NETWORKING CONFIGURATION FOR SUPPORTING WIRELESS TSN LINKS

      
Application Number 18553354
Status Pending
Filing Date 2022-05-26
First Publication Date 2024-06-06
Owner INTEL CORPORATION (USA)
Inventor
  • Cavalcanti, Dave
  • Perez-Ramirez, Javier
  • Fang, Juan
  • Sudhakaran, Susruth
  • Eisen, Mark
  • Galeev, Mikhail

Abstract

This disclosure describes systems, methods, and devices related to enhanced time-sensitive networking (TSN) configuration. A device may identify a frame received from a TSN domain comprising wired and wireless TSN traffic. The device may decode the frame to extract one or more fields, wherein the one or more fields comprise bridge parameters. The device may determine based on the bridge parameters whether a port associated with the device is wireless capable.

IPC Classes  ?

  • H04W 72/0446 - Resources in time domain, e.g. slots or frames
  • H04W 28/02 - Traffic management, e.g. flow control or congestion control
  • H04W 72/51 - Allocation or scheduling criteria for wireless resources based on terminal or device properties
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

97.

DEFAULT BEAM OPERATIONS FOR UPLINK TRANSMISSIONS

      
Application Number 18550092
Status Pending
Filing Date 2022-05-10
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Wang, Guotong
  • Davydov, Alexei
  • Mondal, Bishwarup

Abstract

Various embodiments herein may relate to default beam operations for uplink transmissions. In particular, some embodiments are directed to default beam operations for physical uplink shared channel (PUSCH), physical uplink control channel (PUCCH) or sounding reference signal (SRS) transmissions in multi-transmission reception point (TRP) scenarios. Other embodiments may be disclosed or claimed.

IPC Classes  ?

  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04B 7/024 - Co-operative use of antennas at several sites, e.g. in co-ordinated multipoint or co-operative multiple-input multiple-output [MIMO] systems
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/044 - Wireless resource allocation based on the type of the allocated resource

98.

METHOD AND SYSTEM OF AUDIO FALSE KEYPHRASE REJECTION USING SPEAKER RECOGNITION

      
Application Number 18367180
Status Pending
Filing Date 2023-09-12
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Ossowski, Jacek
  • Bocklet, Tobias
  • Lopatka, Kuba

Abstract

Techniques related to a method and system of audio false keyphrase rejection using speaker recognition are described herein. Such techniques use speaker recognition of a computer originated voice to omit actions triggered when a keyphrase is present in captured audio and omitted when speech of the captured audio was spoken by the computer originated voice.

IPC Classes  ?

  • G10L 15/22 - Procedures used during a speech recognition process, e.g. man-machine dialog
  • G10L 15/08 - Speech classification or search
  • G10L 17/00 - Speaker identification or verification

99.

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO SUPPORT LIVE MIGRATION OF PROTECTED CONTAINERS

      
Application Number 18378124
Status Pending
Filing Date 2023-10-09
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Rozas, Carlos V.
  • Vij, Mona
  • Leslie-Hurd, Rebekah M.
  • Zmudzinski, Krystof C.
  • Chakrabarti, Somnath
  • Mckeen, Francis X.
  • Scarlata, Vincent R.
  • Johnson, Simon P.
  • Alexandrovich, Ilya
  • Neiger, Gilbert
  • Shanbhogue, Vedvyas
  • Anati, Ittai

Abstract

A processor includes a decode unit to decode an instruction that is to indicate a page of a protected container memory, and a storage location outside of the protected container memory. An execution unit, in response to the instruction, is to ensure that there are no writable references to the page of the protected container memory while it has a write protected state. The execution unit is to encrypt a copy of the page of the protected container memory. The execution unit is to store the encrypted copy of the page to the storage location outside of the protected container memory, after it has been ensured that there are no writable references. The execution unit is to leave the page of the protected container memory in the write protected state, which is also valid and readable, after the encrypted copy has been stored to the storage location.

IPC Classes  ?

  • G06F 12/14 - Protection against unauthorised use of memory
  • G06F 8/41 - Compilation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
  • G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
  • G06F 21/60 - Protecting data

100.

SPUTTER TARGETS FOR SELF-DOPED SOURCE AND DRAIN CONTACTS

      
Application Number 18399237
Status Pending
Filing Date 2023-12-28
First Publication Date 2024-06-06
Owner Intel Corporation (USA)
Inventor
  • Karpov, Ilya V.
  • Budrevich, Aaron A.
  • Dewey, Gilbert
  • Metz, Matthew V.
  • Kavalieros, Jack T.
  • Lavric, Dan S.

Abstract

An integrated circuit structure includes a source or drain region, and a contact coupled to the source or drain region. Sputter targets that include metals doped with the appropriate dopant types are used to deposit a conductive layer on the source or drain region that is annealed to form a region including metals and semiconductor materials between the source or drain region and the contact. A first dopant is within the source or drain region, and a second dopant is within the region. In one example, the first dopant is elementally different from the second dopant. In another example, the first dopant is elementally the same as the second dopant, wherein a concentration of the first dopant within a section of the source or drain region is within 20% of a concentration of the second dopant within the region.

IPC Classes  ?

  • H01J 37/34 - Gas-filled discharge tubes operating with cathodic sputtering
  • C23C 14/34 - Sputtering
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
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