Disclosed herein are integrated circuit (IC) contact structures, and related devices and methods. For example, in some embodiments, an IC contact structure may include an electrical element, a metal on the electrical element, and a semiconductor material on the metal. The metal may conductively couple the semiconductor material and the electrical element.
Techniques are disclosed for dynamically selecting out of band emission protection mechanisms to protect the usage of other frequency bands, as well as techniques for managing the scheduling and transmission of safety related messages having different communication latency requirements.
For example, a wireless communication device may be configured to determine an expected interference-based value corresponding to an Uplink (UL) transmission from a wireless communication station (STA) in a Trigger-Based (TB) Multi-User (MU) UL transmission to be communicated from a plurality of STAs to the wireless communication device; to determine one or more transmit (Tx) configuration parameters for the STA based on the expected interference-based value corresponding to the UL transmission from the STA; and to transmit a trigger frame to trigger the TB MU UL transmission, the trigger frame including the one or more Tx configuration parameters to configure the UL transmission from the STA.
Disclosed embodiments relate to executing a vector-complex fused multiply-add instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers identifies a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, generate a complex result by using the four products according to the instruction, and store a result to the corresponding position of the identified destination operand.
For example, an Access Point (AP) may be configured to process network slicing information including slice identification information and Service Level Agreement (SLA) information, wherein the slice identification information is to identify one or more Quality of Service (QoS) network slices. For example, the AP may be configured to determine a configuration of one or more radio resource allocations to be assigned to the one or more QoS network slices, and to transmit a network slicing advertisement including network slicing assignment information to indicate an assignment of the one or more radio resource allocations to the one or more QoS network slices.
Various embodiments herein provide techniques for cancelation of one or more uplink (UL) transmissions from a user equipment (UE). The UE may receive an indication of a parameter d to use for determining a start of a reference UL resource (RUR). The parameter d may be UE-specific. The UE may further receive a physical downlink control channel (PDCCH) that includes a downlink control information (DCI) to indicate that a UL transmission is to be canceled in a RUR. The UE may determine a starting symbol of the RUR based on the parameter d. In embodiments, the UE may scale the parameter d based on a first subcarrier spacing (SCS) associated with the parameter d and a second SCS associated with the uplink transmission to obtain a scaled parameter d′ that is used to determine the starting symbol of the RUR. Other embodiments may be described and claimed.
This disclosure describes systems, methods, and devices related to enhanced plate polishing. A device may place a liquid between a plate and a wafer. The device may utilize a controller to vary a current flowing through an array of coils. The device may apply pressure on the plate to press against the liquid and the wafer.
B24B 1/00 - Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
Technologies for cryptographic separation of MMIO operations with an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment. The accelerator determines, based on a target memory address, a first memory address range associated with the memory-mapped I/O transaction, generates a second authentication tag using a first cryptographic key from a set of cryptographic keys, wherein the first key is uniquely associated with the first memory address range. An accelerator validator determines whether the first authentication tag matches the second authentication tag, and a memory mapper commits the memory-mapped I/O transaction in response to a determination that the first authentication tag matches the second authentication tag. Other embodiments are described and claimed.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
9.
METHOD TO IMPLEMENT WAFER-LEVEL CHIP-SCALE PACKAGES WITH GROUNDED CONFORMAL SHIELD
Embodiments disclosed herein include electronic packages with conformal shields and methods of forming such packages. In an embodiment, the electronic package comprises a die having a first surface, a second surface opposite the first surface, and sidewall surfaces. A redistribution layer is over the first surface of the die, and the redistribution layer comprises a first conductive layer. In an embodiment, an under ball metallization (UBM) layer is over the redistribution layer, and a conductive shield is over the sidewall surfaces of the die and the second surface of the die. In an embodiment, the conductive shield is electrically coupled to the UBM layer.
H01L 23/552 - Protection against radiation, e.g. light
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
11.
HARDWARE ACCELERATION OF DATA REDUCTION OPERATIONS
A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
An example apparatus disclosed herein is to receive network data communicated via a first channel associated with the online collaboration session, the network data including received media data packets. The disclosed example apparatus is also to analyze the network data to determine first loopback data, the first loopback data including at least one of a first quality score based on a first analysis of the received media data packets or a second quality score based on a second analysis of media decoded from the received media data packets. The disclosed example apparatus is also to analyze local data obtained by a local client during the online collaboration session to determine second loopback data. The disclosed example apparatus is further to cause transmission of a loopback message to a moderator client via the second channel, the loopback message based on the first loopback data and the second loopback data.
H04L 12/18 - Arrangements for providing special services to substations for broadcast or conference
G06F 3/04817 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
H04L 51/04 - Real-time or near real-time messaging, e.g. instant messaging [IM]
H04L 65/1069 - Session establishment or de-establishment
An apparatus of an access point (AP) includes memory and processing circuitry configured to encode a trigger frame for transmission to a plurality of station devices (STAs) in a wireless network. A first request frame received from a STA of the plurality of STAs is decoded. The first request frame requests the AP to create a protected period for the STA when the STA is in an exposed node situation. A second request frame is encoded for transition to at least a second AP. The second request frame requests the at least second AP to establish a restricted target wake time (rTWT) for the STA. A first response frame from the at least second AP is decoded. The first response frame includes an indication of whether the rTWT is established. A second response frame is encoded for transmission to the STA. The second response frame includes the indication.
Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
Embodiments for orchestrating execution of workloads on a distributed computing infrastructure are disclosed herein. In one example, environment data is received for compute devices in a distributed computing infrastructure. The environment data is indicative of an operating environment of the respective compute devices and a physical environment of the respective locations of the compute devices. Future operating conditions of the compute devices are predicted based on the environment data, and workloads are orchestrated for execution on the distributed computing infrastructure based on the predicted future operating conditions.
The present disclosure is generally related to reconfigurable radio equipment (RREs), and in particular to information models and protocols for the multiradio interface for RREs and radio application packages (RAPs) used for reconfiguring RREs. Various extensions to the information models of the multiradio interface for RREs are provided such that internal state information is included in the information models and protocols of the multiradio interface. Various aspects of RAP container formats and structure are also provided.
H04L 41/0895 - Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
G06F 8/71 - Version control ; Configuration management
H04L 41/0806 - Configuration setting for initial configuration or provisioning, e.g. plug-and-play
H04L 67/60 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources
Apparatus, systems, articles of manufacture, and methods for robot movement are disclosed. An example robot movement apparatus includes a sequence generator to generate a sequence of context variable vectors and policy variable vectors. The context variable vectors are related to a movement target, and the policy variable vectors are related to a movement trajectory. The example apparatus includes a calculator to calculate an upper policy and a loss function based on the sequence. The upper policy is indicative of a robot movement, and the loss function is indicative of a degree to which a movement target is met. The example apparatus also includes a comparator to determine if the loss function satisfies a threshold and an actuator to cause the robot to perform the robot movement of the upper policy when the loss function satisfies the threshold.
Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware description, automatically detecting a case-splitting opportunity within the critical path, generating hardware description language for a case split having determined operator domain restrictions, and outputting a second hardware description including the hardware description language for the case split, wherein the second hardware description has a reduced operator hardware cost for the critical path relative to the first hardware description.
The present disclosure provides techniques for physical uplink shared channel (PUSCH) only based small data transmission, including: configuration of pre-allocated UL resource (PUR) set; association of synchronization signal block (SSB) and PUSCH transmission; scrambling sequence generation of the PUSCH transmission; and a procedure for PUSCH only transmission carrying small data. Other embodiments may be described and claimed.
H04L 1/1867 - Arrangements specially adapted for the transmitter end
H04L 5/00 - Arrangements affording multiple use of the transmission path
H04L 5/10 - Channels characterised by the type of signal the signals being represented by different frequencies with mechanical filters or demodulators
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
Methods, apparatus, systems, and articles of manufacture are disclosed to improve webservers using dynamic load balancers. An example method includes identifying a first and second data object type associated with media and with first and second data objects of the media. The example method also includes enqueuing first and second event data associated with the first and second data object in a first and second queue in first circuitry in a die of programmable circuitry. The example method further includes dequeuing the first and second event data into a third and fourth queue associated with a first and second core of the programmable circuitry, the first circuitry separate from the first core and the second core. The example method additionally includes causing the first and second core to execute a first and second computing operation based on the first and second event data in the third and fourth queues.
H04L 65/612 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio for unicast
H04L 67/02 - Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
H04L 67/60 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
22.
METHOD AND SYSTEM OF VIDEO CODING WITH HANDLING OF ILLEGAL BLOCK PARTITIONS
Methods, systems, and articles are described herein related to video coding. The method comprises receiving compressed image data of video frames including a block of image data of at least one of the frames. The method also comprises receiving first partition data to be used to decode the compressed image data and indicating a partition in the block. This method comprises detecting whether or not the block has an illegal block partition. Also, the method comprises generating second partition data to indicate the illegal block partition of the block is to be ignored. Further, the method includes decoding the block at least according to the second partition data.
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
23.
LASER ABLATION-BASED SURFACE PROPERTY MODIFICATION AND CONTAMINATION REMOVAL
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Example apparatus disclosed herein are to process a first image of a first video segment from the image capture sensor with a machine learning algorithm to determine a first score for the first image, the machine learning algorithm to detect actions associated with images, the actions associated with labels. Disclosed example apparatus are also to determine a second score for the first video segment based on respective first scores for corresponding images in the first video segment. Disclosed example apparatus are further to determine, based on the second score, whether to retain the first video segment in the memory.
G06V 10/40 - Extraction of image or video features
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 20/40 - Scenes; Scene-specific elements in video content
25.
TECHNOLOGIES FOR A FLEXIBLE 3D POWER PLANE IN A CHASSIS
Technologies for a flexible three-dimensional power plane in a chassis are disclosed. In one embodiment, a flexible ribbon cable is laid along a circuit board tray. The flexible ribbon cable is secured to the tray using power bosses. The power bosses connect to one or more conductors on the ribbon cable. When the circuit board is mounted on the circuit board tray, the power bosses extend through holes in the circuit board and mate with power clips on the surface of the circuit board tray. The ribbon cable, power bosses, and power clips can distribute power to various locations on the circuit board, without requiring large traces that take up space on the circuit board.
H05K 7/14 - Mounting supporting structure in casing or on frame or rack
H01R 12/79 - Coupling devices for flexible printed circuits, flat or ribbon cables or like structures connecting to rigid printed circuits or like structures
A system that includes at least one memory device and at least one graphics processing unit (GPU) comprising at least one processor and at least one register accessible to the at least one processor. In some examples, the at least one processor is configured to: retrieve, from the at least one memory device, pixel data of a kernel grid into the at least one register to load pixel data neighboring a target pixel region once into the one or more registers and process the neighboring pixel data based on the retrieved pixel data of the kernel grid from the at least one register.
Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
G06T 5/20 - Image enhancement or restoration by the use of local operators
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
28.
HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS
Techniques for slicing memory of a hardware processor core by linear address are described. In certain examples, a hardware processor core includes memory circuitry having: a cache comprising a plurality of slices of memory, wherein each of a plurality of cache lines of memory are only stored in a single slice, and each slice stores a different range of address values compared to any other slice, wherein each of the plurality of slices of memory comprises: an incomplete load buffer to store a load address from the address generation circuit for a load request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the load address being within a range of address values of that memory slice, a store address buffer to store a store address from the address generation circuit for a store request operation, broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, in response to the store address being within a range of address values of that memory slice, a store data buffer to store data, including the data for the store request operation that is to be stored at the store address, for each store request operation broadcast to the plurality of slices of memory by the memory circuit from the execution circuit, and a store completion buffer to store the data for the store request operation in response to the store address being stored in the store address buffer of that memory slice, and, in response, clear the store address for the store request operation from the store address buffer and clear the data for the store request operation from the store data buffer.
Technologies for performing sensor fusion include a compute device. The compute device includes circuitry configured to obtain detection data indicative of objects detected by each of multiple sensors of a host system. The detection data includes camera detection data indicative of a two or three dimensional image of detected objects and lidar detection data indicative of depths of detected objects. The circuitry is also configured to merge the detection data from the multiple sensors to define final bounding shapes for the objects.
Systems and methods are disclosed for providing non-lexical cues in synthesized speech. An example system includes processor circuitry to generate a breathing cue to enhance speech to be synthesized from text; determine a first insertion point of the breathing cue in the text, wherein the breathing cue is identified by a first tag of a markup language; generate a prosody cue to enhance speech to be synthesized from the text; determine a second insertion point of the prosody cue in the text, wherein the prosody cue is identified by a second tag of the markup language; insert the breathing cue at the first insertion point based on the first tag and the prosody cue at the second insertion point based on the second tag; and trigger a synthesis of the speech from the text, the breathing cue, and the prosody cue.
G06F 40/40 - Processing or translation of natural language
G10L 13/08 - Text analysis or generation of parameters for speech synthesis out of text, e.g. grapheme to phoneme translation, prosody generation or stress or intonation determination
31.
METHODS AND APPARATUS FOR TELEMETRY GRANULARITY MANAGEMENT
An example first device disclosed includes interface circuitry, machine readable instructions, and programmable circuitry to operate based on the machine readable instructions to update configuration data based on a telemetry pattern from a second device, the second device to satisfy a neighbor condition, generate telemetry data based on the configuration data, and update the first set of data based on feedback from a recipient of the telemetry data.
A method and apparatus for detecting data lane mapping between a first circuitry and a second circuitry in a system. The first and second circuitry include a plurality of first and second data lanes, respectively that are mapped each other. The external device and the first circuitry are configured with a specific data pattern. A data transfer test is performed such that the specific data pattern is transferred from the external device to the first circuitry via the second data lanes. The data transfer test is performed iteratively by adjusting timing parameters for the second data lanes in the second circuitry in a pre-configured range while setting a timing parameter for a target second data lane in the second circuitry to an invalid value. Data lane mapping for the target second data lane between the first circuitry and the second circuitry is determined based on the data transfer test result.
An apparatus including a memory and a processor configured to: identify an item located within the environment based on sensor data, wherein the sensor data represents one or more sensor detections of the environment; determine a metric representative of a likelihood of the item becoming lost the within the environment based on information about the item; and select, based on the metric, at least one monitoring method to monitor the item within the environment from a plurality of monitoring methods.
Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
35.
APPARATUS, SYSTEM AND METHOD OF AN ORTHOGONAL FREQUENCY-DIVISION MULTIPLEXING (OFDM) TRANSMISSION OVER A WIDE BANDWIDTH
For example, an apparatus may include a segment parser to parse scrambled data bits of a PPDU into a first plurality of data bits and a second plurality of data bits, the PPDU to be transmitted in an OFDM transmission over an aggregated bandwidth comprising a first channel in a first frequency band and a second channel in a second frequency band; a first baseband processing block to encode and modulate the first plurality of data bits according to a first OFDM MCS for transmission over the first channel in the first frequency band; and a second baseband block to encode and modulate the second plurality of data bits according to a second OFDM MCS for transmission over the second channel in the second frequency band.
Examples described herein relate to a router. In some examples, the router includes an interface and circuitry coupled to the interface. In some examples, the circuitry is to determine whether an incoming packet is to reach a faulty link based on a fault location received in a received negative acknowledgment (NACK) message and based on a determination that the incoming packet is to reach the faulty link, drop the packet one or multiple hops before reaching the faulty link.
Various technologies relating to wireless sensor networks (WSNs) are disclosed, including, but not limited to, device onboarding and authentication, network association and synchronization, data logging and reporting, asset tracking, and automated flight state detection.
Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.
A method of an aspect includes receiving a request for a chained accelerator operation, and configuring a chain of accelerators to perform the chained accelerator operation. This may include configuring a first accelerator to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. This may also include configuring a second accelerator to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.
Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
41.
PIPELINING SERVICES IN NEXT-GENERATION CELLULAR NETWORKS
This disclosure describes systems, methods, and devices related to pipelining services. A device may receive from a service consumer a request for pipeline service with service orchestration chaining function (SOCF), wherein the request comprises pipeline service context information. The device may generate requirements for the pipeline service based on the pipeline service context information. The device may select Computation, Communication, and Data Control Functions (CFs) instances for the pipeline service. The device may send a pipeline policy create request to a policy control function (PCF) when the PCF is responsible for generating policies related to the pipeline service including a pipeline ID. The device may receive a pipeline policy create response from the PCF indicating results of the pipeline ID and policy generation.
A system for video segmentation may include a neural network and a memory including multi-range arrays. The multi-range arrays may store feature map arrays including different number of feature maps. The system may generate a feature map from a frame in a video at a time and store the feature map in the memory. The feature map may be in a feature map array that also includes one or more contextual feature maps generated from other frames in the video. The system uses the feature map array to determine whether the frame falls into a segment of the video. The system may generate a new feature map later from another frame and include the new feature map in a new feature map array that also includes the first feature map. The system uses the new feature map array to determine whether the new frame falls into a segment.
MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.
Systems, apparatus, articles of manufacture, and methods are disclosed for power budgeting for computer peripherals with electronic devices. An example apparatus to budget power in an electronic device includes interface circuitry; machine readable instructions; and programmable circuitry to at least one of instantiate or execute the machine readable instructions to: detect a Type-C event associated with a computer peripheral; write a power level offset based on an assumed power contract for the computer peripheral during debounce time; obtain an actual power contract for the computer peripheral; and adjust the power level offset based on the actual power contract.
Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
47.
SYSTEMS AND METHODS FOR TONE MAPPING OF HIGH DYNAMIC RANGE IMAGES FOR HIGH-QUALITY DEEP LEARNING BASED PROCESSING
Systems and methods for tone mapping of high dynamic range (HDR) images for high-quality deep learning based processing are disclosed. In one embodiment, a graphics processor includes a media pipeline to generate media requests for processing images and an execution unit to receive media requests from the media pipeline. The execution unit is configured to compute an auto-exposure scale for an image to effectively tone map the image, to scale the image with the computed auto-exposure scale, and to apply a tone mapping operator including a log function to the image and scaling the log function to generate a tone mapped image.
Examples described herein relate to a router interface device. In some examples, the router includes an interface and circuitry. In some examples, the circuitry is to: proactively drop a packet and send a negative acknowledgement (NACK) message to a sender based on lack of buffer space for a response associated with the packet and sent from a downstream network interface device that received the packet and also based on one or more of: congestion at a downstream switch or congestion at an endpoint receiver.
Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.
Examples described herein relate to a router. In some examples, the router includes an interface and circuitry coupled to the interface. In some examples, the circuitry is to reserve a memory region in a buffer for a response sent by a receiver of a forwarded packet.
Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.
Systems, apparatus, articles of manufacture, and methods are disclosed to manage workloads for an operating system wherein it causes programmable circuitry to cause a task of a workload to be executed with a first processor core configuration; cause the task to be executed with a second processor core configuration; compare a first performance metric of the execution of the task with the first processor core configuration to a second performance metric of the execution with the second processor core configuration; and cause to be used one of the first processor core configuration or the second processor core configuration based on the comparison.
Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
G06F 1/26 - Power supply means, e.g. regulation thereof
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/383 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions using diffusion into, or out of, a solid from or into a gaseous phase
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A graph neural network (GNN) model is used in a scheduling process for compiling a deep neural network (DNN). The DNN, and parameter options for scheduling the DNN, are represented as a graph, and the GNN predicts a set of parameters that is expected to have a low cost. Using the GNN-based model, a compiler can produce a schedule for compiling the DNN in a relatively short and predictable amount of time, even for DNNs with many layers and/or many parameter options. For example, the GNN-based model reduces the overhead of exploring every parameter combination and does not exclude combinations from consideration like prior heuristic-based approaches.
Semiconductor packages and methods for forming semiconductor packages are disclosed. An example semiconductor package includes a substrate and a core. An insulator material is present over the core, and along a direction perpendicular to a first surface of the core, a portion of the insulator material is between the core and a first surface of the substrate. A via extends between the first surface of the core and a second surface of the core in the direction perpendicular to the first surface of the core. A bridge die is in a recess in the substrate. The bridge die is coupled with the via. An electronic component is coupled to an end of the via at a second surface of the substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
This disclosure describes systems, methods, and devices related to single-radio multi-channel medium access. A device may detect that a primary channel is occupied by a transmission of a first packet by a neighboring station device in an overlapping basic service set (OBSS). The device may detect that a secondary channel is idle. The device may select the secondary channel for packet transmission while the primary channel is occupied by the first packet. The device may cause to send a second packet to a first station device using the secondary channel.
An apparatus, system, and method for protecting a component from an observation attack are provided. A power balancing circuit configured to protect a cryptography component can include a ring oscillator electrically connected to a power supply, a time-to-digital converter (TDC) electrically connected to monitor an electrical parameter of the electrical power drawn by the cryptography component and provide data indicative of the electrical parameter, and a controller circuit configured to adjust a number of inverters of the ring oscillator drawing power from the power supply based on the data.
Various embodiments are generally directed to virtualized systems. A first guest memory page may be identified based at least in part on a number of accesses to a page table entry for the first guest memory page in a page table by an application executing in a virtual machine (VM) on the processor, the first guest memory page corresponding to a first byte-addressable memory. The execution of the VM and the application on the processor may be paused. The first guest memory page may be migrated to a target memory page in a second byte-addressable memory, the target memory page comprising one of a target host memory page and a target guest memory page, the second byte-addressable memory having an access speed faster than an access speed of the first byte-addressable memory.
A server system can have an electrical hierarchy that includes a transformer level, a bus segment level, a power distribution unit (PDU) level, and a server device level. The different levels can have nominal safety levels of power draw that are lower than the actual maximum power draw capability. Based on monitoring power draw at multiple levels of the electrical hierarchy, a power manager can determine that it is permissible for a server device, a group of server devices, or a portion of the electrical hierarchy to exceed the nominal safety level of power draw.
Disclosed herein are IC structures with one or more decoupling capacitors based on dummy TSVs provided in a support structure. An example decoupling capacitor includes first and second capacitor electrodes and a capacitor insulator between them. The first capacitor electrode is a liner of a first electrically conductive material on sidewalls and a bottom of an opening in the support structure, the opening in the support structure extending from the first side towards, but not reaching, the second side. The capacitor insulator is a liner of a dielectric material on sidewalls and a bottom of the opening in the support structure lined with the first electrically conductive material. The second capacitor electrode is a second electrically conductive material filling at least a portion of the opening in the support structure lined with the first electrically conductive material and with the dielectric material.
H01G 4/35 - Feed-through capacitors or anti-noise capacitors
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
61.
PACKAGE ARCHITECTURE WITH GLASS CORE SUBSTRATE HAVING INTEGRATED INDUCTORS
Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01F 41/00 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
62.
INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECISION INPUT OPERANDS
Disclosed embodiments relate to instructions for fused multiply-add (FMA) operations with variable-precision inputs. In one example, a processor to execute an asymmetric FMA instruction includes fetch circuitry to fetch an FMA instruction having fields to specify an opcode, a destination, and first and second source vectors having first and second widths, respectively, decode circuitry to decode the fetched FMA instruction, and a single instruction multiple data (SIMD) execution circuit to process as many elements of the second source vector as fit into an SIMD lane width by multiplying each element by a corresponding element of the first source vector, and accumulating a resulting product with previous contents of the destination, wherein the SIMD lane width is one of 16 bits, 32 bits, and 64 bits, the first width is one of 4 bits and 8 bits, and the second width is one of 1 bit, 2 bits, and 4 bits.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
63.
FLOATING-POINT DECOMPOSITION CIRCUITRY WITH DYNAMIC PRECISION
Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
Systems and methods may provide for receiving web content and determining a trust level associated with the web content. Additionally, the web content may be mapped to an execution environment based at least in part on the trust level. In one example, the web content is stored to a trust level specific data container.
G06F 21/51 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
65.
ADAPTIVE DEFORMABLE KERNEL PREDICTION NETWORK FOR IMAGE DE-NOISING
Embodiments are generally directed to an adaptive deformable kernel prediction network for image de-noising. An embodiment of a method for de-noising an image by a convolutional neural network implemented on a compute engine, the image including a plurality of pixels, the method comprising: for each of the plurality of pixels of the image, generating a convolutional kernel having a plurality of kernel values for the pixel; generating a plurality of offsets for the pixel respectively corresponding to the plurality of kernel values, each of the plurality of offsets to indicate a deviation from a pixel position of the pixel; determining a plurality of deviated pixel positions based on the pixel position of the pixel and the plurality of offsets; and filtering the pixel with the convolutional kernel and pixel values of the plurality of deviated pixel positions to obtain a de-noised pixel.
An apparatus of an access point multi-link device (AP MLD) is configured as a Transmitted Basic Service Set Identifier (TxBSSID) in a wireless network including a multiple BSSID (MBSSID) set. The apparatus includes memory and processing circuitry coupled to the memory and configured to encode beacon frames for transmission to non-AP MLDs in the wireless network. The transmission is on behalf of the TxBSSID and Non-Transmitted BSSIDs (NonTxBSSIDs) within the MBSSID set. A link recommendation frame is encoded for transmission to the non-AP MLDs. The link recommendation frame includes link recommendations for the non-AP MLDs associated with any APs in the MBSSID set. A group management cipher suite of the TxBSSID is used to protect the link recommendation frame encoded for the transmission.
Examples relate to an apparatus, a device, a method, a computer program (or computer-readable medium) and computer system for determining presence of a noisy neighbor virtual machine. Some aspects of the present disclosure relate to an apparatus for a computer system, the apparatus comprising interface circuitry, machine-readable instructions, and processor circuitry to execute the machine-readable instructions to obtain performance information of one or more hardware performance measurement components of the computer system, determine, based on the performance information, a deviation of a utilization of the computer system from an expected utilization of the computer system, and determine presence of a first virtual machine having a workload that impacts a performance of one or more second virtual machines based on the deviation.
Systems, apparatus, articles of manufacture, and methods are disclosed to generate super-resolution upscaling. An example apparatus to process an image disclosed herein includes interface circuitry to accept input image data with a first resolution, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to upscale the input image data based on an upscale factor to generate intermediate image data with a second resolution higher than the first resolution, process the input image data with a neural network to produce neural network output data with a number of channels per pixel that is based on the upscale factor, combine the intermediate image and the neural network output data to generate output image data with the second resolution.
Systems, apparatus, articles of manufacture, and methods are disclosed that compile portable code for specific hardware are disclosed herein that include an apparatus including computer readable instructions, and programmable circuitry to at least one of execute or instantiate the instructions to receive input code, the input code written for operation on a first platform, determine a target platform, the target platform different than the first platform, and translate, via an artificial intelligence (AI) model, the input code to output code, the output code written for operation on the target platform.
A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, generate first intermediate data, and store the first intermediate data to a storage. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data from the storage, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
72.
SYSTEMS AND METHODS FOR AN ACCELERATED AND ENHANCED TUNING OF A MODEL BASED ON PRIOR MODEL TUNING DATA
Disclosed examples including generating a joint model based on first and second subject models, the first and second subject models selected based on a relationship between the first and second subject models; selecting the joint model from a plurality of joint models after a determination that entropy data points of the joint model satisfy a threshold, the entropy data points based on multiple tuning trials of the joint model; and providing tuning data associated with the joint model to a tuning session of a target model.
A chip or other apparatus of an aspect includes a first accelerator and a second accelerator. The first accelerator has support for a chained accelerator operation. The first accelerator is to be controlled as part of the chained accelerator operation to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data. The second accelerator also has support for the chained accelerator operation. The second accelerator is to be controlled as part of the chained accelerator operation to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data. Other apparatus, methods, systems, and machine-readable medium are disclosed.
This disclosure describes systems, methods, and devices for configuring sounding reference signal resources across multiple frequency locations for device positioning. A device may encode for transmission a sounding reference signal (SRS) including a first set of SRS resources for a first transmission by a user equipment (UE) device to the node B network device at a first time and a second set of SRS resources for a second transmission by the UE device to the node B network device at a second time; decode the first transmission received from the UE device using the first set and a first bandwidth at the first time; decode the second transmission received from the UE device using the second set and a second bandwidth at the second time; and combine the first transmission and the second transmission for a device positioning estimation based on the first bandwidth and the second bandwidth.
Various approaches of an edge-native management system, including a session management function application for configuration of edge applications and network traffic functions, are disclosed. An example method for configuration of an edge computing application, performed by a session management function application, includes: receiving network information from an edge computing platform (e.g., MEC platform) that includes an edge computing application (e.g., MEC App), with the network information being received via a network experience function (NEF) of a mobile network (e.g., 3GPP 5G network); transmitting a request to the edge computing platform, based on the received network information, the request including an application data traffic configuration action to perform on the edge computing application; and receiving a response to the request from the edge computing platform, with the response indicating a status of the application data traffic configuration action performed on the edge computing application.
H04L 67/61 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources taking into account QoS or priority requirements
H04L 67/10 - Protocols in which an application is distributed across nodes in the network
G06F 9/451 - Execution arrangements for user interfaces
A user equipment (UE) configured for carrier frequency operations above 52.6 GHz may decode radio-resource control (RRC) signalling received from a gNodeB (gNB) to configure the UE with a number of resource blocks (RBs) (NRB) for a physical uplink control channel (PUCCH) resource for each of one or more enhanced PUCCH formats. The one or more enhanced PUCCH formats may include enhanced PUCCH format 0, enhanced PUCCH format 1 and enhanced PUCCH format 4. The number of RBs may be configurable to be more than one for the enhanced PUCCH format 0, the enhanced PUCCH format 1 and the enhanced PUCCH format 4. The UE may encode an enhanced PUCCH format for transmission in accordance with one of the enhanced PUCCH format 0, the enhanced PUCCH format 1 and the enhanced PUCCH format 4. The enhanced PUCCH format may be transmitted to occupy the number of RBs that are configured.
Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
One or more non-transitory computer-readable media with instructions stored thereon, wherein the instructions are executable to cause one or more processor units to responsive to a data clear command issued by a tenant of a cloud service provider, issue a plurality of write commands to storage locations utilized by the tenant, the write commands to write a value based on an input provided by the tenant to the storage locations; and provide data read from at least a subset of the storage locations for attestation by the tenant of performance of the data clear command.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
Embodiments are directed to providing integrity-protected command buffer execution. An embodiment of an apparatus includes a computer-readable memory comprising one or more command buffers and a processing device communicatively coupled to the computer-readable memory to read, from a command buffer of the computer-readable memory, a first command received from a host device, the first command executable by one or more processing elements on the processing device, the first command comprising an instruction and associated parameter data, compute a first authentication tag using a cryptographic key associated with the host device, the instruction and at least a portion of the parameter data, and authenticate the first command by comparing the first authentication tag with a second authentication tag computed by the host device and associated with the command.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
An electronic circuitry is proposed. The electronic circuitry comprises a directional coupler comprising a first port configured to receive an input signal from a signal source, a second port configured to output the input signal for transmission to a load, a third port configured to output a forward signal based on the input signal, and a fourth port configured to output a reverse signal based on a reflection of the input signal received at the second port. The electronic circuitry further comprises a Time-to-Digital converter, TDC, coupled to the third port and the fourth port. The TDC is configured to determine a phase difference between the forward signal and the reverse signal.
Systems, apparatuses and methods may provide for technology that detects a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generates a combined read-lock request for the plurality of atomic instructions in response to the condition, and sends the combined read-lock request to a lock buffer coupled to a memory device associated with the common address.
Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.
H04L 69/16 - Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
H04L 69/164 - Adaptation or special uses of UDP protocol
H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitions; Interfaces between layers
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
83.
TEMPORALLY AMORTIZED SUPERSAMPLING USING A KERNEL SPLATTING NETWORK
One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. The set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.
A method for authenticating features reported by a vehicle includes receiving, from a network, a map of an area with confidence weights corresponding to each feature on the map and/or a list of trusted users; upon the vehicle entering the area, checking whether the vehicle is on the list of trusted users; and checking features reported from the vehicle and matching the features to the map of the area.
H04W 4/46 - Services specially adapted for particular environments, situations or purposes for vehicles, e.g. vehicle-to-pedestrians [V2P] for vehicle-to-vehicle communication [V2V]
G08G 1/01 - Detecting movement of traffic to be counted or controlled
Methods, systems, apparatus, and articles of manufacture to augment training data based on synthetic images are disclosed. An example apparatus disclosed herein includes programmable circuitry to generate, with one or more first layers of a generative adversarial network (GAN), a latent representation corresponding to a first image representative of a first racial domain, generate, with one or more second layers of the GAN, a second image based on the latent representation, the second image corresponding to a second racial domain different from the first racial domain, and augment a training dataset based on the second image.
Methods, apparatus, and computer programs are disclosed for managing processor power consumption based on message queue utilization. In one embodiment, a method comprising: distributing messages to a set of processor cores of a processor, wherein one message is distributed per distribution round to one queue within a set of queues, each queue corresponding to one processor core within the set of processor cores and including one or more queue entries to be processed by the one processor core, and where the distribution is based on utilization of the set of queues; based on utilization of a corresponding queue for a processor core of the set of processor cores, determining a power state for the processor core to be changed to; and distributing a message to the corresponding queue, the message to cause the processor core to be set to the power state.
Methods and apparatuses relating to processing neural networks are described. In one embodiment, an apparatus to process a neural network includes a plurality of fully connected layer chips coupled by an interconnect; a plurality of convolutional layer chips each coupled by an interconnect to a respective fully connected layer chip of the plurality of fully connected layer chips and each of the plurality of fully connected layer chips and the plurality of convolutional layer chips including an interconnect to couple each of a forward propagation compute intensive tile, a back propagation compute intensive tile, and a weight gradient compute intensive tile of a column of compute intensive tiles between a first memory intensive tile and a second memory intensive tile.
An electronic device includes first and second external conductive pads coupled to route a first signal and third and fourth external conductive pads. The third and the fourth external conductive pads are between the first and the second external conductive pads on a surface of the electronic device.
Contact over active gate (COAG) structures with conductive gate taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. Each of the plurality of gate structures includes a conductive tap structure protruding through the corresponding gate insulating layer. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. An opening is in the interlayer dielectric material and exposes the conductive tap structure of one of the plurality of gate structures. A conductive structure is in the opening and is in direct contact with the conductive tap structure of one of the plurality of gate structures.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Systems, apparatus, articles of manufacture, and methods are disclosed to accelerate service execution. An example apparatus includes a system including first circuitry to initialize during a boot time period, and at least one of audio circuitry and networking circuitry to complete initialization and perform a service before expiration of the boot time period.
Examples described herein relate to utilizing a bus driver to present a peripheral device comprising a single physical function to a host operating system (OS) as a plurality of peripheral devices, associating the plurality of presented peripheral devices with a corresponding plurality of physical Ethernet ports; and enabling the host OS to interact with the plurality of peripheral devices. In some examples, the number of the plurality of peripheral devices correlates to the number of physical Ethernet ports associated with the peripheral device.
Apparatuses, methods and storage medium for computing including determination of work placement on processor cores are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a favored core of the processor cores. The one or more processors, devices, and/or circuitry may be configured to determine whether to migrate a thread to or from the favored core. In some embodiments, the determination may be by a process executed by a driver and/or by an algorithm executed by a power control unit of the processor.
Photonically steered impedance surface antennas are disclosed. A disclosed example apparatus includes a semiconductor substrate to be communicatively coupled to a radio frequency (RF) source, an at least partially transparent dielectric layer, the semiconductor substrate at a first side of the at least partially transparent dielectric layer, an at least partially transparent conductive film at a second side of the at least partially transparent dielectric layer that is opposite the first side of the at least partially transparent dielectric layer, and an illumination source to illuminate at least a portion of the semiconductor substrate to generate a photoinduced solid-state plasma pattern that beam steers an RF signal corresponding to the RF source.
H01Q 3/26 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture
An apparatus, method, and system are described for data transfer between a user equipment (UE) and Data Storage Function (DSF) in a 6G system. The data transfer occurs via a control and/or user plane using a data ID and data filter defined using data ID, metadata, data source, and labeling. User plane data transfer is based on a protocol data unit (PDU) or a standalone data session. The DSF provides data services by service application programming interfaces (APIs). A Service Infrastructure Control Function (SICF) configures routing policies to an evolved Service Communication Proxy User Plane (eSCP-U) to route data inquiries to the correct DSF using a service mesh.
An apparatus and method to implement shared virtual memory in a trust zone. For example, one embodiment of a processor comprises: a plurality of cores; a memory controller coupled to the plurality of cores to establish a first private memory region in a system memory using a first key associated with a first trust domain of a first guest; an input/output memory management unit (IOMMU) coupled to the memory controller, the IOMMU to receive a memory access request by an input/output (IO) device, the memory access request comprising a first address space identifier and a guest virtual address (GVA), the IOMMU to access an entry in a first translation table using at least the first address space identifier to determine that the memory access request is directed to the first private memory region which is not directly accessible to the IOMMU, the IOMMU to generate an address translation request associated with the memory access request, wherein based on the address translation request, a virtual machine monitor (VMM) running on one or more of the plurality of cores is to initiate a secure transaction sequence with trust domain manager to cause a secure entry into the first trust domain to translate the GVA to a physical address based on the address space identifier, the IOMMU to receive the physical address from the VMM and to use the physical address to perform the requested memory access on behalf of the IO device.
Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
97.
MULTI-PHASE SIGNAL GENERATION SCHEME AND METHOD THEREOF
The present disclosure relates to a signal generator including: a plurality of interpolators, each interpolator being configured to: receive a first input signal having a first phase, and a second input signal having a second phase; generate a plurality of interpolated signals based on a plurality of interpolations of the input signals, each interpolated signal having a respective phase based on the respective interpolation, and combine the interpolated signals to provide an output signal; the plurality of interpolators including: a first plurality of interpolators, each interpolator being configured to receive as input signals a first reference signal and a second reference signal; and a second plurality of interpolators, each interpolator being configured to receive as first input signal an output signal from an interpolator of the first plurality of interpolators and as second input signal another output signal from another interpolator of the first plurality of interpolators.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
98.
DATA COLLECTION COORDINATION FUNCTION AND NETWORK DATA ANALYTICS FUNCTION FRAMEWORK FOR SENSING SERVICES IN NEXT GENERATION CELLULAR NETWORKS
This disclosure describes systems, methods, and devices related to sensing service coordination. A device may discover a Network Data Analytics Function (NWDAF) via a Network Function Repository Function (NRF). The device may send an Analytics request or subscribe to the selected NWDAF with a criteria based on a sensing data analytics ID, event ID, and event parameters. The device may select a Data Collection Coordination Function (DCCF) instance when DCCF is used for data collection, based on DCCF Serving Area Information. The device may receive sensing data or data analytics from the NWDAF after NWDAF has processed the data collected from DCCF.
Logic may parse an application function (AF) request from an AF, the AF request comprising a first set of parameters, the first set of parameters comprising a first geographical area and a sensing type. Logic may identify a radio access network (RAN) node based on the first geographical area. Logic may send a sensing request to the RAN node, the sensing request comprising a second set of parameters to identify sensing information, the second set of parameters comprising a second geographical area and a sensing type. Logic may receive a sensing result from the RAN node based on the second set of parameters. And logic may process the sensing result based on the AF request to determine a sensing report; and send, to the AF, the sensing report via the network interface.
For example, a wireless communication device may be configured to determine a Concurrent Multiple Band (CMB) routing scheme based on Quality of Service (QoS) requirement information and network condition information, the CMB routing scheme to route a plurality of application streams to a plurality of radios of the wireless communication device for wireless communication over a plurality of wireless communication bands, the plurality of application streams corresponding to one or more applications to be executed by the wireless communication device; and to route the plurality of application streams to the plurality of radios by determining, based on the CMB routing scheme, to which radio of the plurality of radios to route the application stream of the plurality of application streams.
