A mixed-signal circuit may include an analog circuit and a digital circuit coupled to the analog circuit, wherein the analog circuit is configured to, in a normal operation mode, provide an analog signal to the digital circuit, and wherein the digital circuit is configured to, in the normal operation mode, provide a digital signal to the analog circuit, the mixed-signal circuit may further include a test signal generator configured to, during a test operation mode, receive the digital signal from the digital circuit, generate a test signal based on the digital signal, and provide the test signal to the digital circuit, wherein the test signal generator is configured to generate the test signal using an emulation of the analog circuit, and wherein the mixed-signal circuit is tested based on an output of the digital circuit that is generated in response to the test signal.
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure. The semiconductor structure also includes one or more gate electrodes, each gate electrode disposed over the channel region of one or more of the plurality of parallel semiconductor fins.
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Covers for integrated circuit package sockets are disclosed herein. An example cover for a socket for an integrated circuit package includes a base including a cutout, the cutout to engage a pin associated with the socket, engagement of the cutout and the pin to maintain a position of the cover relative to the socket; and a handle to facilitate positioning of the cover to move the cutout into engagement with the pin.
A cooling system includes a cooling fluid bypass to direct cooling fluid around a processor device to a memory module shadowed by the processor device from the cooling fluid flow. The fluid bypass allows the system to direct cooling fluid to the shadowed memory module that has not been used to cool the processor. There are various configurations, allowing the bypassing of different amounts of cooling fluid, allowing system designers to balance a tradeoff between processor heat and memory module heat.
A user equipment (UE) may generate first HARQ-ACK information bits based on a first PDSCH and second HARQ-ACK information bits based on a second PDSCH. The UE may determine a first slot for an expected PUCCH transmission with the first HARQ-ACK information bits. When the UE is configured for deferring HARQ-ACK for the first PDSCH and when the first slot is unavailable for the expected PUCCH transmission, the UE may determine an earliest second slot that is available. The UE may also determine a third slot for an expected PUCCH transmission with the second HARQ-ACK information bits assigned for the second PDSCH. The resource assigned for transmission of the first HARQ-ACK information bits is used to verify the order for the first and second HARQ-ACK transmissions regardless of whether the first slot is unavailable and the second earliest slot is used for transmission of the first HARQ-ACK information bits.
Disclosed herein are antenna modules, electronic assemblies, and communication devices. An example antenna module includes an IC component, an antenna patch support over a face of the IC component, and a stack of antenna patches vertically arranged at least partially above one another, where a first antenna patch of the stack is an antenna patch closest to the IC component, and a second antenna patch of the stack is an antenna patch closest to the first antenna patch. The first antenna patch is on the face of the IC component while the second and further antenna patches of the stack are on or in the antenna patch support and are electrically isolated from all electrically conductive material pathways in the antenna patch support and in the IC component.
Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.
An apparatus to facilitate acceleration of machine learning operations is disclosed. The apparatus comprises at least one processor to perform operations to implement a neural network and accelerator logic to perform communicatively coupled to the processor to perform compute operations for the neural network.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/78 - Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
G06F 9/00 - Arrangements for program control, e.g. control units
G06N 3/084 - Backpropagation, e.g. using gradient descent
A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
10.
COVERAGE FOR PHYSICAL RANDOM ACCESS CHANNEL AND REPETITION OF CSI REPORT ON PUSCH FOR COVERAGE ENHANCEMENT
Various embodiments herein relate to techniques that may improve coverage for a physical random access channel (PRACH). Additionally, some embodiments may relate to techniques for repetition of a channel state information (CSI) report on a physical uplink shared channel (PUSCH) for coverage enhancement. Other embodiments may be described and/or claimed.
Example apparatus disclosed includes at least one memory, machine readable instructions, and programmable circuitry to at least one of instantiate or execute the machine readable instructions to process a first frame of a video sequence with a neural network, store intermediate outputs of at least one of a convolution layer or a pooling layer of the neural network, the intermediate outputs associated with the first frame, process a second frame of the video sequence based on the intermediate outputs associated with the first frame to skip processing of a temporally static area of the second frame by the at least one of the convolution layer or a pooling layer, the temporally static image area common to the first frame and the second frame.
Voltage converters using switch capacitor voltage converters are described. In some implementations, a hybrid converter having a switch capacitor voltage converter coupled with a downstream second voltage converter such as a buck regulator or LDO is described. It may incorporate circuitry for reducing output offset from the switch cap converter, which in turn, may reduce voltages exposed to switch transistors used in the downstream voltage regulator.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
13.
METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO MANAGE BATTERY OUTGASSING CONDITIONS
Systems, apparatus, articles of manufacture, and methods are disclosed to manage battery outgassing conditions. An example apparatus includes an enclosure having a first conductive surface located proximate to an outer boundary of the enclosure, a second conductive surface located a first distance from the first conductive surface, a capacitance circuit coupled to the first conductive surface and the second conductive surface, and a charge control circuit to control an input signal to the second conductive surface and a third conductive surface based on an output of the capacitance circuit.
G01R 31/392 - Determining battery ageing or deterioration, e.g. state of health
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
14.
SELF-ALIGNED VIA PATTERNING FOR BACKSIDE INTERCONNECTS
Devices, transistor structures, systems, and techniques are described herein related to coupling backside and frontside metallization layers that are on opposite sides of a device layer. A device includes a transistor having semiconductor structures extending between a source and a drain, and a gate between the source and drain, a bridge via extending between a frontside metallization over the transistor and a backside metallization below the transistor, and a thin insulative liner between the bridge via and components of the transistor.
A computer-implemented method of audio processing comprises receiving, by at least one processor, multiple audio signals from multiple microphones. The audio signals are associated with audio emitted from a same source. The method also may include determining an audio quality indicator of individual ones of the audio signals using a neural network, and selecting at least one of the audio signals depending on the audio quality indicators.
G10L 21/028 - Voice signal separating using properties of sound source
G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks
G10L 25/60 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination for measuring the quality of voice signals
H04R 5/027 - Spatial or constructional arrangements of microphones, e.g. in dummy heads
According to the various aspects, the present disclosure is directed to printed circuit board assemblies having a plurality of printed circuit board units or modules that use board connectors for joining the printed circuit board units. In an aspect, the board connector has a first surface, which may be a top surface, and an opposing second surface, which may be a bottom surface, and a plurality of openings, including a first set of connector openings for providing electrical connections between the at least two plurality of printed circuit board units. In another aspect, a method that includes forming a first printed circuit board unit with a first connecting portion and a second printed circuit board unit with a second connecting portion, and the first and second connecting are electrically coupled with the printed circuit board connector.
A circuit comprising: an analog-to-digital converter configured to generate a digital signal based on a received input voltage and a received reference voltage; a capacitor array; and a switching network configured to switch each capacitor of the capacitor array between a first conductor connected to a supply voltage source, and a second conductor connected to the reference voltage; wherein the analog-to-digital converter comprises a logic configured to control the switching network to selectively switch between the first conductor and the second conductor based on the generated digital signal.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
18.
CONTENT SUMMARIZATION AND/OR RECOMMENDATION APPARATUS AND METHOD
Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.
Embodiments described herein include a liquid metal carrier. In an embodiment, the liquid metal carrier includes a substrate that is a polymer. In an embodiment, a first opening is provided through the substrate with a first shape, and a second opening is provided through the substrate with a second shape. In an embodiment, the first shape is different than the second shape.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
21.
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC
Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
22.
KINEMATICALLY ALIGNED OPTICAL CONNECTOR FOR SILICON PHOTONIC INTEGRATED CIRCUITS (PICs) AND METHOD FOR MAKING SAME
A kinematically aligned optical connector may be implemented with a silicon PIC component and a glass substrate component. The kinematically aligned optical connector includes one or more kinematic connectors or mechanical alignment features and visual fiducials that enable true kinematic coupling (i.e., in a three-dimensional Cartesian coordinate system, full constraint in all 6 degrees of freedom, meaning, X, Y, Z planes and all 3 angles), and enables an increased thickness of the glass substrate material of the glass waveguide substrate.
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
23.
INTEGRATED CIRCUIT DEVICES WITH FISHBONE CAPACITOR STRUCTURES
Disclosed herein are IC devices with fishbone capacitor structures. An example capacitor structure includes a first capacitor electrode, a second capacitor electrode, and a third capacitor electrode, wherein the first capacitor electrode is a first line with protrusions on a side of the first line, the second capacitor electrode is a second line with protrusions on a first side of the second line and protrusions on a second side of the second line, the third capacitor electrode is a third line with protrusions on a side of the third line, the protrusions on the side of the first line and the protrusions on the first side of the second line form a first interdigitated capacitor structure, and the protrusions on the side of the third line and the protrusions on the second side of the second line form a second interdigitated capacitor structure.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
G09G 5/36 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory
G09G 5/38 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of individual graphic patterns using a bit-mapped memory with means for controlling the display position
G09G 5/391 - Resolution modifying circuits, e.g. variable screen formats
25.
MICROELECTRONIC ASSEMBLIES HAVING AN INTEGRATED CAPACITOR
Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/528 - Layout of the interconnection structure
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
26.
PHOTONIC INTEGRATED CIRCUIT EDGE COUPLING AND FIBER ATTACH UNIT ATTACHMENT STRESS RELIEF
The substrate of an integrated circuit component comprises a cutout that extends fully or partially through the substrate. An edge of a photonic integrated circuit (PIC) in the integrated circuit component is coplanar with a wall of the cutout or extends into the cutout. An optical fiber in an FAU is aligned with a waveguide within the PIC and the FAU is attached to the PIC edge and an attachment block. The attachment block provides an increased attachment surface area for the FAU. A portion of the FAU extends into the substrate cutout. A stress relief mechanism can secure the fiber optic cable attached to the FAU to the substrate to at least partially isolate the FAU-PIC attachment from external mechanical forces applied to the optical fiber cable. The integrated circuit component can be attached to a socket that comprises a socket cutout into which an FAU can extend.
Gesture input with multiple displays, views, and physics is described. In one example, a method includes generating a three dimensional space having a plurality of objects in different positions relative to a user and a virtual object to be manipulated by the user, presenting, on a display, a displayed area having at least a portion of the plurality of different objects, detecting an air gesture of the user against the virtual object, the virtual object being outside the displayed area, generating a trajectory of the virtual object in the three-dimensional space based on the air gesture, the trajectory including interactions with objects of the plurality of objects in the three-dimensional space, and presenting a portion of the generated trajectory on the displayed area.
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G06F 3/03 - Arrangements for converting the position or the displacement of a member into a coded form
G06F 3/0481 - Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
Technologies for streaming device role reversal include a source computing device and a destination computing device coupled via a communication channel. The source computing device and destination computing device are each configured to support role reversal. In other words, the source computing device and the destination computing device are each capable of switching between receiving and transmitting digital media content over the established communication channel. The source computing device is configured to initiate the role reversal, pause transmit functionality of the source computing device, and enable receive functionality of the source computing device. The destination computing device is configured to receive a role reversal indication from the source computing device, locally process the content, transmit a content stream to the source computing device, and display the content stream on an output device of the source computing device. Other embodiments are described and claimed herein.
H04L 65/61 - Network streaming of media packets for supporting one-way streaming services, e.g. Internet radio
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
29.
METHOD AND APPARATUS FOR SCHEDULING ACCESS TO MULTIPLE ACCELERATORS
Methods, apparatus, and computer programs are disclosed to schedule access to multiple accelerators. In one embodiment, a method is disclosed to perform: receiving a first request to process data for a first application by a first accelerator of a plurality of accelerators of a computing system, an accelerator of the plurality of accelerators being dedicated to one or more respective specialized computations of the computing system for data processing; scheduling resources for the first request based on the first request and a second request to process data for a second application by a second accelerator of the plurality of accelerators, the first and second requests having one or more priority indications indicating priority between the first and second requests; and processing the data for the first application using the resources as scheduled responsive to the first request.
Provided is a method comprising obtaining information about a detected memory error in a memory device, the memory device being connected to a first host via a compute express link, CXL, interface. The method comprises further recording the memory error information into a firmware of the memory device.
A system enables an alert signal test mode. The system has an alert signal line between the memory device and the memory controller. The memory device has a register that controls entry into the alert signal test mode. The memory controller sends a command to trigger the memory device to enter the alert signal test mode. In response to the commands, the memory device asserts the alert signal line with an alert signal in response to entry into the alert signal test mode.
Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 7/58 - Random or pseudo-random number generators
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 12/0871 - Allocation or management of cache space
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0893 - Caches characterised by their organisation or structure
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
H03M 7/46 - Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
Hybrid and adaptive cooling systems are described. A method comprises selecting a cooling system type from a set of cooling system types of a hybrid cooling system to cool an electronic component of an electronic device, generating a control directive to activate a cooling component of the cooling system type, and performing thermal management of the electronic component of the electronic device using the cooling component of the cooling system type. Other embodiments are described and claimed.
An activation function in a neural network may be approximated by one or more linear functions. A linear function may correspond to a segment of the input range of the activation function, e.g., a linear segment. A programmable look-up table may store slopes and intercepts of linear functions. A post processing engine (PPE) array executing the activation function may determine that an input data element of the activation function falls into the linear segment and compute an output of the linear function using the input data element. The output of the linear function may be used as the approximated output of the activation function. Alternatively, the PPE array may determine that the input data element is in a saturation segment and use a fixed value associated with the saturation segment as the approximated output of the activation function.
Embodiments herein relate to a voltage converter with a floating level shifter. The floating level shifter is implemented on a silicon substrate using complementary metal-oxide semiconductor (CMOS) technology while the power train is implemented on a Gallium Nitride substrate. The floating level shifter may be all-digital and avoid the use of passive devices. The floating level shifter is responsive to a voltage output from a bootstrap circuit, a voltage of a switching node of a power train and a drive voltage of the bootstrap circuit, to shift an input signal to an output signal in a charge phase of a switching cycle. The output signal drives a high-side driver for a high-side transistor of the power train, where the voltage output from the bootstrap circuit and the voltage of the switching node alternate in charge and discharge phases of the switching cycle.
H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/003 - Modifications for increasing the reliability
36.
HEAT DISSIPATION SOLUTIONS FOR INTEGRATED CIRCUIT PACKAGES
In one embodiment, an integrated circuit package includes a package substrate, a first integrated circuit die electrically coupled to the package substrate via wire bond connectors, and a second integrated circuit die coupled to the package substrate. The package further includes a heat spreader coupled to the first integrated circuit die via a thermal interface material (TIM) and a dielectric material encompassing the first integrated circuit die and the second integrated circuit die on the package substrate. A top surface of the heat spreader is aligned with a top surface of the dielectric material.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A data transmitter with a phase detector, average duty cycle sensor and phase sampler to optimize a clock/data paths. Phase and duty cycle information are provided to a digital control to adjust a timing in the data path and clock path, respectively. The phase detector reads a skew between the data and negative and positive phase clock signals inside a driver. An optimal pulse width delta is determined by the target duty cycle sensor. Using a measured averaged duty cycle sensor, the digital control calculates the duty cycle error to the target value that is needed inside the driver. The phase sampler has a multiplexer which routes the clock signals to phase sensors which determine a phase error based on, e.g., a rising edge-to-rising edge comparison and a falling edge-to-falling edge comparison. In addition, it includes a duty cycle sensor for each clock phase.
Disclosed herein are devices, systems, and methods for a predictive imaging system to determine exposure-related settings for a scene that is to be captured by an imagining device. The predictive imaging system determines a motion of the scene that is to be captured by an image sensor of the imaging device and determines an exposure-related configuration setting of the imaging device, where the exposure-related configuration setting is based on the determined motion of the scene. The predictive imaging system then generates an instruction for the imaging device to capture the scene using the determined configuration setting.
Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
Embodiments are provided for summarization and recommendation of content. In disclosed embodiments, a summarization engine scores constituent parts of content, and generates a plurality of summaries from a plurality of points of view for the content based at least in part on the scores of constituent parts. The summaries may be formed with constituent parts extracted from the contents. A recommendation engine provides recommendations to a user based on rankings of the summaries generated by the summarization engine. Other embodiments may be described and/or claimed.
Systems, apparatuses and methods may provide for technology including a digital to analog conversion (DAC) stage to generate analog input activation signals, a multiply-accumulate (MAC) computation stage coupled to the DAC stage, the MAC computation stage to generate output activation results based on the analog input activation signals and multi-bit weight data stored in the MAC computation stage, an analog integration stage coupled to the MAC computation stage, the analog integration stage to conduct partial sum accumulations on the output activation results, and analog to digital conversion (ADC) stage coupled to the analog integration stage, the ADC stage to generate digital computation results based on an output of the analog integration stage, and a controller to vary a number of cycles in the partial sum accumulations based on an overflow condition associated with one or more of the output activation results or the output of the analog integration stage.
H03M 1/14 - Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and accelerate the packet-processing pipeline for the network data packet through the machine by processing the action.
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
43.
UNIFIED PROGRAMMING INTERFACE FOR REGRAINED TILE EXECUTION
Systems, apparatuses and methods may provide for technology that detects a tensor operation in an application, wherein the tensor operation has an unspecified tensor input size, determines the input tensor size at runtime, and selects a partition configuration for the tensor operation based at least in part on the input tensor size and one or more runtime conditions. In one example, the technology searches a lookup table for the input tensor size and at least one of the runtime condition(s) to select the partition configuration.
Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A method for implementing a programmable device is provided. The method may include extracting an underlay from an existing routing network on the programmable device and then mapping a user design to the extracted underlay. The underlay may represent a subset of fast routing wires satisfying predetermined constraints. The underlay may be composed of multiple repeating adjacent logic blocks, each implementing some datapath reduction operation. Implementing circuit designs in this way can dramatically improve circuit performance while cutting down compile times by more than half.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/03 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes
46.
MULTI-MEANS LOCALLY-ADAPTIVE VECTOR QUANTIZATION FOR MEMORY EFFICIENT AND HIGH-PERFORMANCE STREAMING SIMILARITY SEARCH
Systems, apparatuses and methods may provide for technology that determines a plurality of means based on a plurality of vectors, wherein each mean in the plurality of means corresponds to center of a cluster, assigns each vector in a plurality of vectors to a mean in the plurality of means, and conducts a compression of the plurality of vectors based on the plurality of means. The technology may also build a directed graph based on the compressed plurality of vectors and update the directed graph. Updating the graph may involve determining a plurality of modified means, detecting that a change in one or more modified means in the plurality of modified means exceeds a threshold, conducting an update of the modified mean(s), and bypassing the update for one or more remaining means in the plurality of modified means.
Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Systems, apparatus, articles of manufacture, and methods are disclosed for accessories for electronic devices and removable fan cartridges for electronic devices. An example electronic device accessory includes a backplate panel removably couplable to a first chassis of a first electronic device to replace a portion of a first cover of the first chassis and removably couplable to a second chassis of a second electronic device to replace a portion of a second cover of the second chassis. The example electronic device accessory also includes a mating device to releasably couple the backplate panel to the first chassis and independently releasably couple the backplate panel to the second chassis and a fan coupled to the backplate panel. The fan is to increase a Z height of the first electronic device when the backplate panel is coupled to the first electronic device and increase a Z height of the second electronic device when the backplate panel is coupled to the second electronic device.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
An integrated circuit (IC) package includes a via extending through a stack of antipads in a stack of layers, and the stack of antipads has an antipad with a shorter diameter between antipads with longer diameters. The via may have first and second connections and first and second pads at or over and under the antipads. The longer diameters (over and under the shorter diameter) may be equal. Intervening antipads of intermediate size may be between the smallest antipads and the largest antipads. An antipad void profile may be tapered and concave, with flatter slopes nearer the upper and lower ends of the via and steeper slopes near a via midpoint. A second via may be adjacent the first via. One or more other vias may have an aligned (rather than a tapered) profile.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
Integrated circuit structures having partial channel cap removal, and methods of fabricating integrated circuit structures having partial channel cap removal, are described. For example, an integrated circuit structure includes a sub-fin structure beneath a stack of nanowires. A dielectric channel cap has an opening over the stack of nanowires. A gate electrode is over and around the stack of nanowires. A gate dielectric structure is between the gate electrode and the stack of nanowires. A conductive tap is on the gate electrode and in the opening in the dielectric channel cap. A dielectric layer is on the gate electrode and laterally adjacent to the conductive tap.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
54.
ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT WITH ULTRA LOW-LEAKAGE
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
55.
SELECTIVE UNDERFILLING USING PRE-APPLIED THERMOSET ADHESIVE
Integrated circuit (IC) packages with pre-applied underfill in select areas, and methods of forming the same, are disclosed herein. In one example, an IC package includes a package substrate, a first IC die electrically coupled to the package substrate, a second IC die electrically coupled to the first IC die, and a thermoset adhesive that partially fills an area between the first IC die and the second IC die.
Methods and apparatus for moisture degree detection are disclosed. An example apparatus for use with an input device includes trace routing positioned at or proximate a contact area of the input device, the trace routing including a first electrode, and a second electrode separated from the first electrode by a distance; and an amplifier electrically coupled to the first electrode and the second electrode, the amplifier to provide a signal based on a resistance related to a degree of moisture present between the first electrode and the second electrode.
G01N 27/04 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
G06F 1/16 - Constructional details or arrangements
Disclosed herein are devices, systems, and methods for self-sanitizing a device using the built-in screen display of the device (e.g., a laptop). The device includes a processor configured to execute instructions to determine a relationship between a location of a display of the device and a location of a keyboard surface of the device. The processor is also configured to execute instructions configured to, based on the relationship, enable a sanitization mode on the device and to configure the display to emit light toward the keyboard surface to sanitize the keyboard surface when the sanitization mode is enabled.
Embodiments herein relate to a temperature-sensing circuit for a semiconductor device. The circuit has a remote temperature-sensing element (RTSE) including a metal thermistor formed in a metal layer on the front side or backside of a substrate. The metal thermistor may be serpentine or spiral shaped. The RTSE communicates with a separate sense circuit at another location such as on the substrate. The RTSE can further include a thin film resistor (TFR) in an adjacent dielectric layer of the stack or within the sense circuit. The RTSE is driven alternately at opposing ends to cancel out the effects of power supply variations. An output voltage which represents a sensed temperature is obtained from a point between the metal thermistor and the TFR for processing by an analog-to-digital converter.
G01K 7/22 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a non-linear resistance, e.g. thermistor
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
59.
MULTI-PORT MEDIA ACCESS CHANNEL (MAC) WITH FLEXIBLE DATA-PATH WIDTH
Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.
An accelerator includes a memory, a compute zone to receive an encrypted workload downloaded from a tenant application running in a virtual machine on a host computing system attached to the accelerator, and a processor subsystem to execute a cryptographic key exchange protocol with the tenant application to derive a session key for the compute zone and to program the session key into the compute zone. The compute zone is to decrypt the encrypted workload using the session key, receive an encrypted data stream from the tenant application, decrypt the encrypted data stream using the session key, and process the decrypted data stream by executing the workload to produce metadata.
H04L 9/06 - Arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
This disclosure describes systems, methods, and devices for performing performance measurements for one-way uplink packet delay in wireless communications. An apparatus of a Service Based Management Architecture (SBMA) Management Service (MnS) Producer may identify performance measurements, received from a network function (NF) of a 5th Generation (5G) wireless network, indicative of uplink packet delay between a user equipment (UE) and a protocol data unit (PDU) session anchor (PSA) user plane function (UPF) of the 5G wireless network; detect whether the performance measurements indicate that the uplink packet delay includes an uplink PDCP delay occurred in the UE (D1); and generate performance metrics for the NF using the performance measurements.
Examples described herein relate to a network interface device comprising: an interface to a port; and circuitry to: perform parallel evaluation of multiple rules for a packet; drop the packet based at least in part on an indication by the parallel evaluation that communication with a target is not permitted; and permit communication of the packet based at least in part on a second indication by the parallel evaluation that communication with the target is permitted. In some examples, the parallel evaluation of multiple rules is to evaluate one or more of: a permitted sender Internet Protocol (IP) address range, a permitted destination IP address range, a permitted packet protocol, or a permitted egress port range.
Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.
H04L 47/765 - Admission control; Resource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions triggered by the end-points
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
Systems and methods described herein may relate to providing a dynamically configurable circuitry able to be programed using a microsector granularity. Furthermore, selective partial reconfiguration operations may be performed use write operations to write a new configuration over existing configurations to selectively reprogram a portion of programmable logic. An n-bit data register (e.g., a 1-bit data register) and/or control circuitry receiving data and commands from an access register disposed between portions of programmable logic may enable at least some of the operations described.
Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
67.
CONDUCTIVE MEMORY MODULE NOTCH AND CONNECTOR-TO-MOTHERBOARD PINS FOR POWER OR GROUND
Apparatus and methods for conductive memory module notch and connector-to-motherboard pins for power or ground. A memory module includes a conductive notch that is coupled to either one or more ground planes in respective layers in the memory module's PCB or to a power rail formed on one or more layers in the PCB. A memory module connector includes a notch pin that is configured to mate with the conductive notch when the memory module is installed in the connector. The connector is mounted to a motherboard or the like and the notch pin is coupled to either power (e.g., Vin) or ground in the motherboard. When coupled to power, Vin is supplied to the memory module via the notch pin/conductive notch. When coupled to ground on the motherboard, at least a portion of the ground planes in the PCB are coupled to ground via the notch pin/conductive notch.
An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
Various embodiments herein provide a switched capacitor voltage converter with a subset of one or more phases that selectively provide a decoupling capacitance. The voltage converter may include multiple phases coupled in parallel between an input terminal and an output terminal. The individual phases may include a capacitor and a set of switches. A first subset of one or more of the phases may operate in a switching mode in which the respective set of switches open and close to generate an output voltage at the output terminal based on an input voltage at the input terminal. The voltage converter may further include a second subset of one or more phases that are selectively operable in the switching mode or in a decoupling mode. In the decoupling mode, the switches of the respective phase may maintain the capacitor coupled between the output terminal and ground. Other embodiments may be described and claimed.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
70.
ON-CHIP PHASE NOISE MEASUREMENT SYSTEM FOR BUILD-IN SELF-TEST OF MULTIPLE HIGH-FREQUENCY OSCILLATOR SYSTEMS
A non-transitory computer readable medium having instructions stored therein that when executed by a processor cause the processor to: determine a time difference between a first reference point of a first signal and a second reference point of a second signal, the first signal modulated with a first frequency, and the second signal modulated with a second frequency different from the first frequency; to determine a phase noise based on the determined time difference; and to use the determined phase noise for processing a signal associated with the first signal.
G01S 13/34 - Systems for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
71.
Through-Hole Structures for Improved Power Performance
The present disclosure is directed to a package substrate having surface layers with a power region for coupling with a semiconductor device, base layers of the package substrate, and a plurality of through hole vias providing direct couplings between the surface layers with the base layers, for which the surface layers and the base layer are provided with micro vias and the plurality of through hole vias are located below the power region of the surface layer. In an aspect, the package substrate includes a first and second plurality of plane layers, for which the first and second plurality of plane layers are without micro vias.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
72.
SURFACE FINISHES FOR CONTACTS AND FIDUCIAL MARKERS ON INTEGRATED CIRCUIT PACKAGE SUBSTRATES AND ASSOCIATED METHODS
Surface finishes for contacts and fiducial marks on integrated circuit package substrates and associated methods are disclosed. An example integrated circuit (IC) package substrate includes a first solder resist layer; a second solder resist layer opposite the first solder resist layer; and a fiducial marker including tin in an opening in the first solder resist layer.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
Methods and apparatus are disclosed for implementing capacitors in semiconductor devices. An example semiconductor die includes a first dielectric material disposed between a first metal interconnect and a second metal interconnect; and a capacitor positioned within a via extending through the first dielectric material between the first and second metal interconnects, the capacitor including a second dielectric material disposed in the via between the first and second metal interconnects.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Systems, apparatus, articles of manufacture, and methods are disclosed for deploying feet and/or including hinge gaskets to improve thermal solutions and/or acoustic experience with electronic devices. An example electronic device includes a first panel; a second panel; a hinge coupling the first panel and the second panel; a foot coupled to the second panel, the foot movable between a deployed position and a retracted position; a sensor to detect a position of the first panel; and programmable circuitry to execute instructions to cause the foot to be moved between the deployed position and the retracted position based on the position of the first panel.
Various examples relate to a control apparatus, a control device, a method, and a computer program for managing repair of a memory circuitry, and to a corresponding computing device. The control apparatus comprises processing circuitry configured to determine a score of a memory failure probability of at least one memory cell of the memory circuitry and trigger a repair procedure of the at least one memory cell of the memory circuitry when the score reaches a threshold.
Methods, apparatus, systems, and articles of manufacture are disclosed for data collection balancing for sustainable storage. An example apparatus includes at least one memory, machine executable instructions, and processor circuitry to at least one of execute or instantiate the machine executable instructions to orchestrate resources in an edge environment based on data ingested from a data source, execute a machine learning model based on the data to generate outputs, the outputs including at least one of a first value representative of data criticality or a second value representative of data quality of the data, reduce resource requirements associated with the resources of the edge environment based on the outputs to effectuate green data management of the edge environment, and cause an operation at a node of the edge environment based on at least one of the data or the outputs, the node associated with the data.
Methods, apparatus, systems and articles of manufacture to control address space isolation in a virtual machine are disclosed. An example apparatus includes an address width adjustor to identify a memory width value corresponding to a guest memory associated with a virtual machine (VM), and generate an expanded emulated memory width value. The example apparatus also includes a memory mirror manager to generate a first guest physical address (GPA) range based on the memory width value, and generate a second GPA range based on the expanded emulated memory width value. The example apparatus also includes an EPT generator to generate root paging structures of a first type of EPT with respective addresses within the first GPA range, and generate root paging structures of a second type of EPT with respective addresses within (a) the first GPA range and (b) the second GPA range.
A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. Example instructions partition resources of the host system to allocate (a) first resources of the host system for a first virtual machine and (b) second resources of the host system for a second virtual machine, wherein the resources of the host system include memory resources and a trusted platform module, the first virtual machine to run a first guest operating system and the second virtual machine to run a second guest operating system, wherein the first guest operating system is to run in a first isolated environment, the second guest operating system is to run in a second isolated environment; implement a virtual trusted platform module to support encryption for the first virtual machine; and protect the first resources and the second resources from unauthorized access.
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 12/14 - Protection against unauthorised use of memory
G06F 21/53 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by executing in a restricted environment, e.g. sandbox or secure virtual machine
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
Some demonstrative aspects include radar apparatuses, devices, systems and methods. In one example, an apparatus may include a plurality of Transmit (Tx) antennas to transmit radar Tx signals, a plurality of Receive (Rx) antennas to receive radar Rx signals based on the Tx signals, and a processor to generate radar information based on the radar Rx signals. The apparatus may be implemented, for example, as part of a radar device, for example, as part of a vehicle including the radar device. In other aspects, the apparatus may include any other additional or alternative elements and/or may be implemented as part of any other device.
G01S 7/41 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisation; Target signature; Target cross-section
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
G01S 13/58 - Velocity or trajectory determination systems; Sense-of-movement determination systems
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
G01S 13/95 - Radar or analogous systems, specially adapted for specific applications for meteorological use
A computing platform is disclosed. The computing platform includes a first computer system comprising a first graphics processing unit (GPU), a network coupled to the first computer system and a second computer system, coupled to the first computer system via the network, comprising a second GPU, wherein the first and second computer system are configured to perform distributed processing of graphics workloads between the first GPU and the second GPU.
A server is provided. The server comprises one or more interfaces configured to communicate with a client and processing circuitry configured to control the one or more interfaces and to transmit an interrupt to the client informing the client about an operation state of the server.
An example of an apparatus may include circuitry to monitor one or more sensors, determine a debug condition based on the monitored one or more sensors, and provide an indication of the debug condition. In some examples, the apparatus includes further circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition. Other examples are disclosed and claimed.
Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a first surface and a second surface opposite from the first surface. In an embodiment, pads are on the first surface of the package substrate, where the pads have a first width. In an embodiment, a layer is on the first surface of the package substrate, where the layer comprises wells through the layer, and where the wells have a second width that is wider than the first width. In an embodiment, a liquid metal is in the wells and in contact with the pads.
H01R 3/08 - Electrically-conductive connections not otherwise provided for for making connection to a liquid
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 3/32 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
84.
APPARATUS AND SYSTEM OF ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING
For example, an apparatus may include an Electromagnetic Interference (EMI) shield, which may be configured to provide EMI shielding for electronic circuitry on a Printed Circuit Board (PCB). For example, the EMI shield may be configured to include an EMI shield lid; and an EMI shield connector to electrically couple the EMI shield lid to at least one tube on the PCB to provide a ground to the EMI shield lid via the at least one tube. For example, the EMI shield connector may be configured to maintain the EMI shield lid over the electronic circuitry on the PCB.
Described herein are SRAM cells in which some transistors are implemented as thin film transistors (TFTs) while other transistors are implemented as non-TFTs (e.g., as FinFETs or nanoribbon-based transistors), where the TFTs are folded over non-TFTs to realize high-density 3D SRAM. For a given SRAM cell, either N-type transistors may be implemented as TFTs and stacked above P-type transistors that are implemented as non-TFTs, or P-type transistors may be implemented as TFTs and may be stacked above N-type transistors that are implemented as non-TFTs.
A universal drain pan that comprises a substantially flat base portion with four upright portions is provided. Along a plurality of the upright portions are installed threaded side drains. These side drains, which may be used or plugged as required in the field, are mounted just above the bottom face of the drain pan and incorporate a downward-facing slit to allow a pump to draw a maximum volume of water out of the pan.
Methods, apparatus, systems, and articles of manufacture are disclosed to estimate workload complexity. An example apparatus includes processor circuitry to perform at least one of first, second, or third operations to instantiate payload interface circuitry to extract workload objective information and service level agreement (SLA) criteria corresponding to a workload, and acceleration circuitry to select a pre-processing model based on (a) the workload objective information and (b) feedback corresponding to workload performance metrics of at least one prior workload execution iteration, execute the pre-processing model to calculate a complexity metric corresponding to the workload, and select candidate resources based on the complexity metric.
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
88.
SYSTEMS, APPARATUS, ARTICLES OF MANUFACTURE, AND METHODS FOR CROSS TRAINING AND COLLABORATIVE ARTIFICIAL INTELLIGENCE FOR PROACTIVE DATA MANAGEMENT AND ANALYTICS
Methods, apparatus, systems, and articles of manufacture are disclosed for proactive data management and analytics. An example apparatus includes at least one memory, instructions, and processor circuitry to at least one of execute or instantiate the instructions to identify nodes in a network environment, identify ones of the nodes as data subscribers, ingest data from data sources, execute a machine learning model on the data to generate an output, and perform an action based on the output.
G06F 16/901 - Indexing; Data structures therefor; Storage structures
G06F 16/908 - Retrieval characterised by using metadata, e.g. metadata not derived from the content or metadata generated manually using metadata automatically derived from the content
G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
89.
Concept for Segmenting an Application Buffer into Data Packets
An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.
An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.
An Infrastructure Processing Unit (IPU), including: a model optimization processor configured to optimize an artificial intelligence (AI) model for an accelerator managed by the IPU, and deploy the optimized AI model to the accelerator for execution of an inference; and a local memory configured to store data related to the AI model optimization.
Embodiments of the present disclosure are directed to a silicon photonics integrated apparatus that includes an input to receive an optical signal, a splitter optically coupled to the input to split the optical signal at a first path and a second path, a polarization beam splitter and rotator (PBSR) optically coupled with the first path or the second path, and a semiconductor optical amplifier (SOA) optically coupled with the first path or the second path and disposed between the splitter and the PBSR. Other embodiments may be described and/or claimed.
Embodiments described herein may be related to apparatuses, processes, and techniques related to coherent optical receivers, including coherent receivers with integrated all-silicon waveguide photodetectors and tunable local oscillators implemented within CMOS technology. Embodiments are also directed to tunable silicon hybrid lasers with integrated temperature sensors to control wavelength. Embodiments are also directed to post-process phase correction of optical hybrid and nested I/Q modulators. Embodiments are also directed to demultiplexing photodetectors based on multiple microrings. In embodiments, all components may be implements on a silicon substrate. Other embodiments may be described and/or claimed.
A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Methods, apparatus, systems and articles of manufacture to self-generate a multiple-output ensemble model defense against adversarial attacks are disclosed. An example apparatus includes a model acquirer to acquire the model, an exit point quantity identifier to determine a number of exit points to place in the model, an exit point selector to select exit points to be enabled in the model, and an exit output generator to generate an additional model structure to calculate an output at each respective exit point.
Embodiments are generally directed to a flexible overlapping display. An embodiment of a mobile device includes a processor to process data for the mobile device, a bendable and foldable display screen, one or more device sensors to sense an orientation of the mobile device, and one or more display sensors to sense a current arrangement of the display screen. The processor is to identify one or more portions of the display screen that are visible to a user based at least in part on data from the one or more device sensors and the one or more display sensors.
An apparatus and system for a unified transmission configuration indicator (TCI) state switch requirement are described. Both radio resource management and TCI state switch delay requirements are described. The UL TCI state switch delay requirement may depend on whether a downlink (DL) reference signal (RS) associated with the UL TCI state satisfies known conditions, as well as whether a joint or separate TCI mode is being used. In the separate TCI mode. the delay requirement may include timing between a DL data transmission and acknowledgement, and also include a time for receive beam refinement in frequency range2. In the joint TCI mode. the UL and DL TCI state switch delay requirement—due may be the same or may be the same as the separate TCI mode.
The present disclosure is directed to monitoring the integrity of the thermal interface material (TIM) of a semiconductor device directly by a monitoring component of a motherboard, a system on chip (SOC), or a remote device to measure either the electrical resistivity or capacitive property of the TIM, depending on the type of TIM being used, as a means to directly assess the thermal properties (conductivity, resistance, and/or impedance) of the TIM as it ages. In an aspect, the electrical resistivity or capacitive property of the TIM may be initially measured and charted, and thereafter, the changes in the electrical resistivity or capacitive property may be sensed by the monitoring component and, based on the delta of those changes, there may be remedial actions taken to mitigate impacts to the overall system performance and/or to prevent irreparable damage to the semiconductor device/system.
An apparatus to verify firmware in a computing system, comprising a non-volatile memory, including firmware memory to store agent firmware associated with each of a plurality of interconnect protocol (IP) agents and version memory to store security version numbers (SVNs) included in the agent firmware, a security controller comprising verifier logic to verify an integrity of the version memory by applying a hash algorithm to contents of the version memory to generate a SVN hash, and a trusted platform module (TPM) to store the SVN hash.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A light detection and ranging system is provided, which includes an output to output coherent laser light; an optical frequency discriminator configured to apply optical frequency discrimination to a portion of the coherent laser light to generate frequency discriminated laser light; and a processor configured to determine laser phase noise in the frequency discriminated laser light; to determine a laser phase noise compensation using the determined laser phase noise; and to apply the laser phase noise compensation to a received light signal corresponding to the output coherent laser light.
G01S 17/34 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
G01S 17/93 - Lidar systems, specially adapted for specific applications for anti-collision purposes
patents
