Intel Corporation

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1.

PIPELINING SERVICES IN NEXT-GENERATION CELLULAR NETWORKS

      
Application Number US2023076462
Publication Number 2024/081642
Status In Force
Filing Date 2023-10-10
Publication Date 2024-04-18
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Zongrui
  • Li, Qian
  • Tong, Xiaopeng
  • Stojanovski, Alexandre Saso
  • Luetzenkirchen, Thomas
  • Kolekar, Abhijeet
  • Palat, Sudeep
  • Bangolae, Sangeetha L.
  • Heo, Youn Hyoung

Abstract

This disclosure describes systems, methods, and devices related to pipelining services. A device may receive from a service consumer a request for pipeline service with service orchestration chaining function (SOCF), wherein the request comprises pipeline service context information. The device may generate requirements for the pipeline service based on the pipeline service context information. The device may select Computation, Communication, and Data Control Functions (CFs) instances for the pipeline service. The device may send a pipeline policy create request to a policy control function (PCF) when the PCF is responsible for generating policies related to the pipeline service including a pipeline ID. The device may receive a pipeline policy create response from the PCF indicating results of the pipeline ID and policy generation.

IPC Classes  ?

  • H04L 47/2483 - Traffic characterised by specific attributes, e.g. priority or QoS involving identification of individual flows
  • H04L 41/0894 - Policy-based network configuration management
  • H04L 41/342 - Signalling channels for network management communication between virtual entities, e.g. orchestrators, SDN or NFV entities
  • H04W 28/24 - Negotiating SLA [Service Level Agreement]; Negotiating QoS [Quality of Service]
  • H04L 61/4511 - Network directories; Name-to-address mapping using standardised directory access protocols using domain name system [DNS]

2.

SEQUENTIAL MODELING WITH MEMORY INCLUDING MULTI-RANGE ARRAYS

      
Application Number CN2022124510
Publication Number 2024/077463
Status In Force
Filing Date 2022-10-11
Publication Date 2024-04-18
Owner INTEL CORPORATION (USA)
Inventor
  • Guo, Ping
  • Yao, Anbang
  • Wu, Xiangbin
  • Wu, Yufei
  • Lai, Mee Sim

Abstract

A system for video segmentation may include a neural network and a memory including multi-range arrays. The multi-range arrays may store feature map arrays including different number of feature maps. The system may generate a feature map from a frame in a video at a time and store the feature map in the memory. The feature map may be in a feature map array that also includes one or more contextual feature maps generated from other frames in the video. The system uses the feature map array to determine whether the frame falls into a segment of the video. The system may generate a new feature map later from another frame and include the new feature map in a new feature map array that also includes the first feature map. The system uses the new feature map array to determine whether the new frame falls into a segment.

IPC Classes  ?

3.

ENHANCED CONFIGURATION OF CHANNEL SOUNDING SIGNAL FOR BANDWIDTH STITCHING FOR WIRLESS DEVICE POSITIONING

      
Application Number US2023076074
Publication Number 2024/081537
Status In Force
Filing Date 2023-10-05
Publication Date 2024-04-18
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Guotong
  • Xiong, Gang
  • Chatterjee, Debdeep
  • Lee, Jihyun

Abstract

This disclosure describes systems, methods, and devices for configuring sounding reference signal resources across multiple frequency locations for device positioning. A device may encode for transmission a sounding reference signal (SRS) including a first set of SRS resources for a first transmission by a user equipment (UE) device to the node B network device at a first time and a second set of SRS resources for a second transmission by the UE device to the node B network device at a second time; decode the first transmission received from the UE device using the first set and a first bandwidth at the first time; decode the second transmission received from the UE device using the second set and a second bandwidth at the second time; and combine the first transmission and the second transmission for a device positioning estimation based on the first bandwidth and the second bandwidth.

IPC Classes  ?

  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/04 - Wireless resource allocation
  • H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network

4.

EDGE-NATIVE MANAGEMENT SYSTEM OF EDGE APPLICATIONS

      
Application Number US2023034948
Publication Number 2024/081317
Status In Force
Filing Date 2023-10-11
Publication Date 2024-04-18
Owner INTEL CORPORATION (USA)
Inventor
  • Filippou, Miltiadis
  • Sabella, Dario

Abstract

Various approaches of an edge-native management system, including a session management function application for configuration of edge applications and network traffic functions, are disclosed. An example method for configuration of an edge computing application, performed by a session management function application, includes: receiving network information from an edge computing platform (e.g., MEC platform) that includes an edge computing application (e.g., MEC App), with the network information being received via a network experience function (NEF) of a mobile network (e.g., 3GPP 5G network); transmitting a request to the edge computing platform, based on the received network information, the request including an application data traffic configuration action to perform on the edge computing application; and receiving a response to the request from the edge computing platform, with the response indicating a status of the application data traffic configuration action performed on the edge computing application.

IPC Classes  ?

  • H04L 67/61 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources taking into account QoS or priority requirements
  • H04L 67/10 - Protocols in which an application is distributed across nodes in the network
  • G06F 9/451 - Execution arrangements for user interfaces
  • H04W 88/14 - Backbone network devices

5.

DATA COLLECTION COORDINATION FUNCTION AND NETWORK DATA ANALYTICS FUNCTION FRAMEWORK FOR SENSING SERVICES IN NEXT GENERATION CELLULAR NETWORKS

      
Application Number US2023075158
Publication Number 2024/076852
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-11
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Zongrui
  • Li, Qian
  • Kedalagudde, Meghashree Dattatri
  • Stojanovski, Alexandre Saso
  • Hamidi-Sepehr, Fatemeh
  • Hewavithana, Thushara
  • Luetzenkirchen, Thomas
  • Kolekar, Abhijeet
  • Palat, Sudeep
  • Heo, Youn Hyoung
  • Bangolae, Sangeetha

Abstract

This disclosure describes systems, methods, and devices related to sensing service coordination. A device may discover a Network Data Analytics Function (NWDAF) via a Network Function Repository Function (NRF). The device may send an Analytics request or subscribe to the selected NWDAF with a criteria based on a sensing data analytics ID, event ID, and event parameters. The device may select a Data Collection Coordination Function (DCCF) instance when DCCF is used for data collection, based on DCCF Serving Area Information. The device may receive sensing data or data analytics from the NWDAF after NWDAF has processed the data collected from DCCF.

IPC Classes  ?

  • H04W 24/02 - Arrangements for optimising operational condition
  • H04L 41/14 - Network analysis or design

6.

METHODS AND ARRANGEMENTS FOR NETWORK-BASED SENSING

      
Application Number US2023034243
Publication Number 2024/076513
Status In Force
Filing Date 2023-09-30
Publication Date 2024-04-11
Owner INTEL CORPORATION (USA)
Inventor
  • Stojanovski, Alexandre Saso
  • Ding, Zongrui
  • Hamidi-Sepehr, Fatemeh
  • Li, Qian
  • Luetzenkirchen, Thomas
  • Palat, Sudeep
  • Kolekar, Abhijeet
  • Hewavithana, Thushara

Abstract

Logic may parse an application function (AF) request from an AF, the AF request comprising a first set of parameters, the first set of parameters comprising a first geographical area and a sensing type. Logic may identify a radio access network (RAN) node based on the first geographical area. Logic may send a sensing request to the RAN node, the sensing request comprising a second set of parameters to identify sensing information, the second set of parameters comprising a second geographical area and a sensing type. Logic may receive a sensing result from the RAN node based on the second set of parameters. And logic may process the sensing result based on the AF request to determine a sensing report; and send, to the AF, the sensing report via the network interface.

IPC Classes  ?

  • H04W 24/08 - Testing using real traffic
  • H04W 24/10 - Scheduling measurement reports
  • H04W 4/38 - Services specially adapted for particular environments, situations or purposes for collecting sensor information
  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • G01W 1/14 - Rainfall or precipitation gauges
  • G01N 15/00 - Investigating characteristics of particles; Investigating permeability, pore-volume or surface-area of porous materials

7.

PACKAGE ARCHITECTURE WITH DIE-TO-DIE COUPLING USING GLASS INTERPOSER

      
Application Number US2023071581
Publication Number 2024/076799
Status In Force
Filing Date 2023-08-03
Publication Date 2024-04-11
Owner INTEL CORPORATION (USA)
Inventor
  • Marin, Brandon C.
  • Duan, Gang
  • Ecton, Jeremy
  • Nad, Suddhasattwa
  • Pietambaram, Srinivas V.

Abstract

Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/66 - High-frequency adaptations
  • H01L 23/15 - Ceramic or glass substrates
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

8.

COMMUNICATION OF MEDIA CONFIGURATION INFORMATION OVER A SERIAL COMMUNICATION INTERFACE

      
Application Number US2023074165
Publication Number 2024/076823
Status In Force
Filing Date 2023-09-14
Publication Date 2024-04-11
Owner INTEL CORPORATION (USA)
Inventor
  • Lusted, Kent C.
  • Shah, Nishant S.

Abstract

A host device comprising first circuitry to receive one or more packets sent by a communication device over a serial communication interface between the communication device and the host device, wherein the one or more packets comprise media configuration information stored in a memory of the communication device and an indication of a mapping of the memory of the communication device; and second circuitry to transmit data packets over the serial communication interface after the host device has been configured based on the media configuration information.

IPC Classes  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

9.

DISTRIBUTED ADDRESS TRANSLATION SERVICES

      
Application Number CN2022123674
Publication Number 2024/073864
Status In Force
Filing Date 2022-10-02
Publication Date 2024-04-11
Owner INTEL CORPORATION (USA)
Inventor
  • He, Shaopeng
  • Jain, Anjali Singhai
  • Li, Yadong
  • Ben-Shahar, Israel
  • Vakharwala, Rupin H.
  • Tian, Kun
  • Nagabhushana, Rashmi Hanagal
  • Sawula, Andrzej
  • Pawlowski, Bartosz
  • Burres, Brad A.

Abstract

A computing system including two or more processing units shares virtual memory for a program between the two or more processing units. Each of the processing units may include memory management circuitry to manage a respective page table corresponding to the virtual memory. A first portion of the addresses of the virtual address space of the program are mapped to addresses of physical memory associated with a first one of the two or more processing units, while a second portion of the addresses of the virtual address space are mapped to addresses in physical memory associated with a second one of the two or more processing units.

IPC Classes  ?

  • G06F 12/14 - Protection against unauthorised use of memory

10.

SCALABLE COHERENT PHOTONIC INTEGRATED CIRCUIT (PIC) ARCHITECTURE

      
Application Number US2023032208
Publication Number 2024/076443
Status In Force
Filing Date 2023-09-07
Publication Date 2024-04-11
Owner INTEL CORPORATION (USA)
Inventor
  • Gilardi, Giovanni
  • Yu, Haijiang
  • Liu, Ansheng
  • Zhu, Xiaoxing
  • Akulova, Yuliya
  • Narayan, Raghuram
  • Doussiere, Pierre
  • Malouin, Christian
  • Dosunmu, Olufemi

Abstract

Embodiments herein relate to a photonic integrated circuit (PIC). The PIC may include a transmit module and a receive module. An optical port of the PIC may be coupled to the transmit module or the receive module. A semiconductor optical amplifier (SOA) may be positioned in a signal pathway between the optical port and the transmit module or the receive module. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers
  • H01S 5/50 - Amplifier structures not provided for in groups

11.

GLASS RECIRCULATOR FOR OPTICAL SIGNAL REROUTING ACROSS PHOTONIC INTEGRATED CIRCUITS

      
Application Number US2023070364
Publication Number 2024/073163
Status In Force
Filing Date 2023-07-18
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Duong, Benjamin T.
  • Darmawikarta, Kristof Kuwawi
  • Pietambaram, Srinivas V.
  • Gaan, Sandeep

Abstract

Various embodiments disclosed relate to routing optical signals from silicon photonics, such as a photonic integrated circuit. The present disclosure includes a glass recirculatory layer with waveguides at varying heights to allow re-routing of such optical signals from silicon photonics, such as a photonic integrated circuit. Re-routing of optical signals can be accomplished in the glass recirculatory layer with reduced losses due to reduced intersections of waveguides therein.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

12.

APPARATUS AND METHOD USED IN WLANS

      
Application Number CN2022122103
Publication Number 2024/065265
Status In Force
Filing Date 2022-09-28
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Qinghua
  • Chen, Xiaogang
  • Lin, Xintian
  • Zhu, Yuan
  • Gurevitz, Assaf
  • Song, Hao

Abstract

The application relates to an apparatus and method used in Wireless Local Area Networks (WLANs). The apparatus includes: a Radio Frequency (RF) interface; and processor circuitry coupled with the RF interface and configured to: generate a transmission signal sequence by performing Cyclic Shift Diversity (CSD) operation and phase rotation on a base signal sequence; and provide the transmission signal sequence to the RF interface for transmitting in a duplicate transmission mode on different sub-channels.

IPC Classes  ?

13.

ORTHOGONAL PHASE MODULATION LIDAR

      
Application Number CN2022122452
Publication Number 2024/065359
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Fei
  • Liu, Ling
  • Wu, Xiangbin
  • Yao, Anbang
  • Zhang, Lidan

Abstract

An apparatus(100), including an electro‐optical modulating means for phase modulating a light signal(S1) with a range measurement code and a light beam isolation code; an electro‐optical detecting means for receiving a reflected light signal(R) of the phase modulated light signal reflected by an object and converting the received reflected light signal(R) into an electronic data signal(D); and a processor means for correlating the electronic data signal(D) with the light beam isolation code and the range measurement code to obtain a range to the object.

IPC Classes  ?

  • G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar

14.

METHODS, SYSTEMS, ARTICLES OF MANUFACTURE AND APPARATUS TO SYNCHRONIZE TASKS

      
Application Number CN2022122691
Publication Number 2024/065415
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Zhigang
  • Wang, Hai Tao
  • Shen, Yingzhe

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to synchronize tasks. An example apparatus to synchronize tasks includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to identify a first task frequency associated with a first task, the first task executed by the computing device, the first task outputting first data at first times, identify a second task frequency associated with a second task, the second task executed by the computing device, the second task outputting second data at second times, when the second task frequency is different from the first task frequency, calculate a first difference between the second task frequency and the first task frequency, and adjust at least one of the first task frequency or the second task frequency based on the first difference such that the second times match the first times.

IPC Classes  ?

15.

LOW-COMPLEXITY ENHANCMENT VIDEO CODING USING TILE-LEVEL QUANTIZATION PARAMETERS

      
Application Number CN2022122818
Publication Number 2024/065464
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Zhou, Huijuan
  • Li, Jing
  • Jiang, Renzhi
  • Wang, Yi
  • Wang, Chenchen

Abstract

This disclosure describes systems, methods, and devices related to decoding low-complexity enhancement video coding (LCEVC) video data. A device may receive a bitstream including a first layer and enhancement layers; decode a video frame of the first layer of the bitstream using a base decoder; up-sample the decoded video frame; decode the video frame of a first enhancement layer using tile-level quantization parameters; generate a first combined intermediate video frame using the up-sampled video frame and the decoded video data of the first enhancement layer; up-sample the first combined intermediate video frame; decode encoded video data of a second enhancement layer; generate a second combined intermediate video frame using the decoded video data of the second enhancement layer and a selected reference frame; and generate a combined output video frame using the first combined intermediate video frame and the second combined intermediate video frame.

IPC Classes  ?

  • H04N 19/33 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the spatial domain

16.

EVALUATION AND MITIGATION OF SOFT-ERRORS IN PARALLEL AND DISTRIBUTED TRAINING AND INFERENCE OF TRANSFORMERS

      
Application Number CN2022123553
Publication Number 2024/065794
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Yakai
  • Wu, Keqiang
  • Zhang, Jian

Abstract

The application provides an apparatus, method, and storage medium for evaluation and mitigation of soft-errors in parallel and distributed training and inference of transformers. The apparatus includes two or more processing units (220) capable to communicate with each other and operating collectively as a transformer for deep learning. Each processing unit (220) is configured to perform a matrix multiplication on a first matrix with a first column summation vector added after a last row of the first matrix and a first parameter matrix with a first row summation vector added after a last column of the first parameter matrix, to obtain a second matrix; perform an all-reduce operation on second matrices obtained by the two or more processing units (220) to obtain a third matrix; and determine whether a soft error has occurred by performing a checksum verification on the third matrix.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 17/16 - Matrix or vector computation
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

17.

VEHICLE PASSENGER DISPLAY MODIFICATION

      
Application Number CN2022123563
Publication Number 2024/065799
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Buerkle, Cornelius
  • Guo, Ping
  • Lai, Mee Sim
  • Lee, Meng Siong
  • Lee, Kuan Heng
  • Oboril, Fabian
  • Pasch, Frederik
  • Tan, Say Chuan
  • Yeap, Wei Seng
  • Yew, Chien Chern

Abstract

An apparatus, including: an interface configured to receive image data in real-time of a surroundings of a vehicle; processing circuitry configured to: identify a point of interest within the received image data; generate modified image data based on the received image data and the identified point of interest; and transmit the modified image data to be displayed to a vehicle passenger.

IPC Classes  ?

  • B60R 1/00 - Optical viewing arrangements; Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles
  • B60J 3/04 - Antiglare equipment associated with windows or windscreens; Sun visors for vehicles adjustable in transparency
  • B61L 27/04 - Automatic systems, e.g. controlled by train; Change-over to manual control

18.

ACCELERATE DEEP LEARNING WITH INTER-ITERATION SCHEDULING

      
Application Number CN2022123615
Publication Number 2024/065826
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Zhang, Liangang
  • Ma, Guokai
  • Gong, Jiong
  • Zhao, Fan

Abstract

An apparatus relates to accelerate deep learning with inter-iteration scheduling based on operation categorization associated with the deep learning. The apparatus includes interface circuitry (1120), programmable circuitry; and instructions to cause the programmable circuitry to: classify a group of operations of a distributed deep learning workload based on a resource utilization of the group of operations; select at least two operations of the group of operations for overlapped execution based on the classification and a dependency analysis of the at least two operations of the group of operations; and perform a distributed training of the distributed deep learning workload based on an execution schedule that includes overlapped execution of the selected at least two operations.

IPC Classes  ?

19.

IMMERSION COOLING SYSTEMS, APPARATUS, AND RELATED METHODS

      
Application Number CN2022123650
Publication Number 2024/065847
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Birch, Thomas
  • Chuang, Jimmy
  • Fan, Yuehong
  • He, Jing-Hua John
  • Mcafee, Eric
  • Sarangi, Suchismita
  • Shia, David
  • Tien, Ming
  • Wang, Chuanlou
  • Wei, Peng
  • Winkel, Casey
  • Wondimu, Berhanu
  • Wu, Dong-Han
  • Wu, Jay
  • Zhou, Shaorong

Abstract

Immersion cooling systems, apparatus, and related methods for cooling electronic computing platforms and/or associated electronic components are disclosed herein. An immersion cooling chassis includes a first face, a second face opposite the first face, a third face disposed between the first face and the second face, the third face perpendicular to the first face, a fourth face disposed between the first face and the second face, the fourth face perpendicular to the first face and opposite the third face, and a first portion to be cooled via a first convection of a coolant fluid, the first portion including a coolant inlet defined in the third face, and a coolant outlet defined in the first face, and a second portion to be cooled via a second convection of air, the second portion including an air inlet defined in the first face between the fourth face and the coolant outlet.

IPC Classes  ?

  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

20.

BLOCK NORMALIZED ADDER WITH FOUR-DEEP SYSTOLIC PARAMETER SUPPORT

      
Application Number CN2022123669
Publication Number 2024/065859
Status In Force
Filing Date 2022-10-01
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Chen, Jiasheng
  • Parra, Jorge
  • Drane, Theo
  • Zorn, William
  • Hurd, Kevin
  • Heinecke, Alexander
  • Hickmann, Brian
  • Hadj-Chaib, Alexandre
  • Taylor, Elliot
  • Wu, Shifu
  • Mu, Shuai
  • Avancha, Sasikanth
  • Mellempudi, Naveen
  • Qi, Yue
  • He, Bin

Abstract

An apparatus to facilitate a block normalized adder (BNA) with four-deep systolic parameter support is disclosed. The apparatus includes matrix acceleration hardware comprising: data processing units, wherein the respective data processing units comprise normalization adding circuitry including: multiplier circuits; shifters to receive multiplier outputs from the multiplier circuits and apply block normalization; and an accumulator circuit to accumulate shifter outputs from the shifters with an intermediate value, wherein the accumulator circuit to generate an accumulator output in a high precision and unnormalized format to pass to a next stage of the matrix acceleration hardware; a bypass data structure to cause a global source operand to bypass the data processing units; and an adder circuit to add the accumulator output from a final data processing unit of the data processing units with the global source operand and apply round to nearest even to generate a final output.

IPC Classes  ?

  • G06F 17/16 - Matrix or vector computation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

21.

HARDWARE SUPPORT FOR N-DIMENSIONAL MATRIX LOAD AND STORE INSTRUCTIONS

      
Application Number CN2022123670
Publication Number 2024/065860
Status In Force
Filing Date 2022-10-01
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Fu, Fangwen
  • George, Biju
  • Ganapathy, Sabareesh
  • Xiong, Wei
  • Wu, Chengxi
  • Wiegert, John
  • Ray, Joydeep

Abstract

An apparatus to facilitate hardware support for n-dimensional matrix load and store instructions is disclosed. The apparatus includes a graphics processor comprising a general-purpose graphics execution resources, the general-purpose graphics execution resources including a matrix accelerator, the matrix accelerator configured to perform a matrix operation on a plurality of tensors stored in a memory; and circuitry configured to facilitate access to the memory by the general-purpose graphics execution resources, wherein the circuitry is configured to: receive a request to access a tensor of the plurality of tensors; and generate a n-dimensional block access message along a dimension of n >2 of the tensor, the n-dimensional block access message to enable access to the tensor by the matrix accelerator, wherein the n-dimensional block access message comprises an application programming interface (API) descriptor defining a tensor width, tensor pitch, tensor block offset, and a tensor block size of the tensor.

IPC Classes  ?

22.

PORT SELECTION FOR HARDWARE QUEUING MANAGEMENT DEVICE

      
Application Number US2022044811
Publication Number 2024/072374
Status In Force
Filing Date 2022-09-27
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Kumar, Pushpendra
  • Misra, Amruta
  • Mcdonnell, Niall
  • Arulambalam, Ambalavanar
  • Chen, Ximing
  • Beatty, Paul
  • Pathak, Pravin

Abstract

In an embodiment, a processor may include multiple processing engines and multiple hardware queue manager (HQM) devices. Each HQM device is to queue data requests for a different subset of the plurality of processing engines. At least one processing engine is to execute a first set of instructions to: detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices; in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device; and transmit the first enqueue instruction using the recommended port for the first HQM device.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
  • G06F 9/4401 - Bootstrapping
  • G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit

23.

ENHANCED WI-FI HIGH-BANDWIDTH SIGNALING DESIGN

      
Application Number US2022045281
Publication Number 2024/072397
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Huang, Po-Kai
  • Li, Qinghua
  • Stacey, Robert

Abstract

This disclosure describes systems, methods, and devices related to higher bandwidth channelization signaling in Wi-Fi. An access point may determine a channel consisting of a contiguous 240 MHz in a 5 GHz bandwidth or contiguous 480 MHz in a 6 GHz bandwidth for use by a basic service set of one or more station devices; generate a frame comprising an indication of the channel; and transmit the frame to the one or more station devices of the basic service set.

IPC Classes  ?

  • H04W 28/20 - Negotiating bandwidth
  • H04W 72/04 - Wireless resource allocation
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

24.

APPARATUS, SYSTEM, AND METHOD OF COMMUNICATION DURING A SYNCHRONIZED TRANSMIT OPPORTUNITY (S-TXOP)

      
Application Number US2022045297
Publication Number 2024/072400
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Azizi, Shahrnaz
  • Friedman, Avishay
  • Vituri, Shlomi
  • Gurevitz, Assaf
  • Kenney, Thomas J.

Abstract

For example, an Access Point (AP) may be configured to transmit a Synchronized Transmit Opportunity (S-TxOP) trigger to initiate an S-TxOP. For example, the S-TxOP may include a plurality of transmission slots synchronized based on the S-TxOP trigger, wherein the plurality of transmission slots may be configured for communication between the AP and one or more scheduled wireless communication stations (STAs). For example, a transmission slot of the plurality of transmission slots may include one or more blanked Orthogonal-Frequency-Division-Multiplexing (OFDM) symbols at an end of the transmission slot. For example, the one or more blanked OFDM symbols may be reserved for time-sensitive communications. For example, the AP may be configured to communicate a time-sensitive transmission with a time-sensitive STA during at least one blanked OFDM symbol of the one or more blanked OFDM symbols.

IPC Classes  ?

  • H04W 72/12 - Wireless traffic scheduling
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/04 - Wireless resource allocation
  • H04J 13/00 - Code division multiplex systems

25.

ADD BLOCK ACKNOWLEDGMENT DURING FAST BASIC SERVICE SET TRANSITION

      
Application Number US2022045457
Publication Number 2024/072416
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Cariou, Laurent
  • Fang, Juan

Abstract

This disclosure describes systems, methods, and devices related to enhanced fast BSS transition. A device may determine a need to transition to a target access point (AP) from a current AP. The device may send an authentication request frame to be sent to the target AP to perform a fast basic service set (BSS) transition (FT). The device may identify an authentication response frame received from the target AP comprising an add block acknowledgment (ADDBA) element. The device may establish a session and data transmission with the target AP.

IPC Classes  ?

  • H04W 48/20 - Selecting an access point
  • H04W 76/10 - Connection setup
  • H04W 12/06 - Authentication
  • H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
  • H04W 84/12 - WLAN [Wireless Local Area Networks]
  • H04W 88/18 - Service support devices; Network management devices

26.

A SYSTEM FOR ACCESSING MULTIPLE PRIMARY CHANNELS IN A WIRELESS MEDIUM

      
Application Number US2022045458
Publication Number 2024/072417
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Park, Minyoung
  • Cariou, Laurent
  • Fang, Juan

Abstract

This disclosure describes a system for accessing multiple primary channels in a wireless medium. A device may cause to send a beacon frame to one or more wireless stations (STA(s)), wherein the beacon frame comprises a notification of two or more primary channels at an access point (AP). The device may receive a first physical layer protocol data unit (PPDU) from a first STA of the one or more STAs. The device may select a first primary channel of the two or more primary channels, wherein the first primary channel is idle. The device may cause to transmit the first PPDU from the first STA on the first primary channel.

IPC Classes  ?

  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 74/00 - Wireless channel access, e.g. scheduled or random access
  • H04W 48/18 - Selecting a network or a communication service

27.

UNLICENSED NATIONAL INFORMATION INFRASTRUCTURE 4 (UNII4) DISCOVERY OPERATION

      
Application Number US2022045462
Publication Number 2024/072419
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Cariou, Laurent
  • Kenney, Thomas J.

Abstract

This disclosure describes systems, methods, and devices related to an unlicensed national information infrastructure 4 (UNII4) discovery. A device may identify a UNII4 discovery request received from a station device (STA) by a first AP of the AP MLD. The device may send the UNII4 discovery request from the first AP to a second AP of the AP MLD, wherein the second AP is capable of operating on a UNII4 frequency band. The device may send a discovery response to the discovery request from the second AP to the STA. The device may establish a first link in a multi-link operation between the second AP and the STA.

IPC Classes  ?

  • H04W 48/16 - Discovering; Processing access restriction or access information
  • H04W 48/08 - Access restriction or access information delivery, e.g. discovery data delivery
  • H04W 76/15 - Setup of multiple wireless link connections
  • H04W 72/04 - Wireless resource allocation

28.

GRADIENT-FREE EFFICIENT CLASS ACTIVATION MAP GENERATION

      
Application Number US2022080818
Publication Number 2024/072472
Status In Force
Filing Date 2022-12-02
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Byun, Seok-Yong
  • Lee, Wonju

Abstract

A class activation map (CAM) network generates a saliency map for a particular class of a multi-class classifier used for classifying images. The saliency map for a class highlights pixels in the image where the classifier focuses on when identifying objects of the class in the image. The CAM network described herein generates a feature map based on an input image using a first convolutional neural network (CNN) and applies a set of spatial masks to the feature map to generate a set of masked feature maps. A second CNN processes the set of masked feature maps to determine probabilities that different portions of the image correspond to particular classes. These probabilities are used to create the saliency map.

IPC Classes  ?

29.

HIGH-DENSITY SOCKET CONNECTORS

      
Application Number CN2022121431
Publication Number 2024/065104
Status In Force
Filing Date 2022-09-26
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Du, Lianchang
  • Smalley, Jeffory
  • Nekkanty, Srikant
  • Zhang, Zhichao
  • Zeng, Yi
  • Zhang, Xinjun
  • Yin, Maoxin

Abstract

High-density socket connectors are disclosed herein. An example socket connector includes a first housing to be coupled to a substrate, The first housing has a first side, a second side opposite the first side, and a first opening extending through the first housing between the first side and the second side. The socket connector includes a socket pin disposed in the first opening. The socket connector further includes a second housing moveably coupled to the first housing. The second housing has a third side, a fourth side opposite the third side, and a second opening extending through the second housing between the third side and the fourth side. The socket pin extends into the second opening of the second housing. The second housing is moveable relative to the first housing between a first position and a second position.

IPC Classes  ?

  • H01R 13/10 - Sockets for co-operation with pins or blades

30.

METHODS AND APPARATUS TO MANUFACTURE COUPLED INDUCTOR 

      
Application Number CN2022122564
Publication Number 2024/065390
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Liang, Xiaoguo
  • Abou-Alfotouh, Ahmed
  • Wu, Alan
  • Radhakrishnan, Kaladhar
  • Douglas, Jonathan
  • Dai, Wei

Abstract

Methods and apparatus to manufacture a coupled inductor are disclosed. An example coupled inductor includes a base of a magnetic core including a first channel and a second channel extending between first and second sides of the base, the first channel spaced apart from the second channel, a third channel of the base extending transverse to the first and second channels, a first conductive wire positioned in the base, a first portion of the first conductive wire positioned in the first channel, a second portion of the first conductive wire positioned in the second channel, a third portion of the first conductive wire positioned in the third channel, and a first portion of a second conductive wire positioned in the first channel, a second portion of the conductive wire positioned in the second channel, a third portion of the second conductive wire positioned in the third channel.

IPC Classes  ?

  • H01F 17/04 - Fixed inductances of the signal type with magnetic core
  • H01F 27/30 - Fastening or clamping coils, windings, or parts thereof together; Fastening or mounting coils or windings on core, casing, or other support

31.

ENHANCED IMAGE SLICE RECONSTRUCTION FOR VIDEO STREAMS

      
Application Number CN2022122800
Publication Number 2024/065451
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner
  • INTEL CORPORATION (USA)
  • DIAZ, Raul (USA)
  • TRIGUI, Tahani (Canada)
Inventor
  • Wang, Yi
  • Du, Jianxin
  • Yu, Ping
  • Chen, Xiaomin
  • Li, Ming

Abstract

This disclosure describes systems, methods, and devices related to decoding JPEG XS video data. A device may identify a bitstream received from a device, the bitstream encoded using JPEG XS; determine that a first slice of a video frame of the bitstream is located within a region of interest of the video frame; determine that a second slice of the video frame is not located within a region of interest of the video frame; discard the second slice based on the determination that the second slice is not located within a region of interest of the video frame; apply an inverse wavelet transformation to the first slice based on the determination that the first slice is located within a region of interest of the video frame; and generate a reconstructed video frame including the first slice and excluding the second slice.

IPC Classes  ?

  • H04N 19/52 - Processing of motion vectors by encoding by predictive encoding

32.

METHOD AND APPARATUS FOR OPTIMIZING DEEP LEARNING COMPUTATION GRAPH

      
Application Number CN2022122907
Publication Number 2024/065525
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Chen, Ciyong
  • Qin, Zhennan
  • Song, Yunfei
  • Ye, Jun

Abstract

Provided herein are apparatus and method for optimizing deep learning computation graph. The method includes obtaining a deep learning computation graph including compute-intensive operators and memory-intensive operators; fusing the memory-intensive operators into the compute-intensive operators to generate a new computation graph; dividing the new computation graph into sub-computation graphs; and fusing compute-intensive operators, in each of the sub-computation graphs, to generate an optimized computation graph. Other embodiments may also be disclosed and claimed.

IPC Classes  ?

33.

METHODS AND APPARATUS TO PERFORM ARTIFICIAL INTELLIGENCE-BASED SPARSE COMPUTATION BASED ON HYBRID PATTERN AND DYNAMIC ENCODING

      
Application Number CN2022122915
Publication Number 2024/065530
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Meng, Hengyu
  • Chang, Hanwen
  • Shen, Haihao

Abstract

Methods, apparatus, systems, and articles of manufacture to perform artificial intelligence-based sparse computation based on hybrid pattern and dynamic encoding are disclosed. An example apparatus includes memory, computer readable instructions, and processor circuitry to execute the computer readable instructions to: determine a hybrid sparse pattern of a selected layer of an artificial intelligence (AI) -based model, the hybrid sparse pattern having a sparsity ratio and a block pattern for the selected layer; in response to the sparsity ratio being above a threshold, reduce the sparsity ratio of the selected layer; and in response to the sparsity ratio being below the threshold, adjust the block pattern of the selected layer, the block pattern of the selected layer corresponding to an accuracy ratio.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • G06N 3/08 - Learning methods

34.

SERVER, END CLIENT, METHODS AND PROGRAM CODE

      
Application Number CN2022122923
Publication Number 2024/065531
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Tao, Jian
  • Liu, Fei

Abstract

A server is provided. The server comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions. The machine-readable instructions are executed to install or update the main base operation system on the server. Further, the machine-readable instructions are executed transmit, to the end client, end client data indicative of an end client operation system to be installed or updated on the end client. Further, the machine-readable instructions are executed to generate a main branch for main-taining the main base operation system and a subbranch for maintaining the end client opera-tion system.

IPC Classes  ?

35.

METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO GENERATE HARDWARE-AWARE MACHINE LEARNING MODEL ARCHITECTURES FOR MULTIPLE DOMAINS WITHOUT TRAINING

      
Application Number CN2022122927
Publication Number 2024/065535
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Zhang, Jian
  • Ding, Bin
  • Liu, Tianyi

Abstract

Disclosed is a technical solution to generate hardware-aware machine learning (ML) model architectures for multiple domains without training. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions. The example processor circuitry is to generate multiple candidate architectures for a ML model based on target hardware with which the ML model is to be executed and a search space corresponding to the multiple domains. Additionally, the example processor circuitry is to compute respective composite scores for the multiple candidate architectures, the respective composite scores based on respective latency scores for the multiple candidate architectures. The example processor circuitry is also to select an architecture for the ML model from the multiple candidate architectures for the ML model, the selected architecture corresponding to a composite score associated with the selected architecture that satisfies a criterion.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology

36.

METHODS AND APPARATUS FOR IMAGE SEGMENTATION ON SMALL DATASETS

      
Application Number CN2022122928
Publication Number 2024/065536
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Chen, Xin
  • Ding, Ke

Abstract

Methods, apparatus, and systems are disclosed for semantic image segmentation using small datasets. An example apparatus includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to identify a gradient vector flow associated with the input image, generate a spatial feature map based on pixels of the input image using a two-stream neural network architecture, generate a field feature map based on the gradient vector flow using the two-stream neural network architecture, fuse the spatial feature map and the field feature map, and output a segmented image of the input image based on the fused feature map.

IPC Classes  ?

37.

HIGH FIDELITY ATTESTATION-BASED ARTIFICIAL INTELLIGENCE INFERENCE SYSTEM

      
Application Number CN2022123602
Publication Number 2024/065816
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Zhu, Bing
  • Smith, Ned
  • Poornachandran, Rajesh
  • Yan, Shaopu
  • Huang, Yang

Abstract

A controller system is configured to organize a plurality of compute kernels to execute an instance of an artificial intelligence inference pipeline, each of the compute kernels executing on a respective plurality of processing platforms; access metadata of each of the plurality of processing platforms, the metadata describing attestation data of each of the plurality of processing platforms; transmit the metadata to an evaluator system, the evaluator system to evaluate the metadata to validate that the plurality of processing platforms are compliant with a service level agreement; receive reinforcement data, the reinforcement data used to adjust at least one of the plurality of processing platforms in a later execution of the instance of the artificial intelligence inference pipeline; and communicate with a processing platform of the plurality of processing platforms to adjust a sensor configuration or an artificial intelligence model used by the processing platform.

IPC Classes  ?

  • G06F 15/00 - Digital computers in general; Data processing equipment in general

38.

USER INTERRUPT MODERATION FOR USER INTER-PROCESSOR-INTERRUPTS

      
Application Number CN2022123618
Publication Number 2024/065829
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Xue, Zhan
  • Mehta, Sohil
  • Cui, Bo

Abstract

Methods and apparatus relating to techniques for user interrupt moderation of user Inter-Processor-Interrupts (IPIs) are described. In an embodiment, a processor executes a receiver process to process a user Inter-Processor Interrupt (IPI) from a sender process. A memory stores User Inter-Processor Interrupt Moderation Configuration (UIMC) data to be accessed by the receiver process. In response to a comparison of a number of invocations of the user IPI during a time interval and an interrupt throttle rate, it is determined whether to drop the user IPI. Other embodiments are also disclosed and claimed.

IPC Classes  ?

  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt

39.

IMPROVING ACCURACY OF MACHINE LEARNING OPERATIONS BY COMPENSATING FOR LOWER PRECISION WITH SCALE SHIFTING

      
Application Number CN2022123651
Publication Number 2024/065848
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • He, Pujiang
  • Doshi, Kshitij

Abstract

Disclosed is a technical solution for improving accuracy of operations of machine learning by compensating for lower precision with scale shifting. An example non-transitory computer readable medium comprises instructions that, when executed, cause a machine to at least identify a first precision data type and a second precision data type associated with execution of a machine-learning model, the first precision data type to have a first data precision greater than a second data precision of the second precision data type, determine at least one scale factor to be applied to first weights of the machine-learning model, the first weights based on the first precision data type, and convert the first weights to second weights based on a multiplication of the first weights and the at least one scale factor, the second weights based on the second precision data type.

IPC Classes  ?

40.

PROVIDING BYTECODE-LEVEL PARALLELISM IN A PROCESSOR USING CONCURRENT INTERVAL EXECUTION

      
Application Number CN2022123654
Publication Number 2024/065850
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Chen, Yuan
  • Sheffield, David B.
  • Zhang, Qi
  • Chynoweth, Michael W.

Abstract

In one embodiment, an apparatus comprises: a first plurality of registers to store information of at least a main sequence; a second plurality of registers to store information of at least one concurrent interval, the at least one concurrent interval independent of the main sequence, where the second plurality of registers are accessible only by instructions of the at least one concurrent interval and the first plurality of registers are accessible by instructions of the main sequence and the at least one concurrent interval; and an execution circuit coupled to the first register file and the second register file, the execution circuit to execute the instructions of the main sequence and the at least one concurrent interval. Other embodiments are described and claimed.

IPC Classes  ?

41.

ROBOT POSITION ERROR CORRECTION

      
Application Number CN2022123657
Publication Number 2024/065852
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Shi, Xuesong
  • Wang, Yujie
  • Manepalli, Sangeeta
  • Singh, Ruchika
  • Chattopadhyay, Rita
  • Dekel, Shay

Abstract

System and techniques for robot position error correction are described herein. A position of a robot may be established based on measurements of an environment of the robot from a first sensor of the robot. An error value based on data from a second sensor of the robot may be obtained. A weight is selected for the error value and a weighted error value is created by combining the weight and the error value. The position and the weighted error value may be combined to create a corrected position that is used as a basis for an operation of the robot.

IPC Classes  ?

  • G01C 21/00 - Navigation; Navigational instruments not provided for in groups

42.

ENHANCED UNAVAILABILITY MODE FOR STATION DEVICES UNASSOCIATED TO ACCESS POINTS

      
Application Number US2022044975
Publication Number 2024/072379
Status In Force
Filing Date 2022-09-28
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor Cariou, Laurent

Abstract

This disclosure describes systems, methods, and devices related to signaling unavailability to an access point (AP). A station device may generate a first frame indicating that the station device will be unavailable on a communication link; cause the station device to transmit the first frame on the communication link to the AP prior to associating to the AP; generate a second frame indicating that the station device is available on the communication link; cause the station device to transmit the second frame on the communication link to the AP after being unavailable after to transmitting the first frame; and identify an 802.11 authentication response received from the AP, after transmitting the second frame, indicating that the station device has been authenticated to the AP.

IPC Classes  ?

43.

ENHANCED NETWORK CODING DESIGN IN WI-FI 802.11 AGGREGATE MPDU FORMAT

      
Application Number US2022045285
Publication Number 2024/072398
Status In Force
Filing Date 2022-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Park, Minyoung
  • Cariou, Laurent
  • Mao, Wei
  • Nikopour, Hosein

Abstract

This disclosure describes systems, methods, and devices related to using network coding for aggregate medium access control (MAC) protocol data units (A-MPDUs). A device may identify an A-MPDU received from a second device; decode an A-Control subfield of a MAC header of a MPDU of the A-MPDU; determine, based on decoding the A-Control subfield, a network coding type used to generate the MPDU, a total number of data packets included in the A-MPDUs, a total number of parity packets included in the A-MPDUs, the parity packets based on the data packets, a packet index for the MPDU, the packet index indicating that the MPDU is an i-th packet of the A-MPDU, and that the MPDU is included in either a data packet of the total number of data packets or a parity packet of the total number of parity packets.

IPC Classes  ?

  • H04L 1/00 - Arrangements for detecting or preventing errors in the information received
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

44.

APPARATUS, SYSTEM, AND METHOD OF COMMUNICATING DURING A TRANSMIT OPPORTUNITY (TXOP) OVER A WIRELESS COMMUNICATION CHANNEL

      
Application Number US2022045296
Publication Number 2024/072399
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Cariou, Laurent
  • Kenney, Thomas J.

Abstract

For example, a wireless communication device may be configured to transmit protection information to signal that a Transmit Opportunity (TxOP) over a wireless communication channel is to be protected according to a preemption-based protection scheme. For example, the TxOP may include a preemption period between a first transmission period and a second transmission period. For example, the preemption-based protection scheme may be configured to allow one or more preempt-eligible wireless communication stations (STAs) to communicate over the wireless communication channel during the preemption period, and to prohibit non-preempt-eligible STAs from communicating over the wireless communication channel during the preemption period. For example, the wireless communication device may be configured to pause communication over the wireless communication channel during the preemption period to provide an opportunity to the one or more preempt-eligible STAs to preempt the wireless communication channel to communicate traffic.

IPC Classes  ?

  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 84/12 - WLAN [Wireless Local Area Networks]

45.

UNLICENSED NATIONAL INFORMATION INFRASTRUCTURE 4 ACCESS POINT COORDINATION AND CHANNEL ACCESS

      
Application Number US2022045464
Publication Number 2024/072420
Status In Force
Filing Date 2022-09-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Cariou, Laurent
  • Kenney, Thomas J.

Abstract

This disclosure describes systems, methods, and devices related to unlicensed national information infrastructure 4 (UNII4) channel access. A device may perform a first scan for signals from an outside basic service set (BSS) on a UNII4 frequency band. The device may generate a frame comprising an indication to allow an associated STA to perform enhanced distributed channel access (EDCA). The device may perform a second scan for signals subsequent to the associated STA performing EDCA.

IPC Classes  ?

  • H04W 74/08 - Non-scheduled access, e.g. random access, ALOHA or CSMA [Carrier Sense Multiple Access]
  • H04W 74/00 - Wireless channel access, e.g. scheduled or random access
  • H04W 16/14 - Spectrum sharing arrangements
  • H04W 72/04 - Wireless resource allocation
  • H04W 88/08 - Access point devices

46.

TECHNOLOGIES FOR HYBRID DIGITAL/ANALOG PROCESSORS FOR A QUANTUM COMPUTER

      
Application Number US2023031061
Publication Number 2024/072586
Status In Force
Filing Date 2023-08-24
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Mladenov, Todor
  • Daraeizadeh, Sahar
  • Matsuura, Anne

Abstract

Technologies for a hybrid digital/analog processor for a quantum computer are disclosed. In the illustrative embodiment, a hybrid digital/analog processor may be able to process digital instructions as well as analog instructions. The digital instructions may be, e.g., read from or write to memory or registers, perform an arithmetic operation, perform a branch, etc. The analog instructions may be to, e.g., provide an analog voltage to a particular electrode of a qubit, provide an analog pulse to a qubit, measure a reflection of an analog signal from a qubit, etc. The integration of analog operations in the hybrid digital/analog processor can improve performance by, e.g., lowering latency and lowering power usage.

IPC Classes  ?

  • G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
  • G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers
  • B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

47.

MICROELECTRONICS PACKAGES WITH PHOTO-INTEGRATED GLASS INTERPOSER

      
Application Number US2023031563
Publication Number 2024/072600
Status In Force
Filing Date 2023-08-30
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Tanaka, Hiroki
  • May, Robert A.
  • Darmawikarta, Kristof
  • Nie, Bai
  • Marin, Brandon
  • Ecton, Jeremy
  • Pietambaram, Srinivas
  • Liu, Changhua

Abstract

Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 23/15 - Ceramic or glass substrates
  • H01L 23/66 - High-frequency adaptations

48.

HYBRID PERFORMANCE MONITORING UNIT (PMU) ENUMERATION

      
Application Number US2023034210
Publication Number 2024/073099
Status In Force
Filing Date 2023-09-29
Publication Date 2024-04-04
Owner INTEL CORPORATION (USA)
Inventor
  • Rivas Toledano, Raoul
  • Kapaley, Udayan
  • Yasin, Ahmad
  • Gopalakrishnan, Karthik
  • Torrant, Marc

Abstract

Detailed herein are examples of hybrid (heterogenous) performance monitoring unit enumeration. In some examples, a processor supports an instruction that enumerates performance monitoring unit enumeration. For example, the processor comprises decoder circuitry to decode an instance of a single instruction, the single instruction to include a field for an opcode; and execution circuitry to execute the decoded instruction according to the opcode to return the processor identification and feature information including an enumeration of heterogenous performance monitoring unit capabilities.

IPC Classes  ?

  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 11/30 - Monitoring

49.

SELF-EVOLVING AND MULTI-VERSIONING CODE

      
Application Number CN2022121108
Publication Number 2024/060256
Status In Force
Filing Date 2022-09-23
Publication Date 2024-03-28
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Junyong
  • Chen, Yuan
  • Huang, Wenyong
  • Wang, Xin
  • Haghighat, Mohammad Reza

Abstract

Systems and methods for self-evolving and multi-versioning code. The system includes a compiler configured to translate a high-level source language file into a web assembly (wasm) file. One or more checkpoints are inserted into a function in the wasm file. The checkpoints are specified at various functions, to cause the compiler to collect parameter values where they are inserted. The compiler performs a just in time (JIT) compile operation on the wasm file with the checkpoint, generating enhanced JIT'd code. Inference operators can also be created in a background thread and included in the compile process to support profile monitoring. The JIT'd code is executed, and depending on the application, parameter values from the runtime environment can be emitted, as well as the values of the checkpoint parameter (s). Upon detecting a profile change, the compiler regenerates the JIT'd code.

IPC Classes  ?

  • G06F 9/455 - Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines

50.

NON-GRID OF BEAMS (GOB) BEAMFORMING CONTROL AND POLICY OVER E2 INTERFACE

      
Application Number US2023073748
Publication Number 2024/064534
Status In Force
Filing Date 2023-09-08
Publication Date 2024-03-28
Owner INTEL CORPORATION (USA)
Inventor
  • Han, Jaemin
  • Whinnett, Nicholas
  • Ying, Dawei
  • Ruan, Leifeng
  • Schreck, Jan

Abstract

Various embodiments herein provide techniques related to a radio access network (RAN) intelligence controller (RIC), a RAN Node, and/or a user equipment (UE). The RIC may be configured to determine to add, modify, or delete a beamforming configuration for one or more user equipments (UEs), wherein the beamforming configuration is associated with a non-grid-of beams (non-GoB) beamforming mode. The RIC may be further configured to encode, based on the determination, a message for transmission to the RAN Node to add, modify, or delete the beamforming configuration for the UE. The RAN Node may be configured to accordingly add, modify, or delete the beamforming configuration. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04B 7/0413 - MIMO systems
  • H04W 24/02 - Arrangements for optimising operational condition
  • H04W 88/08 - Access point devices
  • H04W 92/12 - Interfaces between hierarchically different network devices between access points and access point controllers
  • H04W 92/20 - Interfaces between hierarchically similar devices between access points

51.

VIEWPORT SWITCH LATENCY REDUCTION IN LIVE STREAMING

      
Application Number CN2022120930
Publication Number 2024/060213
Status In Force
Filing Date 2022-09-23
Publication Date 2024-03-28
Owner INTEL CORPORATION (USA)
Inventor
  • Luo, Ying
  • Chen, Xiaomin
  • Lv, Hongbo
  • Mao, Wenquan
  • Zhang, Hua

Abstract

This disclosure describes systems, methods, and devices related to enhanced viewport switching. A device may determine a view point change from a first segment to a second segment of a video stream, wherein each segment comprises a plurality of video chunks. The device may download a chunk location box at an end of each video chunk of the plurality of video chunks. The device may parse the chunk location box to update a chunk indexing table. The device may perform a completion check on a video chunk of the plurality of video chunks.

IPC Classes  ?

  • H04N 21/234 - Processing of video elementary streams, e.g. splicing of video streams or manipulating MPEG-4 scene graphs

52.

APPARATUS, DEVICE, METHOD, AND COMPUTER PROGRAM FOR EXECUTING BYTECODE

      
Application Number CN2022121027
Publication Number 2024/060232
Status In Force
Filing Date 2022-09-23
Publication Date 2024-03-28
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Junyong
  • Chen, Yuan
  • Zhang, Shiyu
  • Pan, Jie

Abstract

Examples relate to an apparatus, a device, a method, and a computer program for executing bytecode, and to a computer system and system comprising such an apparatus or device. The apparatus for executing bytecode comprises interface circuitry and processing circuitry and is configured to obtain, from a web server, a data transfer comprising bytecode to be executed, compile a first portion of the bytecode to native code, start execution of the first portion of the bytecode, and during execution of the first portion of the bytecode, compile a second portion of the bytecode to native code.

IPC Classes  ?

53.

PROGRAMMING STATEMENTS IN EMBEDDED DOMAIN SPECIFIC LANGUAGE

      
Application Number CN2022119150
Publication Number 2024/055262
Status In Force
Filing Date 2022-09-15
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Zhibin
  • Ling, Liyang
  • Chen, Xinghong

Abstract

An apparatus for compiling code comprising programming statements in an embedded do-main specific language is configured to obtain code comprising a first set of programming statements in an embedded domain-specific programming language and a second set of pro-gramming statements in a second programming language, the first set of programming state-ments comprising one or more pre-defined programming statements encapsulating a block of programming statements. The apparatus is configured to compile the first set of programming statements to generate a first set of transformed programming statements according to an in-termediate representation, the encapsulated programming statements being represented as a function call to a function comprising transformed programming statements corresponding to the encapsulated programming statements. The apparatus is configured to compile the second set of programming statements, the first set of programming statements being represented by the first set of transformed programming statements during the compilation of the second set of programming statements.

IPC Classes  ?

54.

DYNAMIC EXPLAINABLE ARTIFICIAL INTELLIGENCE PIPELINE COMPOSABILITY AND CUSTOMIZATION

      
Application Number US2023016946
Publication Number 2024/058823
Status In Force
Filing Date 2023-03-30
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Cheruvu, Ria
  • Bajpai, Harsha
  • Mehmood, Arshad
  • Sharmin, Saima

Abstract

Various systems and methods are described for explainable artificial intelligence (Al) operations, workflows, and implementing systems are discussed. In an example, explainable Al operations are coordinated in a computing system, by: receiving a schema for the explainable Al operations, the schema corresponding to a persona role used to evaluate an Al model; coordinating or performing the explainable Al operations, the explainable Al operations including: data analysis on output data produced from the Al model, and model analysis on performance of the Al model; and outputting explanation data from the explainable Al operations, the explanation data customized based on the schema. The explanation data may include a variety of data metrics and values used for reports, deployment, and monitoring.

IPC Classes  ?

55.

ACCELERATION OF COMMUNICATIONS

      
Application Number US2023030956
Publication Number 2024/058923
Status In Force
Filing Date 2023-08-23
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Manohar, Rajit
  • Soule, Robert
  • Tsai, Jr-Shian
  • Chen, Edmund
  • Cummings, Uri V.
  • Bressana, Pietro
  • Li, Rui

Abstract

Examples described herein relate to a network interface device that includes packet processing circuitry and circuitry. In some examples, the circuitry is to execute a first process of partitioned processes to provide a remote procedure call (RPC) interface for a second process. In some examples, the second process of the partitioned processes includes a business logic. In some examples, the partitioned processes comprise resource and deployment definition are based on an Interface Description Language (IDL) and a memory allocation.

IPC Classes  ?

56.

NUMEROLOGY, FRAME STRUCTURE, AND SIGNAL RESOURCE DIMENSIONING FOR JOINT COMMUNICATION AND SENSING SYSTEMS

      
Application Number US2023032025
Publication Number 2024/058955
Status In Force
Filing Date 2023-09-06
Publication Date 2024-03-21
Owner INTEL CORPORATION (USA)
Inventor
  • Hamidi-Sepehr, Fatemeh
  • Hewavithana, Thushara
  • Chatterjee, Debdeep
  • Lehne, Mark
  • Li, Qian

Abstract

An apparatus and system are described for joint communication and sensing. A sensing frame structure design is described within the next generation cellular system frame and numerology, as are the use of Positioning Reference Signals (PRS) for sensing with various expansions and adaptations. Speed/ direction related measurements of a user equipment (UE) allow velocity estimation in localization/positioning. Specifics of sequence-based signal generation and initialization in which a Gold sequence is used are also described.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path

57.

IMAGE PROCESSING WITH FACE MASK DETECTION

      
Application Number CN2022117834
Publication Number 2024/050760
Status In Force
Filing Date 2022-09-08
Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Fuwen
  • Xia, Yu
  • Zhou, Lan

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to automatically process an image based on a detection of a face mask. An example article of manufacture includes instructions that, when executed, cause programmable circuitry to at least: map a characteristic of an upper area (402) of a face of a person in an image to a color plot including a face skin tone cone (302); map a characteristic of a lower area (404) of the face to the color plot; and identify a presence or an absence of a face mask based on the respective positions of the characteristic of the upper area (402) and the characteristic of the lower area (404) relative to the skin tone cone (302).

IPC Classes  ?

  • G06K 11/00 - Methods or arrangements for graph-reading or for converting the pattern of mechanical parameters, e.g. force or presence, into electrical signals
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
  • H04L 27/00 - Modulated-carrier systems

58.

METHODS AND ARRANGEMENTS TO COMMUNICATE UE CONTEXT INFORMATION

      
Application Number US2023032006
Publication Number 2024/054454
Status In Force
Filing Date 2023-09-05
Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Han, Jaemin
  • Whinnett, Nicholas
  • Ying, Dawei
  • Ruan, Leifeng
  • Schreck, Jan

Abstract

Logic may determine user equipment (UE) context information associated with a UE, the UE context information comprising new information related to establishment of a new connection with the UE or related to an update of the UE context information for an existing connection with the UE. Logic may identify an event trigger associated with new information. And logic may respond to a query from the near-RT RIC for UE context information associated with the UE, wherein the UE supports a non-grid of beams mode for beamforming.

IPC Classes  ?

  • H04W 8/24 - Transfer of terminal data
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station

59.

ENHANCED IMAGE AND VIDEO OBJECT DETECTION USING MULTI-STAGE PARADIGM

      
Application Number CN2022118175
Publication Number 2024/050827
Status In Force
Filing Date 2022-09-09
Publication Date 2024-03-14
Owner INTEL CORPORATION (USA)
Inventor
  • Wei, Haoran
  • Guo, Ping
  • Wang, Peng
  • Wu, Xiangbin
  • Wu, Jiajie

Abstract

This disclosure describes systems, methods, and devices related to object detection in images. A device may input an image, representing an object, to a manual labeling learner system; identify, using the system, first coordinates of an upper left corner of a bounding box representing the object based on a heatmap indicative of a probability of the first coordinates representing the upper left corner; identify, using the system, second coordinates of a bottom right corner of the bounding box based on the first coordinates and a first distance regression map indicative of coordinate differences between the second coordinates and ground truth coordinates input to the machine learning model as training data; generate, using the system, adjustments to the first coordinates and the second coordinates based on a second regression map; and generate, using the system, the adjusted first and second coordinates, the bounding box.

IPC Classes  ?

  • G06V 10/20 - Image preprocessing
  • G06T 7/246 - Analysis of motion using feature-based methods, e.g. the tracking of corners or segments
  • H04L 27/00 - Modulated-carrier systems

60.

LOOP TRANSFORMATION IN TENSOR COMPILERS OF DEEP NEURAL NETWORKS (DNNS)

      
Application Number CN2022116853
Publication Number 2024/045188
Status In Force
Filing Date 2022-09-02
Publication Date 2024-03-07
Owner INTEL CORPORATION (USA)
Inventor
  • Rong, Hongbo
  • Avancha, Sasikanth
  • Heinecke, Alexander
  • Georganas, Evangelos
  • Chen, Xin
  • Madhu, Kavitha
  • Zhang, Mingzhe

Abstract

A tensor compiler for DNNs can use trained models for optimizing loop nests in IRs. A loop nest may include loops. A loop may be nested within another loop. A loop specifies a tensor operation to be repeatedly executed by a processor. The tensor compiler generates a schedule tree for an IR. The schedule tree includes schedules arranged based on hierarchies. The tensor compiler may select a schedule from the schedule tree by using a trained model that can predict performances of the processor executing the tensor operation in accordance with the IR transformed using the schedules. The tensor compiler then transforms the loop nest with the selected schedule and generates an implementation to be run by the processor. The tensor compiler may instrument the implementation for facilitating receipt of runtime performance information of the processor. The tensor compiler may use the runtime performance information to further train the model.

IPC Classes  ?

61.

OPTIMIZATION OF EXECUTABLE GRAPH FOR ARTIFICIAL INTELLIGENCE MODEL INFERENCE

      
Application Number CN2022116815
Publication Number 2024/045175
Status In Force
Filing Date 2022-09-02
Publication Date 2024-03-07
Owner INTEL CORPORATION (USA)
Inventor Huang, Zhengxu

Abstract

The application relates to optimization of an executable graph for AI model inference. An optimization method may include: duplicating the executable graph to generate a number M of same executable graphs; determining one or more nodes eligible for optimization from the executable graph, based on an inference throughput related parameter associated with an inference device to perform the AI model inference; and generating an optimized executable graph for the AI model inference by optimizing the one or more nodes from each of the number M of same executable graphs. Here, M is an integer in a range of 2 to a maximum number N of allowed executable graphs, and N is an integer manually configured or estimated based on a memory size of the inference device and a size of the executable graph.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology

62.

POST-ATTACK REAL-TIME TRAJECTORY RECOVERY OF COLLABORATIVE ROBOTIC ARMS

      
Application Number US2022042459
Publication Number 2024/049444
Status In Force
Filing Date 2022-09-02
Publication Date 2024-03-07
Owner INTEL CORPORATION (USA)
Inventor
  • Ghosal, Radhika
  • Felip Leon, Javier
  • Gonzalez Aguirre, David
  • Juliato, Marcio
  • Lesi, Vuk
  • Sastry, Manoj

Abstract

Techniques to perform post-attack real-time trajectory recovery of collaborative robotic arms are described. An intrusion detection system detects a security attack, and sends an alarm to a robotic safety system. The robotic safety system takes remedial actions to secure one or both of the collaborative robotic arms. In an offline phase, the robotic safety system plans safety trajectories for the collaborative robotic arms and stores them in a database. In an online phase, the robotic safety system receives the alarm from the IDS, and retrieves safety trajectories for the collaborative robotic arms from the database. Other embodiments are described and claimed.

IPC Classes  ?

63.

SIGNAL DE-CORRELATION FOR TRAINING MULTI-LANE ETHERNET INTERFACES

      
Application Number US2023021958
Publication Number 2024/049517
Status In Force
Filing Date 2023-05-11
Publication Date 2024-03-07
Owner INTEL CORPORATION (USA)
Inventor Lusted, Kent C.

Abstract

Examples described herein relate to an Ethernet physical layer transceiver (PHY) circuitry to generate a training signal for transmission for a lane based on a pseudorandom bit sequence (PRBS) polynomial and seed.

IPC Classes  ?

  • H04L 25/49 - Transmitting circuits; Receiving circuits using three or more amplitude levels
  • H04L 25/02 - Baseband systems - Details

64.

TRAINING NEURAL NETWORK THROUGH MANY-TO-ONE KNOWLEDGE INJECTION

      
Application Number CN2022114972
Publication Number 2024/040544
Status In Force
Filing Date 2022-08-26
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Liu, Xiaolong
  • Yao, Anbang
  • Qian, Yi
  • Lin, Jiaojiao
  • Chen, Yurong

Abstract

A target neural network can be trained with a support neural network through many-to-one knowledge injection. The many-to-one knowledge injection is facilitated by two layers inserted into the target neural networks. The first layer converts a target OFM in the target neural network into an expanded feature map having more channels. The second layer converts the expanded feature map to a new feature map having the same dimensions as the target OFM. The expanded feature map can be divided into segments, each of which has the same number of channels as a support OFM in the support neural network so that the knowledge in the support OFM can be injected into each of the segment through a many-to-one injection. To train the target neural network, parameters inside the target neural network are modified to minimize a feature distance between the expanded feature map and the support OFM.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology

65.

POINT GRID NETWORK WITH LEARNABLE SEMANTIC GRID TRANSFORMATION

      
Application Number CN2022114976
Publication Number 2024/040546
Status In Force
Filing Date 2022-08-26
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Cai, Dongqi
  • Yao, Anbang
  • Kang, Yangyuxuan
  • Wang, Shandong
  • Chen, Yurong

Abstract

A point grid network is a neural network that can model graph-structured data. The point grid network receives a graph-structured data sample, which may be a graph representation of an object. The point grid network uses an assignment matrix to transform the graph representation into a grid representation of the object. The assignment matrix defines whether graph nodes in the graph representation is to be assigned to grid elements in the grid structure. The grid representation is a tensor that can be processed through convolutional operations or other types of tensor operations. The point grid network can perform convolution on the grid representation and one or more filters to generate a grid-structured feature map. Values in the filter (s) and values in the assignment matrix are determined through training the point grid network. The point grid network may further determine a condition of the object based on the grid-structured feature map.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology

66.

FRACTIONAL-BIT QUANTIZATION AND DEPLOYMENT OF CONVOLUTIONAL NEURAL NETWORK MODELS

      
Application Number CN2022114114
Publication Number 2024/040421
Status In Force
Filing Date 2022-08-23
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Yao, Anbang
  • Yang, Yi
  • Chen, Feng
  • Shen, Wanglei
  • Lu, Ming
  • Cheng, Liang
  • Zhang, Yu
  • Liu, Miaoming
  • Liu, Bo
  • Chen, Yurong

Abstract

The disclosure relates to fractional-bit network quantization and deployment of CNN models. An AI accelerator, including: an input buffer configured to buffer an input image; a weight buffer configured to buffer convolutional kernel indexes for a convolutional layer of a CNN model; a kernel pattern buffer configured to buffer a 1-bit convolutional kernel subset for the convolutional layer of the CNN model, wherein the 1-bit convolutional kernel subset includes 2 τ 1-bit convolutional kernels with a size of K×K; a PE array including one or more PE nodes, each of which is configured to generate convolutional results of an image region of the input image and 1-bit convolutional kernels corresponding to the convolutional kernel indexes in the 1-bit convolutional kernel subset; and an output buffer configured to buffer convolutional results of respective image regions of the input image and the 1-bit convolutional kernels corresponding to the convolutional kernel indexes.

IPC Classes  ?

67.

APPARATUS, DEVICE, METHOD, AND COMPUTER PROGRAM FOR PERSISTING MEMORY RECOVERY ACTIONS

      
Application Number CN2022114728
Publication Number 2024/040502
Status In Force
Filing Date 2022-08-25
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Xu, Tao
  • Liu, Shijie
  • Zhu, Lei
  • Jayakumar, Sarathy
  • Li, Yufu

Abstract

Examples relate to an apparatus, device, method, and computer program for persisting memory recovery actions, and to a computer system comprising such an apparatus or device. An apparatus or device for persisting memory recovery actions is configured to determine one or more memory recovery actions taken by a memory controller with respect to memory cir-cuitry, and to store information on the one or more memory recovery actions being taken by the memory controller to storage circuitry being co-located with the memory circuitry.

IPC Classes  ?

  • G06F 16/21 - Design, administration or maintenance of databases

68.

MEMORY PRESERVED WARM RESET MECHANISM

      
Application Number CN2022114779
Publication Number 2024/040508
Status In Force
Filing Date 2022-08-25
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Nachimuthu, Murugasamy
  • Yao, Jiewen

Abstract

An apparatus is disclosed. The apparatus comprises one or more processors to receive a request to trigger a system management interrupt (SMI), execute policy shim code to enforce access control policy in a first privilege level and dispatch the SMI to shield code to enforce the access security policy to perform a system management mode (SMM) and execute the shield code to perform the SMM, including retrieving an operating system (OS) memory preserved warm reset (MPWR) context, saving the MPWR context and issuing a warm reset.

IPC Classes  ?

69.

IMPLEMENTATION OF DEVICE SEAMLESS UPDATE WITH PRE-AUTHORIZATION POLICY IN TRUSTED EXECUTION ENVIRONMENT

      
Application Number CN2022114781
Publication Number 2024/040509
Status In Force
Filing Date 2022-08-25
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Yao, Jiewen
  • Datta, Shamanna
  • Natu, Mehesh
  • Ruan, Xiaoyu
  • Draper, Andrew
  • Makaram, Raghunandan
  • Munoz, Alberto

Abstract

A system and method of enhancing the implementation of device seamless updates with a pre-authorization policy in Trusted Execution Environments include setting a device update pre-authorization policy while establishing a connection with the device, indicating that pre-authorization is necessitated for updating the device, receiving a pre-authorization event from the device, where the pre-authorization event indicates an update for the device has been activated, determining whether the device is authorized to perform the update, and sending a response indicating whether the device is authorized to perform the update to the device.

IPC Classes  ?

70.

HEAD ARCHITECTURE FOR DEEP NEURAL NETWORK (DNN)

      
Application Number CN2022115254
Publication Number 2024/040601
Status In Force
Filing Date 2022-08-26
Publication Date 2024-02-29
Owner INTEL CORPORATION (USA)
Inventor
  • Yao, Anbang
  • Li, Chao
  • Cai, Dongqi
  • Liu, Xiaolong
  • Shao, Wenjian

Abstract

A head of a DNN receives an OFM from a backbone network of the DNN. The head can partition the OFM into feature groups having same sizes. The head can further generate local tensors from the features group. To generate a local tensor from a feature group, the head may further partition the feature group into two subgroups, e.g., based on a splitting factor. The spatial sizes of the subgroups depend on the splitting factor. One subgroup can be converted into an attention tensor. The other subject can be converted into a value tensor, which may have the same size as the attention tensor. The attention tensor and value tensor are mixed to produce the local tensor. The local tensors of all the feature groups can be aggregated to form a global vector, which can be fed into a classifier to output one or more classification determined by the DNN.

IPC Classes  ?

  • G06K 9/00 - Methods or arrangements for reading or recognising printed or written characters or for recognising patterns, e.g. fingerprints
  • G06N 3/08 - Learning methods

71.

SYSTEM FOR PATH-AWARE MOBILITY MANAGEMENT AND MOBILITY-MANAGEMENT-AWARE PATH PLANNING FOR ROBOTS

      
Application Number CN2022113140
Publication Number 2024/036529
Status In Force
Filing Date 2022-08-17
Publication Date 2024-02-22
Owner INTEL CORPORATION (USA)
Inventor
  • Sudhakaran, Susruth
  • Cavalcanti, Dave
  • Eisen, Mark
  • Perez-Ramirez, Javier
  • Fang, Juan

Abstract

Disclosed herein are systems, methods, and devices for providing mobility management and path planning with an interface between the mobility management functions and path planning functions. A mobility controller may receive an expected location into which a robot plans to move at a predefined time and determine, based on the expected location and a current location of the robot, an infrastructure configuration for a wireless infrastructure device that provide wireless connectivity at the expected location. The mobility controller may also generate a message to configure the wireless infrastructure device at the predefined time according to the infrastructure configuration.

IPC Classes  ?

  • G05D 1/02 - Control of position or course in two dimensions

72.

INTEGRATED CIRCUIT DEVICE WITH ELECTRICALLY ACTIVE FIDUCIALS

      
Application Number US2023028148
Publication Number 2024/039485
Status In Force
Filing Date 2023-07-19
Publication Date 2024-02-22
Owner INTEL CORPORATION (USA)
Inventor
  • Niazi, Haris Khan
  • Shi, Yi
  • Elsherbini, Adel A.
  • Brun, Xavier
  • Dogiamis, Georgios
  • Brown, Thomas
  • Karhade, Omkar

Abstract

An integrated circuit (IC) device comprises an array comprising rows and columns of conductive interconnect pads. At least one optical alignment fiducial region is distinct from the array and comprises a fiducial pattern, wherein the fiducial pattern comprises a first group of pads contiguous to a second group of pads, and wherein a width of a space between nearest pads of the first and second groups is wider than the spaces between pads within each group.

IPC Classes  ?

  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

73.

METHOD OF COMPILE-TIME OPTIMIZATION FOR NESTED PARALLEL FOR-LOOPS FOR DEEP LEARNING NEURAL NETWORK COMPUTATION

      
Application Number US2023067621
Publication Number 2024/039923
Status In Force
Filing Date 2023-05-30
Publication Date 2024-02-22
Owner INTEL CORPORATION (USA)
Inventor
  • Mei, Yijie
  • Qin, Zhennan
  • Li, Jianhui

Abstract

A computing system includes memory circuitry to store instructions and a deep neural network (DNN) computation subgraph; and a processor coupled to the memory circuitry to execute the instructions to transform a current operation of the DNN computation subgraph to a nested parallel-for loop instruction for the current operation; block the nested parallel-for loop instruction to create a one-to-one mapping between parallel subtasks of the nested parallel-for loop instruction with threads; and mark a parallel-for loop instruction of the nested parallel-for loop instruction of the current operation and a parallel-for loop instruction of a next operation of the DNN computation subgraph as linkable if both the current operation and the next operation are parallelized along a same data dimension at a top level of the DNN computation subgraph and with a same blocking factor.

IPC Classes  ?

  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06F 8/41 - Compilation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

74.

QUASI-MONOLITHIC DIE ARCHITECTURES

      
Application Number US2023069812
Publication Number 2024/039936
Status In Force
Filing Date 2023-07-07
Publication Date 2024-02-22
Owner INTEL CORPORATION (USA)
Inventor
  • Yao, Jimin
  • Elsherbini, Adel A.
  • Brun, Xavier Francois
  • Jun, Kimin
  • Liff, Shawna M.
  • Swan, Johanna M.
  • Shi, Yi
  • Talukdar, Tushar
  • Eid, Feras
  • Kabir, Mohammad Enamul
  • Karhade, Omkar G.
  • Krishnatreya, Bhaskar Jyoti

Abstract

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

IPC Classes  ?

  • H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

75.

CONSTRAINED APPLICATION PROTOCOL FOR COMPUTING SERVICES IN CELLULAR NETWORKS

      
Application Number US2023070649
Publication Number 2024/039950
Status In Force
Filing Date 2023-07-20
Publication Date 2024-02-22
Owner INTEL CORPORATION (USA)
Inventor
  • Ding, Zongrui
  • Li, Qian
  • Tong, Xiaopeng
  • Stojanovski, Alexandre, Saso
  • Luetzenkirchen, Thomas
  • Kolekar, Abhijeet
  • Palat, Sudeep
  • Bangolae, Sangeetha
  • Heo, Youn Hyoung

Abstract

This disclosure describes systems, methods, and devices related to Constrained Application Protocol (CoAP). A device may decode a service request for computing in CoAP message from User Equipment (UE) via a Radio Resource Control (RRC) or Non-Access Stratum (NAS) container. The device may map the decoded CoAP message into a service request for computing in HTTP to a Service Communication Proxy Function (SOCF), by operating as a CoAP to HTTP proxy. The device may monitor for the results of the computing service if asynchronous results delivery is indicated. The device may encode a CoAP acknowledgement (ACK) message indicating asynchronous data delivery.

IPC Classes  ?

  • H04L 67/566 - Grouping or aggregating service requests, e.g. for unified processing
  • H04L 67/02 - Protocols based on web technology, e.g. hypertext transfer protocol [HTTP]
  • H04L 67/60 - Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources
  • H04W 88/14 - Backbone network devices

76.

PAILLIER CRYPTOSYSTEM WITH IMPROVED PERFORMANCE

      
Application Number CN2022112396
Publication Number 2024/036429
Status In Force
Filing Date 2022-08-15
Publication Date 2024-02-22
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Bin
  • Peng, Bo

Abstract

An improved Paillier cryptosystem generates a product of ciphertext data and plaintext data by inverting ciphertext data using a square of a public encryption key to generate a modular multiplicative inverse of the ciphertext data; subtracting plaintext data from the public encryption key to generate negative plaintext data; and generating a modular exponentiation of the modular multiplicative inverse of the ciphertext data, the negative plaintext data and the square of the public encryption key.

IPC Classes  ?

  • H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy

77.

SIGNALING MECHANISMS FOR POSITIONING FOR USER EQUIPMENTS WITH REDUCED CAPABILITY

      
Application Number US2023072011
Publication Number 2024/036269
Status In Force
Filing Date 2023-08-10
Publication Date 2024-02-15
Owner INTEL CORPORATION (USA)
Inventor
  • Xiong, Gang
  • Chatterjee, Debdeep
  • Wang, Guotong
  • Han, Seunghee
  • Lee, Jihyun

Abstract

Various embodiments herein provide techniques for frequency hopping for positioning with reduced capability (RedCap) user equipments (UEs). For example, the RedCap UE may perform downlink positioning reference signal (DL-PRS) measurements using frequency hopping and bandwidth stitching. Additionally, or alternatively, the RedCap UE may transmit an uplink sounding reference signal (UL-SRS) using frequency hopping. Other embodiments may be described and claimed.

IPC Classes  ?

  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04W 24/08 - Testing using real traffic
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/04 - Wireless resource allocation
  • H04W 88/02 - Terminal devices

78.

TIME DOMAIN NETWORK ENERGY SAVING TECHNIQUES

      
Application Number US2023029875
Publication Number 2024/035802
Status In Force
Filing Date 2023-08-09
Publication Date 2024-02-15
Owner INTEL CORPORATION (USA)
Inventor
  • Islam, Toufiqul
  • Lee, Dae Won
  • Lim, Seau S.

Abstract

An apparatus and system are described for reducing user equipment (UE) power consumption after a 5th generation NodeB (gNB) indicates transition to a power saving mode. Different configurations and rules for the UE to identify and use monitoring or transmission occasions within the PSM active time, as well as modification of UE timers during the PSM, are provided. Discontinuous transmission (DTX) and reception (DRX) configurations are signaled to the UE and contain periodicity, start slot/offset, and on duration, as well as activation of the configurations by downlink control information (DCI). UE reporting and paging based on the configurations are provided when light synchronization system block (SSB) transmission or discovery reference signal transmission is used by the gNB.

IPC Classes  ?

  • H04W 52/02 - Power saving arrangements
  • H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04W 76/28 - Discontinuous transmission [DTX]; Discontinuous reception [DRX]
  • H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems

79.

TECHNIQUES FOR SOUNDING REFERENCE SIGNAL (SRS) OPERATION WITH EIGHT PORTS

      
Application Number US2023071787
Publication Number 2024/036111
Status In Force
Filing Date 2023-08-07
Publication Date 2024-02-15
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Guotong
  • Mondal, Bishwarup

Abstract

Systems, apparatuses, methods, and computer-readable media are provided for sounding reference signal (SRS) transmission with eight antenna ports. For example, one SRS resource with multiple orthogonal frequency division multiplexing (OFDM) symbols may be configured. Alternatively, multiple SRS resources may be configured to enable 8-port operation. Other embodiments may be described and claimed.

IPC Classes  ?

  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/04 - Wireless resource allocation

80.

POWER EFFICIENT MICRO-LED ARCHITECTURES

      
Application Number CN2022112220
Publication Number 2024/031670
Status In Force
Filing Date 2022-08-12
Publication Date 2024-02-15
Owner INTEL CORPORATION (USA)
Inventor
  • West, Paul
  • Lin, Yingfei
  • Woodbeck, Ronald C.
  • Ahmed, Khaled

Abstract

In one embodiment, an apparatus includes a thin film transistor (TFT) structure (304) layer, a dielectric layer (306) on the TFT structure (304) layer, and an anode (308) on the dielectric layer (306) and in electrical connection with the TFT structure (304) layer. The apparatus also includes a light emitting material on the anode (308) and a reflective material layer (318) surrounding the light emitting material. The apparatus further includes a cathode (314) on the light emitting material.

IPC Classes  ?

  • H01L 21/77 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate

81.

INTER-CELL BEAM MANAGEMENT SCHEDULING RESTRICTION AND REPORTING

      
Application Number US2023029757
Publication Number 2024/035724
Status In Force
Filing Date 2023-08-08
Publication Date 2024-02-15
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Hua
  • Zhang, Meng
  • Huang, Rui
  • Hwang, In-Seok
  • Burbidge, Richard C.

Abstract

simultaneousRxDataSSB-DiffNumerologysimultaneousRxDataSSB-DiffNumerologysimultaneousRxDataSSB-DiffNumerology, the UE is not expected to receive downlink data/control signaling or channel state information reference signals or transmit uplink data/control signaling or sounding reference signals on symbols corresponding to SSB indexes configured for L1-RSRP measurement.

IPC Classes  ?

  • H04W 72/12 - Wireless traffic scheduling
  • H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
  • H04W 72/0457 - Variable allocation of band or rate
  • H04W 24/08 - Testing using real traffic
  • H04W 24/10 - Scheduling measurement reports
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 27/26 - Systems using multi-frequency codes

82.

ENHANCED UPLINK TRANSMISSIONS FOR WIRELESS COMMUNICATIONS USING MORE THAN FOUR LAYERS

      
Application Number US2023030077
Publication Number 2024/035930
Status In Force
Filing Date 2023-08-11
Publication Date 2024-02-15
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Guotong
  • Mondal, Bishwarup
  • Sergeev, Viktor

Abstract

This disclosure describes systems, methods, and devices for configuring an uplink transmission for a user equipment device (UE) using eight transmitters. A network device may encode a precoder rank indicator for use in an eight-transmitter uplink transmission by a UE device; encode a precoder indicator, indicative of a precoder type, for use in the eight-transmitter uplink transmission by the UE device; and encode downlink control information (DCI) for transmission to the UE device, the DCI including the precoder rank and the precoder indicator.

IPC Classes  ?

  • H04B 7/0456 - Selection of precoding matrices or codebooks, e.g. using matrices for antenna weighting
  • H04W 72/12 - Wireless traffic scheduling
  • H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station

83.

TRANSMIT (TX) CARRIER SELECTION FOR NEW RADIO (NR) SIDELINK OPERATION

      
Application Number US2023071443
Publication Number 2024/030912
Status In Force
Filing Date 2023-08-01
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Ali, Ansab
  • Roth, Kilian
  • Talarico, Salvatore
  • Malik, Rafia
  • Bangolae, Sangeetha L.
  • Heo, Youn Hyoung

Abstract

Various embodiments herein relate to identification of a transmit carrier for a new radio (NR) sidelink (SL) transmission. Specifically, embodiments may relate to identification of a plurality of potential transmit carriers, and then ranking of those carriers. The ranking may be performed based at least in part on channel busy ratio (CBR) values associated with respective ones of the plurality of potential transmit carriers. Other embodiments may be described and/or claimed.

IPC Classes  ?

  • H04W 72/02 - Selection of wireless resources by user or terminal
  • H04W 72/54 - Allocation or scheduling criteria for wireless resources based on quality criteria
  • H04W 72/563 - Allocation or scheduling criteria for wireless resources based on priority criteria of the wireless resources
  • H04W 72/04 - Wireless resource allocation
  • H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
  • H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices

84.

ACTIVATION AND DEACTIVATION OF SEMI-PERSISTENT SCHEDULING USING MULTI-CELL TECHNIQUES

      
Application Number US2023071625
Publication Number 2024/031028
Status In Force
Filing Date 2023-08-03
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Wang, Yi
  • Li, Yingyang
  • Xiong, Gang

Abstract

This disclosure describes systems, methods, and devices related to semi-persistent scheduling (SPS) or configured grant (CS). A device may decode a configuration for a Downlink Control Information (DCI) format for multi-cell scheduling. The device may detect the DCI format. The device may validate the DCI based on whether it is scrambled with a CS-RNTI or a specific RNTI. The device may activate a semi-persistent scheduling physical downlink shared control channel (SPS PDSCH) reception or a Type 2 configured grant physical uplink shared channel (CG PUSCH) transmission. The device may release for the SPS PDSCH reception or the CG PUSCH transmission based on the validation of the DCI.

IPC Classes  ?

  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04W 72/11 - Semi-persistent scheduling
  • H04W 72/12 - Wireless traffic scheduling
  • H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems

85.

MANAGEMENT DATA ANALYTICS (MDA) REPORTING

      
Application Number US2023028440
Publication Number 2024/030280
Status In Force
Filing Date 2023-07-24
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Yao, Yizhi
  • Chou, Joey

Abstract

An apparatus and system are described for multiple methods of Management Data Analytics (MDA) reporting. A Management Data Analytics Service (MDAS) producer receives a request to create a Managed Object Instance (MOI) for an MDA request. The MDAS producer creates the MOI for the MDA request, responds to an MDAS consumer about a result of creation of the MOI, and performs MDA. The MDAS producer then makes a subscription for a reporting target based on a reporting method selected from a plurality of reporting methods or establishes a streaming connection with the reporting target, creates an MDA report based on the MDA, and sends the MDA report to a reporting target per the reporting method.

IPC Classes  ?

86.

UE CAPABILITY FOR INTER-RAT MEASUREMENTS WITHOUT MEASUREMENT GAPS

      
Application Number US2023029119
Publication Number 2024/030378
Status In Force
Filing Date 2023-07-31
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Huang, Rui
  • Zhang, Meng
  • Li, Hua
  • Hwang, In Seok

Abstract

A user equipment (UE) configured for operation in a 5G NR network may be capable of operating in accordance two or more radio-access technologies (RATs) including a first RAT and a second RAT. The UE may encode a UE capability information element for transmission to a serving cell indicating whether the UE has a capability for performing inter-RAT measurements without measurement gaps. When the UE indicated the capability for performing inter-RAT measurements without measurement gaps, the UE may be configured to simultaneously measure signals of the second RAT in a second frequency band while receiving data or while transmitting data in accordance with the first RAT in a first frequency band. When the UE is performing inter-RAT measurements without measurement gaps, the UE may temporarily pause transmission of acknowledgements (ACKs) and negative ACKs (NACKs) (ACK/NACKs) for the data received in accordance with the first RAT during the measurement of the signals of the second RAT.

IPC Classes  ?

87.

ENHANCED UNKNOWN SECONDARY CELL ACTIVATION FOR WIRELESS COMMUNICATIONS

      
Application Number US2023029335
Publication Number 2024/030502
Status In Force
Filing Date 2023-08-02
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Hua
  • Zhang, Meng
  • Huang, Rui
  • Hwang, In-Seok
  • Burbidge, Richard

Abstract

This disclosure describes systems, methods, and devices for secondary cell activation. A device may decode a medium access control (MAC) control element received from a network node, the MAC control element including a request to activate a secondary cell (SCell); perform receiver beam sweeping using a beam sweeping factor less than eight in a frequency range prior to activating the SCell, the receiver beam sweeping including: automatic gain control using the beam sweeping factor; and searching for the SCell using the beam sweeping factor; encode a reference signal received power (RSRP) report to be transmitted, the RSRP report including a synchronization signal block (SSB) prior to activating the SCell; perform a channel status information measurement prior to activating the SCell; encode a report indicative of the channel status information measurement to be transmitted prior to activating the SCell; and activate the SCell.

IPC Classes  ?

  • H04W 24/08 - Testing using real traffic
  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04B 17/318 - Received signal strength
  • H04W 56/00 - Synchronisation arrangements
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

88.

RADIO RESOURCE MANAGEMENT REQUIREMENTS FOR NEW RADIO DUAL CONNECTIVITY

      
Application Number US2023071425
Publication Number 2024/030903
Status In Force
Filing Date 2023-08-01
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Hua
  • Zhang, Meng
  • Huang, Rui
  • Hwang, In-Seok

Abstract

The present disclosure specifies requirements to support multi-radio (MR)-dual connectivity (DC) radio resource management (RRM) requirements, including RRM requirements for frequency range 1 (FR1)+FR1 new radio (NR)-NR Dual Connectivity (NR-DC) scenarios.

IPC Classes  ?

  • H04W 24/08 - Testing using real traffic
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 56/00 - Synchronisation arrangements
  • H04W 76/15 - Setup of multiple wireless link connections
  • H04B 17/309 - Measuring or estimating channel quality parameters

89.

MICRO LED ARRAYS ON GLASS SUBSTRATES FOR OPTICAL COMMUNICATIONS

      
Application Number CN2022110152
Publication Number 2024/026760
Status In Force
Filing Date 2022-08-04
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Duong, Benjamin
  • Adivarahan, Vinod
  • Cui, Liqiang
  • Marin, Brandon C.
  • Gaan, Sandeep

Abstract

Embodiments disclosed herein include optical communication modules and optoelectronic packages. In an embodiment, an optical communication module comprises a substrate, a transistor over the substrate, an array of micro light emitting diodes (LEDs) over the transistor, and a connector over the array of micro LEDs.

IPC Classes  ?

  • H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication

90.

BEAM FAILURE DETECTION AND LINK RECOVERY TEST FOR MULTI-TRP OPERATION

      
Application Number US2023029220
Publication Number 2024/030434
Status In Force
Filing Date 2023-08-01
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Li, Hua
  • Zhang, Meng
  • Burbidge, Richard C.
  • Huang, Rui
  • Hwang, In Seok

Abstract

A user equipment (UE) configured for operation in a fifth-generation (5G) new radio (NR) network may be configured for Transmission-Reception Point (TRP) specific beam failure detection (BFD) and candidate beam detection (CBD) testing. For the BFD and CBD testing, the UE may monitor signal levels of a PSCell within an active downlink bandwidth part (DL-BWP) during an evaluation period, the signal levels of the PSCell including a signal-to-noise ratio (SNR) level of a reference signal received within a first beam set from a first TRP, a layer one (L1) Reference Signal Received Power (RSRP) level of a reference signal received within a second beam set from the first TRP, and a SNR level of a reference signal received within a first beam set from a second TRP.

IPC Classes  ?

  • H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
  • H04W 24/08 - Testing using real traffic
  • H04W 72/04 - Wireless resource allocation
  • H04W 72/0457 - Variable allocation of band or rate
  • H04B 17/309 - Measuring or estimating channel quality parameters
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

91.

EFFICIENT CERTIFICATE REVOCATION PROCEDURES AND ENHANCED SECURITY MANAGEMENT

      
Application Number US2023029250
Publication Number 2024/030454
Status In Force
Filing Date 2023-08-01
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor Kolekar, Abhijeet

Abstract

This disclosure describes systems, methods, and devices related to revocation resilience. A device may decode a certificate received by a network function (NF) consumer during a transport layer security (TLS) handshake. The device may evaluate whether the certificate includes online certificate status protocol (OCSP) parameters by the NF consumer. The device may initiate an OCSP request to an OCSP responder or a cache manager based on a presence of the OCSP parameters in the certificate. The device may decode an OCSP response from the OCSP responder or the cache manager.

IPC Classes  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • H04L 9/40 - Network security protocols

92.

PRE-CONFIGURED AND CONCURRENT MEASUREMENT GAP UE BEHAVIOR

      
Application Number US2023029264
Publication Number 2024/030463
Status In Force
Filing Date 2023-08-02
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Huang, Rui
  • Zhang, Meng
  • Li, Hua
  • Hwang, In-Seok

Abstract

An apparatus and system are described to indicate user equipment (UE) capability on UE measurements with pre-configured measurement gaps (MGs) in new radio systems. The pre-configured MGs may be one or more instances in concurrent MGs, and may be activated/ deactivated using downlink control information (DCI). The activated pre-configured MGs may overlap with other MGs and may impact the maximum number of concurrent MGs that are supported by the UE. Overlapping MGs may increase pre-configured gap activation delay.

IPC Classes  ?

  • H04W 24/10 - Scheduling measurement reports
  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
  • H04W 72/0457 - Variable allocation of band or rate
  • H04L 5/00 - Arrangements affording multiple use of the transmission path

93.

TECHNIQUES FOR PRIORITIZING SIDELINK POSITIONING INFORMATION

      
Application Number US2023029315
Publication Number 2024/030491
Status In Force
Filing Date 2023-08-02
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Xiong, Gang
  • Chatterjee, Debdeep
  • Roth, Kilian
  • Islam, Toufiqul
  • Lee, Jihyun

Abstract

Techniques relating to prioritization of sidelink positioning reference signals (SL PRS) for sidelink positioning in a new radio (NR) system are described. In one embodiment, a method to manage communications for a user equipment (UE) includes detecting a set of overlapping symbols between a SL PRS and a message in a slot for a frame in a time domain of a NR system, retrieving priority information for the SL PRS from a data storage device, and determining a schedule for transmission or reception of the SL PRS and the message based on the priority information. Other embodiments are described and claimed.

IPC Classes  ?

  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/25 - Control channels or signalling for resource management between terminals via a wireless link, e.g. sidelink
  • H04W 72/56 - Allocation or scheduling criteria for wireless resources based on priority criteria
  • H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
  • H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices

94.

METHODS AND ARRANGEMENTS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING

      
Application Number US2023029375
Publication Number 2024/030532
Status In Force
Filing Date 2023-08-03
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Roth, Kilian
  • Xiong, Gang
  • Chatterjee, Debdeep
  • Lee, Jihyun
  • Islam, Toufiqul

Abstract

Logic may perform resource selection from a resource pool to determine a set of resources from the resource pool for transmission of a reference signal. Logic may autonomously allocate the set of resources for a transmission of the reference signal within a physical sidelink shared channel (PSSCH) or as a standalone transmission. Logic may generate a control information signal to signal the set of resources for the reference signal, the control information signal comprising a source identifier field, a destination identifier field, and one or more fields to indicate automatic gain control, guard symbols, or a combination thereof. And logic may encode the control information signal for transmission to a second UE via the interface.

IPC Classes  ?

  • H04W 72/25 - Control channels or signalling for resource management between terminals via a wireless link, e.g. sidelink
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04L 27/26 - Systems using multi-frequency codes
  • H04W 24/08 - Testing using real traffic
  • H04W 64/00 - Locating users or terminals for network management purposes, e.g. mobility management
  • H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices

95.

ENHANCED QUALITY OF SERVICE-LEVEL SECURITY FOR WIRELESS COMMUNICATIONS

      
Application Number US2023029431
Publication Number 2024/030574
Status In Force
Filing Date 2023-08-03
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Zhang, Yi
  • Stojanovski, Alexandre Saso
  • Kolekar, Abhijeet
  • Luetzenkirchen, Thomas

Abstract

This disclosure describes systems, methods, and devices for quality of service (QoS)- level security configuration in a packet data unit (PDU) session. A device may identify a first user plane security indication received from an application function of a wireless network; identify a second user plane security indication received from the application function; generate, based on the first user plane security indication, a first security configuration for a first QoS flow of a PDU session; generate, based on the second user plane security indication, a second security configuration for a second QoS flow of the PDU session, the first security configuration different than the second security configuration; decode a first packet received, from the UE, in the first QoS flow using the first security configuration; and decode a second packet received, from the UE, in the second QoS flow using the second security configuration.

IPC Classes  ?

  • H04W 28/02 - Traffic management, e.g. flow control or congestion control
  • H04L 41/0894 - Policy-based network configuration management
  • H04W 76/22 - Manipulation of transport tunnels
  • H04W 12/037 - Protecting confidentiality, e.g. by encryption of the control plane, e.g. signalling traffic
  • H04W 88/14 - Backbone network devices

96.

NETWORK-CONTROLLED SMALL GAP (NCSG) CONFIGURATIONS

      
Application Number US2023029529
Publication Number 2024/030640
Status In Force
Filing Date 2023-08-04
Publication Date 2024-02-08
Owner INTEL CORPORATION (USA)
Inventor
  • Huang, Rui
  • Zhang, Meng
  • Li, Hua
  • Burbidge, Richard C.
  • Hwang, In-Seok

Abstract

A computer-readable storage medium stores instructions for execution by one or more processors of a UE to configure the UE for handover using pre-configured gaps in a 5G NR network, and to cause the UE to perform operations including decoding first configuration signaling received from a first base station associated with a first cell. The first configuration signaling configures a legacy measurement gap. The UE decodes second configuration signaling received from the first base station. The second configuration signaling configures an NCSG measurement gap. The UE performs cell measurements of a second cell associated with a second base station during one of the legacy measurement gap or the NCSG measurement gap. The UE encodes the cell measurements for transmission to the first base station. The UE decodes a handover instruction from the first base station. The handover instruction is based on the cell measurements.

IPC Classes  ?

  • H04W 36/00 - Handoff or reselecting arrangements
  • H04W 36/08 - Reselecting an access point
  • H04W 36/38 - Reselection control by fixed network equipment

97.

ARTIFICIAL INTELLIGENCE AND MACHINE LEARNING ENTITY TESTING

      
Application Number US2023071393
Publication Number 2024/026515
Status In Force
Filing Date 2023-08-01
Publication Date 2024-02-01
Owner INTEL CORPORATION (USA)
Inventor
  • Yao, Yizhi
  • Chou, Joey

Abstract

This disclosure describes systems, methods, and devices related to an intelligent evaluator. A device may decode a request from a service consumer for a creation of a first managed object instance (MOI) specifically intended for machine learning (ML) entity testing. The device may encode a response to the service consumer, wherein the response comprises an indication of whether the request for MOI creation is accepted. The device may initiate the ML entity testing upon acceptance of the request. The device may create a second MOI for the ML entity testing report upon completion of the ML entity testing. The device may encode a notification to the service consumer regarding the creation of this second MOI.

IPC Classes  ?

98.

APPARATUS, METHOD, DEVICE AND MEDIUM FOR DYNAMIC BALANCE ABILITY EVALUATION

      
Application Number CN2022108182
Publication Number 2024/020838
Status In Force
Filing Date 2022-07-27
Publication Date 2024-02-01
Owner INTEL CORPORATION (USA)
Inventor
  • Liu, Zhongxuan
  • Lu, Ming
  • Cai, Dongqi
  • Wang, Zhigang
  • Zhao, Hao
  • Zhang, Xu
  • Chen, Yurong

Abstract

The disclosure provides an apparatus, method, device, and medium for dynamic balance ability evaluation. The apparatus includes interface circuitry configured to receive a sequence of video frames including pose information of a person; and processor circuitry coupled to the interface circuitry and configured to extract the pose information from the sequence of video frames; determine one or more pose features for each video frame based on the pose information; identify different phases of motion of the person based on the one or more pose features for each video frame; obtain a plurality of indices for the dynamic balance ability evaluation based on the one or more pose features for each video frame or the different phases of motion of the person; and evaluate the dynamic balance ability of the person based on each index and a corresponding threshold.

IPC Classes  ?

  • G06T 7/20 - Analysis of motion
  • A63B 22/06 - Exercising apparatus specially adapted for conditioning the cardio-vascular system, for training agility or co-ordination of movements with rotating cycling movement
  • A61B 5/00 - Measuring for diagnostic purposes ; Identification of persons

99.

APPARATUS, METHOD, SYSTEM, AND STORAGE MEDIUM FOR DEEP LEARNING OPERATION ON WORKLOADS WITH DYNAMIC SHAPES

      
Application Number CN2022120027
Publication Number 2024/021266
Status In Force
Filing Date 2022-09-20
Publication Date 2024-02-01
Owner INTEL CORPORATION (USA)
Inventor
  • Qin, Zhennan
  • Cui, Jingze
  • Mei, Yijie
  • Li, Jianhui

Abstract

The application provides an apparatus, method, system and storage medium for a deep learning operation on workloads with dynamic shapes. The apparatus includes interface circuitry configured to obtain a profile of tensor shapes; and processing circuitry coupled to the interface circuitry and configured to: infer, from the profile of tensor shapes, a profile of parallel index ranges and a probability for each of the parallel index ranges; determine a set of candidate blocking factors for each of the parallel index ranges; and generate a kernel for the deep learning operation under each of the candidate blocking factors, the kernel for the operation comprising a parallel outer loop and an inner loop with a single-core kernel implementing a part of the deep learning operation working on corresponding parts of the workloads.

IPC Classes  ?

100.

COLLISION HANDLING IN AND HARQ-ACK CODEBOOK GENERATION FOR SIDELINK CARRIER AGGREGATION

      
Application Number US2023026852
Publication Number 2024/025707
Status In Force
Filing Date 2023-07-03
Publication Date 2024-02-01
Owner INTEL CORPORATION (USA)
Inventor
  • Xiong, Gang
  • Talarico, Salvatore
  • Roth, Kilian, Peter, Anton

Abstract

An apparatus and system of supporting sidelink carrier aggregation are described. Mechanisms for Type 1 and Type 2 sidelink hybrid automatic repeat request - acknowledgement (HARQ-ACK) codebook generation for carrier aggregation are described. A sidelink carrier index is included in downlink control information (DCI) format 3 0 received by a user equipment. The sidelink carrier index indicates the sidelink carrier used for resource allocation of a physical sidelink shared channel (PSSCH) and physical sidelink control channel (PSCCH). The HARQ-ACK for a sidelink serving cell is generated and the sidelink HARQ-ACK information bits are concatenated in accordance with ascending order of sidelink serving cell index. Collision handling and prioritization among sidelink transmissions and reception, as well as uplink transmissions during sidelink carrier aggregation are described.

IPC Classes  ?

  • H04W 72/56 - Allocation or scheduling criteria for wireless resources based on priority criteria
  • H04W 72/25 - Control channels or signalling for resource management between terminals via a wireless link, e.g. sidelink
  • H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
  • H04L 1/18 - Automatic repetition systems, e.g. Van Duuren systems
  • H04L 5/00 - Arrangements affording multiple use of the transmission path
  • H04W 72/04 - Wireless resource allocation
  • H04W 52/28 - TPC being performed according to specific parameters using user profile, e.g. mobile speed, priority or network state, e.g. standby, idle or non-transmission
  • H04W 92/18 - Interfaces between hierarchically similar devices between terminal devices
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