The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.
In one example, an eyepiece has a one-piece shape that is solid and rotationally asymmetric. The eyepiece includes first, second and third surfaces at least partially defining the one-piece shape. The first surface is configured to receive a spatially modulated light beam. The second surface is configured to internally reflect the spatially modulated light beam toward the third surface. The third surface is configured to reflect the spatially modulated light beam toward and through the second surface. Transmission of the spatially modulated light beam through the second surface concentrates the spatially modulated light beam.
Described embodiments include an integrated circuit for temperature gradient compensation of a bandgap voltage. A bandgap core circuit has a bandgap feedback input, a bandgap adjustment input and a bandgap reference output. A resistor is coupled between the bandgap adjustment input and a ground terminal. An offset and slope correction circuit has an offset correction output that is coupled to the bandgap adjustment input. A signal at the offset correction output is trimmed at an ambient temperature. A thermal error cancellation (TEC) circuit has a TEC output coupled to the bandgap adjustment input. The TEC circuit includes first and second temperature sensors that are located apart from each other. A signal at the TEC output is responsive to temperatures at the first and second temperature sensors. An amplifier has an amplifier input and an amplifier output. The amplifier input is coupled to the bandgap reference output.
A method for luma-based chroma intra-prediction in a video encoder or a video decoder is provided that includes down sampling a first reconstructed luma block of a largest coding unit (LCU), computing parameters α and β of a linear model using immediate top neighboring reconstructed luma samples and left neighboring reconstructed luma samples of the first reconstructed luma block and reconstructed neighboring chroma samples of a chroma block corresponding to the first reconstructed luma block, wherein the linear model is PredC[x,y]=α·RecL′[x,y]+β, wherein x and y are sample coordinates, PredC is predicted chroma samples, and RecL′ is samples of the down sampled first reconstructed luma block, and wherein the immediate top neighboring reconstructed luma samples are the only top neighboring reconstructed luma samples used, and computing samples of a first predicted chroma block from corresponding samples of the down sampled first reconstructed luma block using the linear model and the parameters.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/59 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.
An electronic device includes a multilevel metallization structure, a semiconductor die, and a package structure. The multilevel metallization structure has multiple levels of conductive metal traces and vias and polyimide insulator material, including a first level along a first side and a final level along a second side. The first level includes conductive metal leads with exposed surfaces along the first side, and the final level includes conductive metal pads with exposed surfaces along the second side. The semiconductor die is flip chip attached to the first side of the multilevel metallization structure with conductive features connected to respective conductive metal pads of the final level of the multilevel metallization structure, and the package structure encloses the semiconductor die and portions of the first side of the multilevel metallization structure.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
Non-transitory computer-readable mediums and systems are provided in which a portion of each chirp of a series of chirps is held at an offset frequency for a period of time, and in which the offset frequency, the period of time or both is varied or dithered across the chirps of the series of chirps. The portion of a chirp that is held at an offset frequency for a period of time may be a non-active portion of the chirp, during which the chirp is not sampled. In some implementations, the portion of a chirp that is held at an offset frequency for a period of time is during a falling portion of the chirp, which may be at the beginning of the falling portion, or at the end of the falling portion immediately before a rise portion of a succeeding chirp.
G01S 7/28 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of pulse systems
G01S 7/35 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group - Details of non-pulse systems
A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
9.
SEMICONDUCTOR PACKAGE WITH TOP CIRCUIT AND AN IC WITH A GAP OVER THE IC
A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.
An apparatus includes a spatial light modulator (SLM) having a first region and a second region and a phase light modulator (PLM) optically coupled to the SLM. The PLM is configured to receive first light having a first color and receive second light having a second color, the second color different than the first color. The PLM is also configured to direct the first light towards the first region of the SLM and direct the second light towards the second region of the SLM.
G02F 1/29 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the position or the direction of light beams, i.e. deflection
An error amplifier includes a first transistor having a first error amplifier input and having first and second current terminals, a second transistor having a second error amplifier input and having third and fourth current terminals, a first resistor coupled between a supply voltage terminal and the first current terminal, and a second resistor coupled between the supply voltage terminal and the third current termina. The error amplifier has a second stage circuit coupled to the first and second resistors. The second stage circuit has an error amplifier output. The second stage circuit is configured to cause less current to flow through the second stage circuit than a current that flows through either of the first or second resistors or the first or second transistors.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
12.
SWITCHED CAPACITOR INTEGRATOR CIRCUIT WITH REFERENCE, OFFSET CANCELLATION AND DIFFERENTIAL TO SINGLE-ENDED CONVERSION
A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.
G06G 7/184 - Arrangements for performing computing operations, e.g. amplifiers specially adapted therefor for integration or differentiation using capacitive elements
13.
VERTICAL HIGH CURRENT HALL SENSOR WITH INTEGRATED HEAT SLUG CURRENT LOOP POWER PAD
An electronic device includes a metal heat slug, a semiconductor die, and a package structure. The metal heat slug has a first portion, a second portion, and a third portion, the second portion is spaced apart from the first portion, and the third portion connects the first and second portions. The semiconductor die is attached to the third portion of the metal heat slug to measure a current of the third portion of the metal heat slug, and the package structure encloses the semiconductor die and the third portion of the metal heat slug and exposes sides of the first and second portions of the metal heat slug.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
The present disclosure generally relates to semiconductor processing in which an alignment mark is formed. An example is method of semiconductor processing. First and second recesses are formed in a semiconductor substrate. A conformal dielectric layer is formed in the first and second recesses and over the semiconductor substrate. A fill material is formed over the conformal dielectric layer in the first recess and over the conformal dielectric layer in the second recess. The fill material fills at least the first recess over the conformal dielectric layer. The fill material in the first and second recesses is recessed to below a top surface of the conformal dielectric layer. The recessed fill material in the first and second recesses is etched. Exposed portions of the conformal dielectric layer are etched. The second recess including the conformal dielectric layer and the recessed fill material disposed therein forms an alignment mark.
A positive overshoot detection circuit comprises a transistor coupled to a current mirror, a reference current source coupled to the current mirror, and a comparator coupled to the reference current source and the current mirror. The comparator output indicates whether the current mirror's current is greater than the reference current source's current. A control input and a current terminal of the transistor are coupled to a clamping circuit. A negative overshoot detection circuit comprises a biasing sub-circuit coupled to a transistor, a resistor coupled to the transistor, and a comparator coupled to the transistor and the resistor. The comparator output indicates whether the transistor is in an on or off state. The biasing sub-circuit is coupled to a clamping circuit. In some implementations, the comparator outputs from the positive and negative overshoot detection circuits are provided to a driver circuit, which modifies its operation.
An example device includes an analog comparator circuitry having a first input configured to couple to an input voltage and a second input configured to couple to a reference voltage, the analog comparator circuitry configured to output a digital value corresponding to a difference between the input voltage and the reference voltage and output sampler circuitry configured to: produce a plurality of samples of the difference, and count the number of samples in which the input voltage is greater than the reference voltage. The example device also includes reference adaption circuitry configured to: determine, based on the count, whether to adjust the reference voltage; responsive to a determination to adjust the reference voltage, determine, based on the count, an amount of adjustment; and responsive to a determination not to adjust the reference voltage, provide an indication of the reference voltage to processor circuitry.
One example includes a passive radar receiver system including an RF receiver front-end to receive a wireless source signal and a reflected signal. An antenna switch of the front-end switches a first antenna to a receiver chain during a first time to generate first radar signal data based on a combined wireless signal comprising wireless source signal and the reflected signal, and switches a second antenna to the receiver chain during a second time to generate second radar signal data based on the combined wireless signal. A signal processor generates source signal data associated with the wireless source signal based on the first and second radar signal data and generates reflected signal data associated with the reflected signal based on the first and second radar signal data, and generates target radar data associated with a target based on the source and reflected radar signal data.
G01S 1/04 - Beacons or beacon systems transmitting signals having a characteristic or characteristics capable of being detected by non-directional receivers and defining directions, positions, or position lines fixed relatively to the beacon transmitters; Receivers co-operating therewith using radio waves - Details
G01S 19/25 - Acquisition or tracking of signals transmitted by the system involving aiding data received from a cooperating element, e.g. assisted GPS
G01S 19/30 - Acquisition or tracking of signals transmitted by the system code related
A user client device with a single receive (RX) chain, a first antenna and a second antenna, and a processor that causes the user client device to couple the single RX chain to the first antenna to receive a first data packet on a first channel and determine a first channel state information (CSI) tile of the first channel based on one or more fields in the first data packet, decouple the first antenna from the single RX chain and couple the second antenna to the single RX chain to continue receiving the first data packet on a second channel, determine a second CSI tile of the second channel based on one or more of a portion of the first plurality of fields, aggregate the first CSI tile with the second CSI tile, and generate a CSI matrix based on aggregating the first CSI tile with the second CSI tile.
H04B 7/06 - Diversity systems; Multi-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.
In one example, an apparatus comprises a power stage having a first power stage input, a second power stage input, and a power stage output. The apparatus also comprises a modulator circuit having a first ramp input, a second ramp input, a modulator input, a first modulator output, and a second modulator output, the first modulator output coupled to the first power stage input, and the second modulator output coupled to the second power stage input. The apparatus also comprises a multi-level ramp generator having a first ramp output and a second ramp output, the first ramp output coupled to the first ramp input, and the second ramp output coupled the second ramp input.
H03K 4/08 - Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
H03F 3/217 - Class D power amplifiers; Switching amplifiers
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
22.
DELAYED SNOOP FOR IMPROVED MULTI-PROCESS FALSE SHARING PARALLEL THREAD PERFORMANCE
Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/084 - Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
H03M 13/01 - Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
23.
CHANNEL STOP AND WELL DOPANT MIGRATION CONTROL IMPLANT FOR REDUCED MOS THRESHOLD VOLTAGE MISMATCH
A channel stop and well dopant migration control implant (e.g., of argon) can be used in the fabrication of a transistor (e.g., PMOS), either around the time of threshold voltage adjust and well implants prior to gate formation, or as a through-gate implant around the time of source/drain extension implants. With its implant depth targeted about at or less than the peak of the concentration of the dopant used for well and channel stop implants (e.g., phosphorus) and away from the substrate surface, the migration control implant suppresses the diffusion of the well and channel stop dopant to the surface region, a more retrograde concentration profile is achieved, and inter-transistor threshold voltage mismatch is improved without other side effects. A compensating through-gate threshold voltage adjust implant (e.g., of arsenic) or a threshold voltage adjust implant of increased dose can increase the magnitude of the threshold voltage to a desired level.
Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
H04N 19/60 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
In some examples, a method includes determining, during a boot sequence of a controller, a hash value for data of a block of a flash storage device, the block including executable code, determining a bit pattern based on a randomly generated number, extracting a subset of data bits of the hash value according to the bit pattern to obtain a snippet, and storing the snippet to a secure storage device.
An apparatus includes a safety fault interrupter circuit. The safety fault interrupter circuit includes a safety fault monitor coupled to a first bias node and configured to selectively assert a fault interrupter signal based at least in part on a first bias voltage and a first power consumption. The safety fault interrupter circuit also includes a power fault monitor for the safety fault monitor, wherein the power fault monitor is coupled to a second bias node and is configured to selectively assert the fault interrupter signal based at least in part on a second bias voltage and a second power consumption that is less than the first power consumption.
G01R 31/327 - Testing of circuit interrupters, switches or circuit-breakers
H02H 3/16 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to fault current to earth, frame or mass
H02H 3/33 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points in different conductors of a single system, e.g. of currents in go and return conductors using summation current transformers
A CNN based-signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.
Devices, systems, and methods detect an image frame freeze condition. An example device includes a core logic circuit configured to generate statistics for received image data associated with an image frame, perform a census transform on pixel values of the image data to generate census transformed data, arrange the census transformed data into a binary string having a binary value, and generate transformed image data by replacing a select pixel value of the pixel values of the image data with a decimal value corresponding to the binary value; a load/store engine (LSE) coupled to the core logic circuit, the LSE configured to determine a cyclic redundancy check (CRC) value based on at least one of the image data, the transformed image data, and at least one statistic of the statistics; and an interface configured to transmit the CRC value to a host device.
In one example, an apparatus comprises: a first switch and a second switch coupled between a fuse terminal and a ground terminal, the first switch having a first switch control terminal, the second switch having a second switch control terminal; and a driver circuit having a control input, a first control output, and a second control output, the control input coupled to the fuse terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.
H02H 7/20 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from norm for electronic equipment
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
30.
VERTICAL DEEP TRENCH AND DEEP TRENCH ISLAND BASED DEEP N-TYPE WELL DIODE AND DIODE TRIGGERED PROTECTION DEVICE
A semiconductor device which includes two or more integrated deep trench features configured as a Zener diode. The Zener diode includes a plurality of deep trenches extending into semiconductor material of the substrate and a dielectric deep trench liner that includes a dielectric material. The deep trench further includes a doped sheath contacting the deep trench liner and an electrically conductive deep trench filler material within the deep trench. The doped sheath of adjacent deep trenches overlap and form a region of higher doping concentration which sets the breakdown voltage of the Zener diode. The Zener diode can be used as a triggering diode to limit the voltage on other components in a semiconductor device.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
A circuit includes a first transistor having first and second current terminals and a first control input, and a second transistor having third and fourth current terminals and a second control input. The third current terminal is coupled to the second current terminal at an intermediate node. In some cases, a third transistor is connected to the intermediate node to bias the intermediate rather than letting the intermediate node float. In other cases, a capacitor is connected to the intermediate node to reduce a negative voltage that might otherwise be present on the intermediate node.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
32.
METHOD AND APPARATUS FOR MATCHED BUFFER DECOMPRESSION
A circuit includes a first clock having a first clock output and a second clock having a second clock output. The circuit also includes a first buffer having a first buffer input, a second buffer input, and a first buffer output, the second buffer input coupled to the first clock output and a second buffer having a third buffer input, a fourth buffer input, and a second buffer output, the third buffer input coupled to the first buffer output and the fourth buffer input coupled to the second clock output. Additionally, the circuit includes a first element of data memory having a first data input and a first data output, the first data input coupled to the first buffer output and a second element of data memory having a second data input and a second data output, the second data input coupled to the second buffer output.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 5/395 - Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
G09G 5/399 - Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
H03M 7/30 - Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.
H03L 7/08 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop
H03L 7/083 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop the reference signal being additionally directly applied to the generator
H03L 7/091 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/10 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
34.
Secured scan access for a device including a scan chain
A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.
G01R 31/00 - Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
An apparatus includes a first camera configured to capture a first image being displayed, a second camera configured to capture a second image being displayed, and a processor configured to generate a pair-wise homography transform for the first camera and the second camera, and map, based on the pair-wise homography transform, the second image from a second frame of reference of the second camera to a first frame of reference of the first camera. The processor is further configured to determine a first corrected quadrilateral for the first image and a second corrected quadrilateral for the second image in the first frame of reference, and project, based on the pair-wise homography transform, the second corrected quadrilateral from the first frame of reference to the second frame of reference. The quadrilaterals are then processed to warp respective images for geometric correction before projecting the images by respective projectors.
A technique for rendering an under-vehicle view including obtaining a first location of a vehicle, the vehicle having a set of cameras disposed about the vehicle, capturing a set of images; storing images of the set of images in a memory, wherein the images are associated with a time the images were captured, moving the vehicle to a second location, obtaining the second location of the vehicle, determining an amount of time for moving the vehicle from the first location to the second location, generating a set of motion data, the motion data indicating a relationship between the second location of the vehicle and the first location of the vehicle, obtaining one or more stored images from the memory based on the determined amount of time, rendering a view under the vehicle based on the one or more stored images and set of motion data, and outputting the rendered view.
B60R 1/00 - Optical viewing arrangements; Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles
G06T 3/00 - Geometric image transformation in the plane of the image
G06T 3/40 - Scaling of a whole image or part thereof
G06T 7/70 - Determining position or orientation of objects or cameras
G06T 7/80 - Analysis of captured images to determine intrinsic or extrinsic camera parameters, i.e. camera calibration
G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation
G06V 10/80 - Fusion, i.e. combining data from various sources at the sensor level, preprocessing level, feature extraction level or classification level
G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
37.
TWO-WAY DESCRIPTOR MATCHING ON DEEP LEARNING ACCELERATOR
A hardware accelerator is configured to perform matrix multiplication and/or additional operations to optimize keypoint matching. A sum of squared error (SSE) calculation may be determined by utilizing the hardware accelerator to perform matrix multiplication to obtain a cost matrix for two sets of keypoint descriptors from two images. The hardware accelerator may determine a best cost calculation for each keypoint in each direction, which is utilized to perform keypoint matching.
A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 15/76 - Architectures of general purpose stored program computers
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
39.
INTEGRATED CIRCUIT WITH DEBUGGER AND ARBITRATION INTERFACE
Circuits, systems and methods are provided. A circuit includes a subsystem, an interface, and a debugger. The interface includes power processing and management (PPM) circuitry coupled to the subsystem, and arbitration logic coupled to the PPM circuitry. In operation, the debugger issues a debug request to the arbitration logic to perform a debug operation on the subsystem, and, in response to the debug request, the arbitration logic provides an interrupt associated with the subsystem to the PPM circuitry. The PPM circuitry, in response to the interrupt and a determination that the subsystem is OFF, powers on the subsystem and provides a notification to the arbitration logic indicating that the subsystem is ON. The PPM circuitry also receives a notification from the arbitration logic that the debug operation related to the debug request is complete, and powers off the subsystem in response to that notification.
In one example, an apparatus comprises: a primary side bridge coupled between a power input and a first ground terminal, the primary side bridge having first switching terminals coupled to first capacitor terminals; and a secondary side bridge coupled between a power output and a second ground terminal, the secondary side bridge having second switching terminals coupled to second capacitor terminals.
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G01D 11/00 - Component parts of measuring arrangements not specially adapted for a specific variable
H02J 50/05 - Circuit arrangements or systems for wireless supply or distribution of electric power using capacitive coupling
Techniques are described herein to enhance capability of floating level translators. For example, increased headroom is accomplished by adaptively bypassing the protection elements of the voltage level translator. In an example, a floating level translator can translate an input signal from a low-voltage domain to a high-voltage domain. A bypass circuit is coupled across the protection elements. The bypass circuit selectively engages during low-voltage operation (e.g., thereby providing a lower loss path relative to loss caused by the high-voltage protection elements and thus increasing the headroom swing), and disengages responsive to the high-voltage reference rail of the high-voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low-voltage domain power rail). The bypass circuit can be implemented in a relatively low-complexity manner (e.g., back-to-back high-voltage FETs) without additional signals to control low-voltage capability.
A pulse width modulator circuit with circuitry for providing a first and second pulse width modulation signal with dead time periods between the first and second pulse width modulation signals, an input for receiving a signal representative of a current in a load adapted to be driven in response to the first and second pulse width modulation signals, and circuitry coupled to the input for adjusting the dead time periods in response to the signal representative of a current.
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/5395 - Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
43.
"WEAK" UNDRIVEN STATE MODELLING FOR POWER MANAGEMENT VERIFICATION
A “weak” undriven state is defined as a signal state, distinguished from conventional unknown and high impedance states, and methods of representing this “weak” undriven state in circuit modelling and power aware digital/mixed-signal simulations for comprehensive and complete RTL-level design verification. The conventional unknown state refers to a circuit element that is powered but has an unknown value, a circuit element that is not powered, or a circuit element having an undriven, floating signal. The unknown state is modified, and the “weak” undriven state refers to a circuit element that is not powered and has an unknown value. The “weak” undriven state can have an electrically high impedance to known supply or ground when no other circuit element is active. The “weak” undriven state distinction is particularly useful to model and verify circuit designs known to be resilient to “weak” undriven states, using event driven logic circuit simulators.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
H03K 19/0948 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET using CMOS
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A float detector includes a latch and a float detection circuit. The latch includes a latch output and an input/output (I/O) terminal. The I/O terminal is coupled to an input terminal. The float detection circuit includes a detection input, a drive output, and a float detection circuit. The detection input is coupled to the latch output. The drive output is coupled to the I/O terminal. The float detector is configured to provide a drive signal at the drive output, and determine that the input terminal is floating based on a latch output signal received at the detection input responsive to the drive signal.
H01R 13/631 - Additional means for facilitating engagement or disengagement of coupling parts, e.g. aligning or guiding means, levers, gas pressure for engagement only
A circuit includes a load circuit and a voltage regulator circuit. The load circuit includes a load voltage input, a first transistor and a second transistor. The first transistor has a first threshold voltage, and the second transistor has a second threshold voltage. The voltage regulator circuit includes a load voltage output and a tracking circuit. The load voltage output is coupled to the load voltage input. The tracking circuit is configured to provide a load voltage at the load voltage output in which the load voltage tracks the first threshold voltage and the second threshold voltage.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
A method for automatic generation of calibration parameters for a surround view (SV) camera system is provided that includes capturing a video stream from each camera comprised in the SV camera system, wherein each video stream captures two calibration charts in a field of view of the camera generating the video stream; displaying the video streams in a calibration screen on a display device coupled to the SV camera system, wherein a bounding box is overlaid on each calibration chart, detecting feature points of the calibration charts, displaying the video streams in the calibration screen with the bounding box overlaid on each calibration chart and detected features points overlaid on respective calibration charts, computing calibration parameters based on the feature points and platform dependent parameters comprising data regarding size and placement of the calibration charts, and storing the calibration parameters in the SV camera system.
H04N 17/00 - Diagnosis, testing or measuring for television systems or their details
B60R 1/00 - Optical viewing arrangements; Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles
G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
H04N 7/18 - Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
47.
WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS
A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0806 - Multiuser, multiprocessor or multiprocessing cache systems
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0817 - Cache consistency protocols using directory methods
G06F 12/0853 - Cache with multiport tag or data arrays
G06F 12/0855 - Overlapped cache accessing, e.g. pipeline
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/0884 - Parallel mode, e.g. in parallel with main memory or CPU
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/121 - Replacement control using replacement algorithms
G06F 12/126 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
G06F 12/127 - Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
48.
AGING COMPENSATION OF A FERROELECTRIC PIEZOELECTRIC SHOCK SENSOR
A method comprises receiving a signal from a piezoelectric device and receiving a measurement of a temperature of the piezoelectric device. The method further comprises reading a first parameter from a memory, in which the first parameter depends on the temperature and relates the signal to an acceleration value and reading a second parameter from the memory, in which the second parameter represents a degree of drift of the piezoelectric device at the temperature. The method further comprises determining an acceleration of the piezoelectric device based on the signal, the first parameter, and the second parameter.
G01P 21/00 - Testing or calibrating of apparatus or devices covered by the other groups of this subclass
G01P 15/09 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by piezoelectric pick-up
49.
SAMPLE ADAPTIVE OFFSET PARAMETER DETERMINATION FOR VIDEO CODING
A method for sample adaptive offset (SAO) filtering in a video encoder is provided that includes estimating SAO parameters for color components of a largest coding unit (LCU) of a picture, wherein estimating SAO parameters includes using at least some non-deblock-filtered reconstructed pixels of the LCU to estimate the SAO parameters, performing SAO filtering on the reconstructed LCU according to the estimated SAO parameters, and entropy encoding SAO information for the LCU in a compressed video bit stream, wherein the SAO information signals the estimated SAO parameters for the LCU.
H04N 19/167 - Position within a video image, e.g. region of interest [ROI]
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
H04N 19/82 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
In examples, a semiconductor package comprises a conductive terminal; a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and a substrate coupled to the conductive terminal and to the device side of the semiconductor die. The substrate includes a first metal layer coupled to first and second vias extending toward and coupled to either the device side of the semiconductor die or the conductive terminal. The substrate includes a second metal layer electrically isolated from the first metal layer by an insulation layer between the first and second metal layers, the second metal layer coupled to a third via extending toward and coupled to either the conductive terminal or the semiconductor die. The first and second metal layers form a Marchand balun.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
A control circuit includes a timeout circuit configured to receive a first control signal. The timeout circuit asserts a timeout output signal on a timeout circuit output responsive to an expiration of a time period following assertion of the first control signal. A counter circuit has an input coupled to the timeout circuit output and has a counter circuit output. Responsive to assertion of the first control signal, the counter circuit selectively increments an output count value on the counter circuit output responsive to the timeout output signal having a first logic state or decrements the output count value on the counter circuit output responsive to the timeout output signal having a second logic state. A comparator circuit has a control input coupled to the counter circuit output. The comparator circuit adjusts a magnitude of a reference signal responsive to the output count value from the counter circuit.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
In one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. The method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
53.
METHODS AND APPARATUS FOR A SELF-CALIBRATING AND ADAPTIVE DISPLAY
An example apparatus comprising: a controller configured to: access a content brightness map; determine an amplitude of a light emitting diode (LED) current based on the content brightness map, a target brightness, or a target color temperature; determine a pulse width modulation (PWM) sequence based on the content brightness map, the target brightness, or the target color temperature; determine an LED PWM signal based on the content brightness map, the target brightness, the target color temperature, or the amplitude of the LED current; transmit a signal indicating the LED current to an LED; transmit the PWM sequence to a spatial light modulator (SLM); and transmit the LED PWM signal to the LED.
G09G 3/34 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix by control of light from an independent source
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
One example includes an integrated circuit with a sense amplifier that includes a first inverter having a first positive power terminal, a first input and a first output; and a second inverter having a second positive power terminal, a second input connected to the first output and a second output connected to the first input. The integrated circuit also includes a reference resistor connected between a positive voltage rail and the second positive power terminal. A fuse is connected between the positive voltage rail and the first positive power terminal.
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
55.
MULTIPLE PRIMARY NODES FOR WIRELESS BATTERY MANAGEMENT SYSTEM ROBUSTNESS
A system includes a first plurality of secondary devices, each secondary device of the first plurality of secondary devices including a first wireless transmitter and a battery monitor integrated circuit (IC). The battery monitor IC is configured to obtain battery data from at least one battery cell, and the first wireless transmitter is configured to wirelessly transmit the battery data. A first primary device has a second wireless transmitter wirelessly coupled to the first wireless transmitters of the first plurality of secondary devices via a first wireless network. A second primary device has a second wireless transmitter. The second primary device is configured to detect a fault with the first primary device and, in response detection of the fault, to establish a second wireless network with the first plurality of secondary devices.
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/396 - Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
A pulse generator circuit includes a charge pump having a charge pump output. A voltage divider is coupled to the charge pump output. The voltage divider has a voltage divider output. An error amplifier has a first error amplifier input and a second error amplifier input. The first error amplifier input is coupled to the voltage divider output. A dependent current source circuit has a first input coupled to the charge pump output, a second input coupled to the voltage divider output, and a third input coupled to the second error amplifier input. The dependent current source is configured to cause a current to flow from the charge pump output that is proportional to a difference between a first voltage at the voltage divider output and a second voltage at the second error amplifier input.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H02M 3/07 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies from a semiconductor wafer without using a blade. The methods include a plasma etch process utilizing metal structures formed on a back side of the wafer as masks to remove a portion of the semiconductor wafer from the back side. The portion removed by the plasma etch process corresponds to the scribe lines between the semiconductor dies. The plasma etch process terminates at a dielectric layer formed on a front side of the wafer. The dielectric layer may be severed to complete the separation process. Moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer that has been severed.
H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
58.
Tunable Fingertip Capacitors with Enhanced Shielding in Ceramic Package
An example semiconductor package comprises a ceramic header having a first open space separated from a second open space by a ceramic barrier. A first heat sink is attached to a bottom of the ceramic header below the first open area. A first integrated circuit (IC) die is mounted on the first heat sink. A second heat sink is attached to a bottom of the ceramic header below the second open area. A second IC die is mounted on the second heat sink. A capacitive interface is disposed in the ceramic barrier between the first IC die and the second IC die. The capacitive has a plurality of capacitive elements alternating with a plurality of shielding elements. The capacitive elements are tunable over a range of capacitive values.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/552 - Protection against radiation, e.g. light
59.
CONTRAST ENHANCEMENT VIA TIME-SEQUENTIAL PROJECTION OF SCENE CONTENT
A device includes at least one processor configured to partition a source image including image components into sub-images, each including a corresponding image component of the image components, and process each sub-image to produce a target image to be projected for each sub-image of the sub-images. The device also includes one or more light sources coupled to the at least one processor and configured to project an incident light, and a phase projection-based display device coupled to the at least one processor and optically coupled to the one or more light sources and configured to modulate, based on the target image of each sub-image, the incident light to separately project the sub-images.
In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
61.
IC FABRICATION FLOW WITH CONTINUOUS DYNAMIC SAMPLING FOR AUTO-VISUAL INSPECTION
A wafer metrology system having a continuous dynamic sampling scheme configured to optimize a sampling rate for AVI of process wafers in an IC fabrication flow based on acceptable quality levels. For a stable process, the process wafers may be sampled at a lower rate without negatively affecting quality control.
A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
In at least one example, a method includes establishing, by a sniffer provisioning server (SPS) of a first wireless device, a trusted relationship between the first wireless device and a sniffer tool using a public key of the sniffer tool. An out-of-band (OOB) key exchange provisions the public key of the sniffer tool to the wireless device. The method further includes obtaining, by the SPS, key material uniquely related to a communication session established between the first wireless device and a second wireless device using a shared password. The key material excludes the shared password and a session key uniquely related to the communication session. The method further includes publishing, by the SPS, the key material over a channel to the sniffer tool based on the trusted relationship. The channel is secured using the public key of the sniffer tool.
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
H04W 12/033 - Protecting confidentiality, e.g. by encryption of the user plane, e.g. user’s traffic
64.
ADAPTIVE FREQUENCY HOPPING IN A WIRELESS BATTERY MANAGEMENT SYSTEM
A method for channel switching by a secondary node. The method includes: receiving, from a primary node, a downlink transmission, measuring one or more statistics about the downlink transmission, determining, from the downlink transmission, an uplink interval, transmitting, to the primary node during the uplink interval, the measured one or more statistics about the downlink transmission, receiving, from the primary node, an indication of a set of useable channels, determining, based on the set of useable channels and at least one of the primary node or the secondary node, a next channel from the set of useable channels, and switching to the next channel based on a switch indication from the primary node.
H04B 1/713 - Spread spectrum techniques using frequency hopping
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.
A system includes a control circuit having a voltage input and a control circuit output. The control circuit produces a control voltage at the control circuit output having a magnitude inversely related to a magnitude of an input voltage at the input voltage input. A VCO has a VCO control input and a VCO clock output. The VCO control input is coupled to the control circuit output. The VCO produces a VCO clock on the VCO clock output having a frequency that is a function of the control voltage. A protection circuit has a first clock input, a second clock input, and a protection circuit output. The second clock input is coupled to the VCO clock output. The protection circuit generates a protection circuit output signal at the protection circuit output based on a difference in frequency between a clock signal at the first clock input and the VCO clock.
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/00 - Conversion of dc power input into dc power output
In at least one example, a method includes transmitting, by a first device, probe packets to a second device on multiple links over N transmission opportunities (TXOPs) with synchronous probing transmissions on the multiple links during each TXOP. N is an integer value greater than 1. Each probe packet corresponds to a different set of transmission parameters. Each link is established between the first device and the second device over different channels of a wireless transmission medium. The method further includes receiving, by the first device responsive to transmitting the probe packets, feedback from the second device on the multiple links in tandem with the synchronous probing transmissions over the N TXOPs. The method further includes selecting, by the first device, a preferred link from among the multiple links based on the feedback.
An example analog-to-digital converter (ADC) comprising: sample and hold circuitry coupled to an analog input; a first sub-ADC coupled to the sample and hold circuitry; a multiplying digital-to-analog converter (M-DAC) coupled to the first sub-ADC; summation circuitry coupled to the sample and hold circuitry and the M-DAC; an amplifier coupled to the summation circuitry; a second sub-ADC coupled to the amplifier; and reference generation circuitry coupled to the first sub-ADC, the M-DAC, and the second sub-ADC, the reference generation circuitry including: reference voltage circuitry coupled to the M-DAC; a first resistor coupled to the reference voltage circuitry; a second resistor coupled to the first resistor; and a capacitor coupled in parallel to the second resistor by a switch.
A digital-to-time converter circuit includes a scrambling and noise shaping circuit, a digital-to-analog converter (DAC), and a buffer circuit. The scrambling and noise shaping circuit includes an input and an output. The input is coupled to a delay input terminal. The scrambling and noise shaping circuit is configured to generate a residue value signal that scrambles and noise shapes a mismatch error. The DAC includes an input and an output. The input of the DAC is coupled to the output of the scrambling and noise shaping circuit. The DAC is configured to generate a residue timing signal based on the residue value signal that scrambles and noise shapes the mismatch error. The buffer circuit includes an input and an output. The input of the buffer circuit is coupled to the output of the DAC. The output of the buffer circuit is coupled to a signal output terminal.
In an example, a method includes connecting a first BLUETOOTH device to a second BLUETOOTH device via one or more links within a link cluster. The method also includes receiving a request at the first BLUETOOTH device from the second BLUETOOTH device to change one or more link connection parameters of a link within the link cluster. The method includes, responsive to receiving the request, changing the link connection parameter of the link within the link cluster.
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
71.
SYNCHRONOUS ALIGNMENT OF MULTIPLE HIGH-SPEED DIVIDERS
Timing alignment circuits for use in synchronizing output signals of high-speed dividers and other clock generators are provided. An example timing alignment circuit includes detection circuitry to receive first and second output signals, and output an error sign signal indicating whether the second output signal leads or lags the first output signal and a divide ratio slip signal. The example timing alignment circuit also includes control and aligning circuitry. The control circuitry receives a first local sync status signal and outputs a first control signal to a first component. The aligning circuitry receives the error sign signal and the divide ratio slip signal from the detection circuitry and also receives a second local sync status signal indicating when the first and second output signals are synchronized. The aligning circuitry outputs a second control signal to a second component that synchronously enables the output path receiving the clocks from different dividers with all rising edges aligned similar to a circuit exiting a synchronous reset.
H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/085 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
A microelectromechanical system (MEMS) switch implemented with a coplanar waveguide. The MEMS switch includes an input terminal, an output terminal. The MEMS switch includes a beam extending between the input terminal and the output terminal. The beam includes a first edge and a second edge coupled to a gate of the MEMS switch. The beam includes a third edge proximate the input terminal. The first edge includes a first set of finger contacts proximate a first corner of the beam and a second set of finger contacts proximate a second corner of the beam. The beam includes a fourth edge proximate the output terminal, the fourth edge opposing the third edge. The MEMS switch has a first anchor coupled to the input terminal. The first anchor includes a first segment extending from a region proximate the input terminal to a region overlying the first set of finger contacts.
A method for calibrating analog-to-digital conversion includes converting, by an analog-to-digital converter (ADC), a first input voltage to a first digital code. The first input voltage is generated from a reference voltage used as a reference voltage by the ADC. The method includes converting, by the ADC, a second input voltage to a second digital code. The second input voltage is generated from the reference voltage used as the reference voltage by the ADC. The method also includes calculating a calibration factor based on the first digital code, the second digital code, the first input voltage, and the second input voltage, converting, by the ADC, a third voltage to a third digital code, and correcting the third digital code using the calibration factor.
A BAW resonator includes first and second electrodes located over a substrate. A piezoelectric layer is located between the first and second electrodes. A guard ring is located between the piezoelectric layer and the second electrode, and is spaced apart from a perimeter of the electrode. The guard ring has a width in a range from 2.5 μm to 3.5 μm.
In an example, a wireless battery management system includes one or more sets of battery cells. The wireless battery management system includes a primary node configured to broadcast a downlink packet in a first superframe. The wireless battery management system also includes a first secondary node coupled to a first set of battery cells. The first secondary node is configured to receive the downlink packet and transmit a first uplink packet to the primary node during the first superframe. The wireless battery management system includes a second secondary node coupled to a second set of battery cells. The second secondary node is configured to receive the first uplink packet from the first secondary node in the first superframe. The second secondary node is also configured to transmit a second uplink packet to the primary node during a second superframe.
G01R 31/371 - Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] with remote indication, e.g. on external chargers
G01R 31/382 - Arrangements for monitoring battery or accumulator variables, e.g. SoC
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
A controller circuit is configured to receive a measurement signal representing a power converter state and receive a control signal representing a power converter resonant period. Based on the power converter state and the power converter resonant period, the controller circuit determines for a switching cycle: a charging interval, a first dead time interval, a discharging interval, and a second dead time interval. The first dead time interval is after the charging interval. The discharging interval is after the first dead time interval. The second dead time interval is after the discharging interval. The controller circuit provides a first drive signal and a second drive signal based on the charging interval, the first dead time interval, the discharging interval, and the second dead time interval.
H02M 1/38 - Means for preventing simultaneous conduction of switches
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
H02M 3/335 - Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
77.
METHODS AND APPARATUS FOR MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) DEVICES
Example methods, systems, and apparatus described herein provide a minimally invasive technique of controlling shape and stress in a MEMS device. An example method includes depositing a layer of material continuously across a semiconductor wafer, exposing the layer of material to oxygen plasma to increase a relative amount of oxygen within the layer of material; and etching the layer of material after exposing the layer of material to the oxygen plasma.
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
78.
COEXISTENCE PRIMITIVES IN POWER LINE COMMUNICATION NETWORKS
Systems and methods for setting a carrier-sensing mechanism in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets the carrier-sensing mechanism based on the preamble detection.
A radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. Other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. Processing circuitry performs a Fast Fourier Transform (FFT) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-Doppler array, and performs a FFT on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-Doppler array; identifies peaks in the first and second range-Doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-Doppler arrays to determine a measured phase shift between the two peaks.
A device including a host logic and a wireless controller. The wireless controller includes a transceiver and a scheduler. The scheduler is configured to determine a first device and a second device to cluster together. Further, upon occurrence of a communication event, the scheduler is configured to wakeup the transceiver for a period of time for the transceiver to exchange packets with the first and second devices, exchange a packet with the first device, exchange a packet with the second device, and power down the transceiver.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
A photovoltaic system with an inverter, at least one solar panel for providing electrical power, and electrical wiring for coupling electrical power from the at least one solar panel to the inverter. Also included is a transmitter for transmitting a messaging protocol along the electrical wiring, where the protocol includes a multibit wireline signal. Also included is circuitry for selectively connecting the electrical power from the at least one solar panel along the electrical wiring to the inverter in response to the messaging protocol.
H02S 50/00 - Monitoring or testing of PV systems, e.g. load balancing or fault identification
H02J 3/38 - Arrangements for parallelly feeding a single network by two or more generators, converters or transformers
H02J 3/46 - Controlling the sharing of output between the generators, converters, or transformers
H02S 40/32 - Electrical components comprising DC/AC inverter means associated with the PV module itself, e.g. AC modules
H02S 40/34 - Electrical components comprising specially adapted electrical connection means to be structurally associated with the PV module, e.g. junction boxes
82.
OPTIMIZING NODE LOCATION IN A BATTERY MANAGEMENT SYSTEM
A battery management system (BMS) is presented herein. The BMS has a master node. The master node includes a master transceiver and a controller communicably coupled to the master transceiver. The BMS has a plurality (n) of slave nodes. Each slave node of the n slave nodes includes a slave transceiver for communicably coupling to at least one battery monitor. The controller of the BMS is configured to direct the master transceiver to establish a communications network with the n slave nodes. To establish the communications network, the controller is also configured to respectively assign each of the n slave nodes to non-overlapping time slots of a superframe. The controller is further configured to direct the master transceiver to consecutively receive uplink (UL) transmissions from the n slave nodes in the non-overlapping time slots of the superframe.
Electrical balance duplexers (EBDs). An example EBD includes a differential TX port coupled to a first coil, a differential RX port coupled to a second coil, a differential ANT port coupled to a third coil, and a differential BAL port coupled to a fourth coil. In some cases, the first and second coils are arranged such that magnetic flux cancellation is achieved between the two, thus isolating the TX port from the RX port. In some cases, DC isolation exists between the coils. During operation, the first coil may electromagnetically couple with the third coil and the fourth coil, and the second coil may electromagnetically couple with the third coil and the fourth coil. In some example cases, the first and second coils are each in their own metallization layer, and the third and fourth coils are in the same layer.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
H04B 1/00 - TRANSMISSION - Details of transmission systems not characterised by the medium used for transmission
H03H 7/46 - Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
H04L 5/14 - Two-way operation using the same type of signal, i.e. duplex
An electronic system includes a repair MMR coupled with a first SRAM module within a plurality of SRAM modules coupled with each other in a daisy-chain configuration on a repair interface, and coupled with a last SRAM module within the plurality of SRAM modules via the repair interface. The electronic system also includes storage memory configured to store repair data for the plurality of SRAM modules and repair instructions, and processing circuitry. The processing circuitry is configured to, during boot up of the electronic system, read repair data for one or more of the plurality of SRAM modules from the storage memory, create serialized repair data for one or more the plurality of SRAM modules based on the repair instructions and the repair data, and to sequentially transmit the serialized repair data to the MMR.
A buffer circuit includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal is coupled to a load terminal. The control terminal is coupled to a preamplifier input terminal. The second transistor includes a first current terminal and a second current terminal. The first current terminal of the second transistor is coupled to the second current terminal of the first transistor. The third transistor includes a first current terminal, a second current terminal, and a control terminal. The first current terminal of the third transistor is coupled to the load terminal. The second current terminal of the third transistor is coupled to a ground terminal. The control terminal of the third transistor is coupled to second current terminal of the second transistor.
An electronic device includes a substrate having electrical circuits and/or electronic devices disposed thereon. Metal traces are formed on the substrate and include feet on each side of the metal traces that flare outward in opposite directions from each other where the metal traces overlie the substrate. A dielectric layer is formed on the substrate and a portion of the metal traces, and an interconnect is disposed on the metal traces.
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
Described embodiments include a circuit for filtering electromagnetic interference (EMI) that includes an electrically conductive housing enclosing the circuit, a first power terminal providing a first signal, and a second power terminal providing a second signal, the first and second signals forming a differential power input. A filter circuit provides a common mode noise cancelling signal at an output responsive to first and second inputs. An inductive choke has first and second coils that are magnetically coupled. The first coil is coupled between the first power terminal and a first converter input. The second coil is coupled between the second power terminal and a second converter input. A third capacitor is coupled between the filter output and the second power terminal. A fourth capacitor is coupled between the first power terminal and the second power terminal, and an inductor is coupled between the housing and a ground terminal.
Described embodiments include a circuit for temperature sensing having a first current source coupled to a diode input terminal. The first current source provides a first current at a first current output. A second current source provides a second current at a second current output. The second current is larger than the first current. A first switch is coupled between the second current source output and the diode input terminal. A capacitor is coupled between the diode input terminal and a temperature output terminal. A second switch is coupled between the temperature output terminal and a ground terminal. The temperature output terminal provides a temperature signal having a voltage that is proportional to a temperature of a component.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
89.
REDUCING SAMPLED AZ NOISE AND SAMPLED RESET NOISE IN SWITCHED CAPACITOR AMPLIFIERS
In at least one example, a circuit includes an amplifier, a first feedback loop, and a second feedback loop. The amplifier includes an amplifier input and an amplifier output. The first feedback loop includes a first feedback capacitor and a first switch. The first feedback loop is coupled between the amplifier input and the amplifier output. The first feedback capacitor is coupled to the amplifier output through the first switch. The second feedback loop includes a second feedback capacitor and a second switch. The second feedback loop is coupled in parallel with the first feedback loop between the amplifier input and the amplifier output. The second feedback capacitor is coupled to the amplifier input and to the first feedback capacitor through the second switch.
A bidirectional phase shifter includes a differential quadrature hybrid coupler, a switch network, and a differential reflection type phase shifter (RTPS). The differential quadrature hybrid coupler includes a first phase input/output (I/O) port, an inverse first phase I/O port, a second phase I/O port, and an inverse second phase I/O port. The switch network is coupled to the first phase I/O port, the inverse first phase I/O port, the second phase I/O port, and the inverse second phase I/O port. The differential RTPS including a differential I/O port coupled to the switch network.
H01P 1/185 - Phase-shifters using a diode or a gas filled discharge tube
H01P 5/18 - Conjugate devices, i.e. devices having at least one port decoupled from one other port consisting of two coupled guides, e.g. directional couplers
H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
91.
BLE LINK CLUSTER DISCOVERY, ESTABLISHING, AND TERMINATION
In an example, a method includes broadcasting advertising packets from a broadcaster BLUETOOTH device, where the advertising packets include one or more connection parameters for one or more links in a link cluster. The method also includes receiving, at the broadcaster BLUETOOTH device, a link cluster coordination request from a scanner BLUETOOTH device, where the link cluster coordination request includes one or more connection parameters for a link in the link cluster.
In examples, a method of manufacturing a semiconductor package comprises providing a lead frame having multiple conductive pins coupled thereto; positioning the lead frame within a mold chase and applying a strip of mold compound to the multiple conductive pins along a length of the lead frame; trimming connections between the lead frame and the multiple conductive pins; bending the multiple conductive pins; trimming the strip of mold compound to singulate the multiple conductive pins from each other and from the lead frame to form singulated conductive pins; coupling a singulated conductive pin from among the singulated conductive pins to a substrate such that a portion of the strip of mold compound coupled to the singulated conductive pin is in contact with the substrate and such that a segment of the singulated conductive pin extends vertically in a plane that is orthogonal to the substrate; coupling a semiconductor die to the substrate; and covering the substrate, the semiconductor die, the portion of the strip of mold compound, and part of the singulated conductive pin with a second mold compound, such that a portion of the segment of the singulated conductive pin extends beyond a top surface of the second mold compound.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
The present disclosure generally relates to a codeword format for data storage and to methods and circuits for generating a codeword based on data to be written in memory and extracting data from a codeword read from memory. In an example, an integrated circuit includes a memory system and a controller circuit. The controller circuit is communicatively coupled to the memory system and is configured to: receive multi-bit data; generate a codeword based on the multi-bit data; and transmit to the memory system the codeword for writing to memory. The codeword has a format that includes first bit positions for the multi-bit data, second bit positions for a bitwise inversion of the multi-bit data, a third bit position for an odd parity value, and a fourth bit position for an even parity value. The odd and even parity values indicate an odd and even parity, respectively, of the multi-bit data.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
Systems, apparatus, articles of manufacture, and methods are disclosed to detect a pace pulse in an electrocardiogram (ECG) signal. An example apparatus includes programmable circuitry configured to execute instructions to: identify a leading edge of a pulse in an input signal based on an amplitude change; identify a transition time of the leading edge of the pulse; validate the leading edge of the pulse based on the amplitude change and transition time; identify a trailing edge of the pulse; determine a width of the pulse between the leading edge and the trailing edge; and validate the pulse based on the width.
In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.
A method for uplink (UL) wireless backhaul communication at a wireless backhaul remote unit in a radio access network comprising receiving a configuration for radio frames and a transmission schedule through a downlink (DL) physical layer broadcast channel, wherein the transmission schedule comprises a transmission allocation for the remote unit, generating a UL data frame, wherein generating the UL data frame comprises performing forward error correction (FEC) encoding on a data bit stream to generate a plurality of FEC codewords, wherein performing the FEC encoding comprises performing Reed Solomon (RS) encoding on the data bit stream to generate a plurality of RS codewords, performing byte interleaving on the RS codewords, and performing Turbo encoding on the byte interleaved RS codewords to generate one or more Turbo codewords, wherein each Turbo codeword is encoded from more than one RS codeword, and transmitting the UL data frame according to the transmission allocation.
H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
Transaction mappers, methods and systems are provided. An example transaction mapper includes a table that associates virtual identification values with bus-device-function (BDF) values; and a firewall that receives an input-output request including a first virtual identification value of the virtual identification values, the first virtual identification value being associated with a function of an external peripheral, generates a first BDF value and a first traffic class value based on the table and the first virtual identification value, determine whether the first virtual identification value satisfies a threshold range, and determine whether to forward the input-output request to an external host device based on whether the first virtual identification value satisfies the threshold range.
A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
H03M 13/27 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
99.
CRACK ARREST FEATURES FOR MIULTILEVEL PACKAGE SUBSTRATE
An electronic device includes a multilevel package substrate, a semiconductor die mounted to the multilevel package substrate, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate. The multilevel package substrate has a first level, a second level, a first metal stack, and a second metal stack. The first metal stack includes a first set of contiguous metal structures of the first and second levels, the second metal stack includes a second set of contiguous metal structures of the first and second levels, the first and second metal stacks are spaced apart from one another, a first metal trace of the first metal stack partially overlaps a second metal trace of the second metal stack, and the first and second metal traces are in different levels of the multilevel package substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
100.
VARIABLE DELAY FIR FILTER FOR REFLECTION EQUALIZATION
In an example, a circuit includes a first signal path including a first filter having a first number of taps and having an input and an output. The circuit also includes a combiner having first and second inputs, the first input coupled to the output of the first filter. The circuit includes a second signal path coupled to the input of the first filter and to the second input of the combiner. The second signal path includes a gain component, a delay component coupled to the gain component, and a second filter having a second number of taps and coupled to the delay component.
H04B 1/7115 - Constructive combining of multi-path signals, i.e. RAKE receivers
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver