Applied Materials, Inc.

United States of America

Back to Profile

1-100 of 18,784 for Applied Materials, Inc. and 10 subsidiaries Sort by
Query
Aggregations
IP Type
        Patent 18,136
        Trademark 648
Jurisdiction
        United States 10,180
        World 8,546
        Europe 30
        Canada 28
Owner / Subsidiary
[Owner] Applied Materials, Inc. 16,848
Varian Semiconductor Equipment Associates, Inc. 1,271
Applied Materials Israel, Ltd. 556
Applied Materials Italia S.R.L. 83
Applied Materials GmbH & Co. KG 31
See more
Date
New (last 4 weeks) 166
2024 June (MTD) 107
2024 May 250
2024 April 137
2024 March 148
See more
IPC Class
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components 3,130
H01J 37/32 - Gas-filled discharge tubes 2,559
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof 2,366
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber 1,429
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping 1,238
See more
NICE Class
07 - Machines and machine tools 342
09 - Scientific and electric apparatus and instruments 326
37 - Construction and mining; installation and repair services 67
42 - Scientific, technological and industrial services, research and design 48
40 - Treatment of materials; recycling, air and water treatment, 41
See more
Status
Pending 2,282
Registered / In Force 16,502
  1     2     3     ...     100        Next Page

1.

LIFT ASSEMBLIES, AND RELATED METHODS AND COMPONENTS, FOR SUBSTRATE PROCESSING CHAMBERS

      
Application Number 18106155
Status Pending
Filing Date 2023-02-06
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Patil, Aniketnitin
  • Dhamodharan, Raja Murali
  • Salinas, Martin Jeffrey
  • Lau, Shu-Kwan

Abstract

The present disclosure relates to lift assemblies, and related methods and components, for substrate processing chambers. In one implementation, a lift assembly for disposition in relation to a substrate processing chamber includes a first motor, a first drive assembly coupled to the first motor, and a first support block coupled to the first drive assembly. The first motor is configured to linearly move the first support block using the first drive assembly. The lift assembly includes a second motor, a second drive assembly coupled to the second motor, and a second support block coupled to the second drive assembly. The second motor is configured to linearly move the second support block using the second drive assembly, and the second motor is configured to linearly move the second support block independently of the first motor linearly moving the first support block.

IPC Classes  ?

  • B23Q 3/10 - Auxiliary devices, e.g. bolsters, extension members
  • C30B 25/12 - Substrate holders or susceptors
  • C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure

2.

CONFINED CHARGE TRAP LAYER

      
Application Number 18425633
Status Pending
Filing Date 2024-01-29
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Kang, Chang Seok
  • Kitajima, Tomohiko
  • Balseanu, Mihaela A.

Abstract

Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

3.

APPARATUS, SYSTEMS, AND METHODS OF MEASURING EDGE RING DISTANCE FOR THERMAL PROCESSING CHAMBERS

      
Application Number 18587724
Status Pending
Filing Date 2024-02-26
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Luckner, Ole
  • Aderhold, Wolfgang R.

Abstract

Aspects of the present disclosure relate to apparatus, systems, and methods of measuring edge ring distance for thermal processing chambers. In one example, the distance measured is used to determine a center position shift of the edge ring.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G01B 11/02 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness
  • G01J 5/02 - Constructional details
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H05B 3/00 - Ohmic-resistance heating

4.

CAVITY SHAPING AND SELECTIVE METAL SILICIDE FORMATION FOR CMOS DEVICES

      
Application Number 18388043
Status Pending
Filing Date 2023-11-08
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Breil, Nicolas Louis
  • Gelatos, Avgerinos V.

Abstract

A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and a p-MOS cavity in an exposed surface of the p-MOS region, and performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 29/40 - Electrodes

5.

CONTACT LAYER FORMATION WITH MICROWAVE ANNEALING FOR NMOS DEVICES

      
Application Number 18387732
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Breil, Nicolas Louis
  • Aderhold, Wolfgang R.
  • Sharma, Shashank
  • Pradhan, Nilay Anil

Abstract

A method of forming an electrical contact in semiconductor structure includes performing a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer having a trench therewithin, the selective deposition process comprising epitaxially forming a contact layer on the semiconductor region within the trench of the dielectric layer, and performing a microwave anneal process to activate dopants in the epitaxially formed contact layer.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

6.

HDLC Data Reception Using Signal Pulse Widths

      
Application Number 18084202
Status Pending
Filing Date 2022-12-19
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Barua, Roshan K.
  • Norris, Gregg
  • Wang, Feng

Abstract

A system and method of receiving HDLC communications is disclosed. The system measures the pulse width of the incoming signal and converts each pulse into a series of bits, based on its pulse width. In this way, the reception of the HDLC communication is not dependent on any particular clock rate and is adaptable. The system takes advantages of the fact that the flag is a string of six consecutive bits that are all “1”. Thus, the longest positive pulse width may be used to determine the bit rate. This allows the system to operate over a very broad range of data rates.

IPC Classes  ?

  • H03K 7/08 - Duration or width modulation
  • H04J 3/24 - Time-division multiplex systems in which the allocation is indicated by an address

7.

METHOD FOR PRECISION OXIDATION CONTROL BY ION IMPLANTATION

      
Application Number 18084670
Status Pending
Filing Date 2022-12-20
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Charnvanichborikarn, Supakit
  • Lu, Cao-Minh Vincent
  • Gomez Herrero, Ana Cristina
  • Gossmann, Hans-Joachim Ludwig
  • Zou, Wei
  • Waite, Andrew Michael

Abstract

A method of processing a semiconductor substrate, including performing a first ion implantation process on the substrate, wherein a first ion beam formed of an ionized first dopant species is directed at a top surface of the substrate and is blocked from a first portion of the substrate while being allowed to implant a second portion of the substrate, and performing a second ion implantation process on the substrate, wherein a second ion beam formed of an ionized second dopant species is directed at the top surface of the substrate and is blocked from the first portion of the substrate while being allowed to implant the second portion of the substrate, wherein an effect of the second ion implantation process on an oxidation rate of the second portion counteracts an effect of the first ion implantation process on the oxidation rate of the second portion.

IPC Classes  ?

  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • C23C 14/04 - Coating on selected surface areas, e.g. using masks
  • C23C 14/48 - Ion implantation
  • H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
  • H01L 21/311 - Etching the insulating layers

8.

SURFACE TOPOLOGIES OF ELECTROSTATIC SUBSTRATE SUPPORT FOR PARTICLE REDUCTION

      
Application Number 18081388
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Chadha, Arvinder Manmohan Singh
  • Beaudry, Christopher

Abstract

A substrate support for use in a processing chamber to hold a substrate thereon includes a substrate support body, and a plurality of mesas on recessed surfaces of the substrate support body, wherein heights of the plurality of mesas from the recessed surfaces vary over the substrate support body between at least two different heights.

IPC Classes  ?

9.

LOW TEMPERATURE DEPOSITION OF IRIDIUM CONTAINING FILMS

      
Application Number 18590141
Status Pending
Filing Date 2024-02-28
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Liu, Feng Q.
  • Chung, Hua
  • Chu, Schubert
  • Chang, Mei
  • Anthis, Jeffrey W.
  • Thompson, David

Abstract

Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.

IPC Classes  ?

  • C23C 16/42 - Silicides
  • C23C 16/14 - Deposition of only one other metal element
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/507 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using external electrodes, e.g. in tunnel type reactors
  • C23C 16/513 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using plasma jets
  • C23C 16/52 - Controlling or regulating the coating process

10.

COMBINATION OF INLINE METROLOGY AND ON TOOL METROLOGY FOR ADVANCED PACKAGING

      
Application Number 18081751
Status Pending
Filing Date 2022-12-15
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor Mueller, Ulrich

Abstract

Aspects of the present disclosure generally relate to a digital lithography system and methods for alignment resolution with the digital lithography system. The digital lithography system includes a metrology system configured to improve overlay alignment for different layers of the lithography process. The metrology system includes an inline metrology system (IMS) in combination with an on tool metrology system (OTM), which enable substrate overlay alignment and die placement correction. The inline metrology system may be positioned on an inline metrology tool and the on tool metrology system is positioned on a digital lithography tool. The inline metrology system facilitates measurement of high-throughput measurement inline metrology data for marks such as die marks and global alignment marks for verification of process stability and die placement data for digital data correction. This inline metrology data can be compared with a design file to determine offsets for the digital data correction.

IPC Classes  ?

  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically

11.

LIFT ASSEMBLIES, AND RELATED METHODS AND COMPONENTS, FOR SUBSTRATE PROCESSING CHAMBERS

      
Application Number US2023035453
Publication Number 2024/129179
Status In Force
Filing Date 2023-10-18
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Patil, Aniketnitin
  • Dhamodharan, Raja Murali
  • Salinas, Martin Jeffrey
  • Lau, Shu-Kwan

Abstract

The present disclosure relates to lift assemblies, and related methods and components, for substrate processing chambers. In one implementation, a lift assembly for disposition in relation to a substrate processing chamber includes a first motor, a first drive assembly coupled to the first motor, and a first support block coupled to the first drive assembly. The first motor is configured to linearly move the first support block using the first drive assembly. The lift assembly includes a second motor, a second drive assembly coupled to the second motor, and a second support block coupled to the second drive assembly. The second motor is configured to linearly move the second support block using the second drive assembly, and the second motor is configured to linearly move the second support block independently of the first motor linearly moving the first support block.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C30B 25/10 - Heating of the reaction chamber or the substrate
  • C30B 25/12 - Substrate holders or susceptors
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

12.

CONTACT LAYER FORMATION WITH MICROWAVE ANNEALING FOR NMOS DEVICES

      
Application Number US2023078900
Publication Number 2024/129263
Status In Force
Filing Date 2023-11-07
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Breil, Nicolas Louis
  • Aderhold, Wolfgang R.
  • Sharma, Shashank
  • Pradhan, Nilay Anil

Abstract

A method of forming an electrical contact in semiconductor structure includes performing a selective deposition process on a semiconductor structure having a semiconductor region and a dielectric layer having a trench therewithin, the selective deposition process comprising epitaxially forming a contact layer on the semiconductor region within the trench of the dielectric layer, and performing a microwave anneal process to activate dopants in the epitaxially formed contact layer.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/24 - Deposition of silicon only
  • C23C 16/56 - After-treatment

13.

METHOD OF REDUCING METAL GATE RESISTANCE FOR NEXT GENERATION NMOS DEVICE APPLICATION

      
Application Number 18067979
Status Pending
Filing Date 2022-12-19
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Gandikota, Srinivas
  • Yang, Yixiong
  • Lin, Yongjing
  • Ailihumaer, Tuerxun
  • Ma, Tengzhou
  • Zheng, Yuanhua
  • Liu, Zhihui
  • Chen, Shih Chung
  • Devrajan, Janardhan
  • Xu, Yi
  • Lei, Yu
  • Sriram, Mandyam

Abstract

Methods of manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of the disclosure advantageously provide methods to reduce the resistance of the work function layer of an electronic device, as well as using a low resistivity metal for filling the gate.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched

14.

FAST GAS SWITCHING

      
Application Number 18083372
Status Pending
Filing Date 2022-12-16
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Tran, Toan
  • Wang, Yen-Kun
  • Wakabayashi, Reyn
  • Babayan, Steve
  • Wan, Wayne

Abstract

A system including a chamber enclosing a processing region, a substrate support within the chamber and configured to retain a substrate in the processing region, a gas distribution manifold coupled to the chamber to introduce first and a second etching gases from the gas distribution manifold using first and second inlets, a first gas distribution channel coupled configured to selectively switch between directing the first etching gas along a first gas flow path towards the processing region, and directing the first etching gas towards a vent, and a second gas distribution channel configured to selectively switch between directing the second etching gas towards the vent, and directing the second etching gas along a fourth gas flow path towards the processing region, and a flow ratio controller operatively coupled to the first and second gas distribution channels and configured to direct the first or second etching gases towards the processing region.

IPC Classes  ?

15.

APPARATUS AND METHOD FOR CONTACTLESS TRANSPORTATION OF A CARRIER

      
Application Number 18081493
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Meiss, Thorsten
  • Sendobry, Alexander

Abstract

An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.

IPC Classes  ?

  • H02N 15/00 - Holding or levitation devices using magnetic attraction or repulsion, not otherwise provided for

16.

VIBRATION SENSOR ASSEMBLY

      
Application Number 18081897
Status Pending
Filing Date 2022-12-15
First Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor Kode, Venkata Raghavaiah Chowdhary

Abstract

A system includes a controller, a substrate transfer device including one or more moveable members, and a vibration sensor assembly coupled to a member of the one or more moveable members. The vibration sensor assembly includes an accelerometer configured to detect vibration of the substrate transfer device and a processing device coupled to the accelerometer. The processing device is to receive vibration data from the accelerometer. The processing device is further to determine a vibration frequency peak of the vibration data. The vibration frequency peak corresponds to a critical frequency associated with the substrate transfer device. The processing device is further to determine that the vibration frequency peak exceeds a threshold magnitude, responsive to which the processing device is further to cause a data signal indicative of the vibration frequency peak to be transmitted to the controller.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B25J 11/00 - Manipulators not otherwise provided for
  • B25J 19/02 - Sensing devices
  • G01P 1/00 - MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION OR SHOCK; INDICATING PRESENCE OR ABSENCE OF MOVEMENT;  INDICATING DIRECTION OF MOVEMENT  - Details of instruments
  • G01P 15/00 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
  • G06F 3/14 - Digital output to display device
  • G08B 21/18 - Status alarms

17.

APPARATUS AND METHOD FOR CONTACTLESS TRANSPORTATION OF A CARRIER

      
Application Number 18500462
Status Pending
Filing Date 2023-11-02
First Publication Date 2024-06-20
Owner Applied Materials, Inc. (USA)
Inventor
  • Meiss, Thorsten
  • Sendobry, Alexander

Abstract

An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.

IPC Classes  ?

  • H02N 15/00 - Holding or levitation devices using magnetic attraction or repulsion, not otherwise provided for

18.

CAVITY SHAPING AND SELECTIVE METAL SILICIDE FORMATION FOR CMOS DEVICES

      
Application Number US2023079052
Publication Number 2024/129269
Status In Force
Filing Date 2023-11-08
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Breil, Nicolas Louis
  • Gelatos, Avgerinos V.

Abstract

A method of forming an electrical contact in a semiconductor structure includes performing a cavity shaping process on a semiconductor structures having an n-type metal oxide semiconductor (n-MOS) region and a p-type MOS (p-MOS) region, the cavity shaping process comprising forming an n-MOS cavity in an exposed surface of the n-MOS region and a p-MOS cavity in an exposed surface of the p-MOS region, and performing a first selective deposition process to form a p-MOS cavity contact, selectively in the p-MOS cavity.

IPC Classes  ?

  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

19.

COMBINATION OF INLINE METROLOGY AND ON TOOL METROLOGY FOR ADVANCED PACKAGING

      
Application Number US2023078375
Publication Number 2024/129253
Status In Force
Filing Date 2023-11-01
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor Mueller, Ulrich

Abstract

Aspects of the present disclosure generally relate to a digital lithography system and methods for alignment resolution with the digital lithography system. The digital lithography system includes a metrology system configured to improve overlay alignment for different layers of the lithography process. The metrology system includes an inline metrology system (IMS) in combination with an on tool metrology system (OTM), which enable substrate overlay alignment and die placement correction. The inline metrology system may be positioned on an inline metrology tool and the on tool metrology system is positioned on a digital lithography tool. The inline metrology system facilitates measurement of high-throughput measurement inline metrology data for marks such as die marks and global alignment marks for verification of process stability and die placement data for digital data correction. This inline metrology data can be compared with a design file to determine offsets for the digital data correction.

IPC Classes  ?

  • G03F 9/00 - Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
  • G03F 7/20 - Exposure; Apparatus therefor

20.

SURFACE TOPOLOGIES OF ELECTROSTATIC SUBSTRATE SUPPORT FOR PARTICLE REDUCTION

      
Application Number US2023035024
Publication Number 2024/129175
Status In Force
Filing Date 2023-10-12
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Chadha, Arvinder Manmohan Singh
  • Beaudry, Christopher

Abstract

A substrate support for use in a processing chamber to hold a substrate thereon includes a substrate support body, and a plurality of mesas on recessed surfaces of the substrate support body, wherein heights of the plurality of mesas from the recessed surfaces vary over the substrate support body between at least two different heights.

IPC Classes  ?

  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

21.

PHASE-RESOLVED OPTICAL METROLOGY FOR SUBSTRATES

      
Application Number US2023083581
Publication Number 2024/129700
Status In Force
Filing Date 2023-12-12
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Saleh, Nedal
  • Jiang, Zhiming
  • Zhang, Xiaodong
  • Srivatsa, Arun Ramaswamy

Abstract

The methods and apparatus provide phase-resolved optical metrology for determining qualities of a substrate and films thereon. Transmitted and reflected signals are coupled using both amplitude and phase information to improve the metrology information obtained from film layers on the substrate.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01N 21/35 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light
  • G01N 21/84 - Systems specially adapted for particular applications
  • G01N 21/88 - Investigating the presence of flaws, defects or contamination

22.

PHOTOMASK HANDLING ASSEMBLY FOR ATMOSPHERIC PRESSURE PLASMA CHAMBER

      
Application Number US2023083579
Publication Number 2024/129698
Status In Force
Filing Date 2023-12-12
Publication Date 2024-06-20
Owner
  • APPLIED MATERIALS, INC. (USA)
  • WU, Banqiu (USA)
Inventor Zimmerman, Nolan Layne

Abstract

An automatic photomask handling assembly is employed for holding a photomask for cleaning processes in an atmospheric pressure plasma (APP) chamber. The automatic photomask handling assembly includes a set of stationary standoffs with each of the stationary standoffs having a first end solidly mounted to the photomask handling assembly and a second end that contacts an underside of a photomask. The automatic photomask handling assembly also has a handling stage that holds the photomask for processing. The handling stage has a set of through openings that allow the set of stationary standoffs to pass through the handling stage as the handling stage moves vertically. The handling stage also has a set of plates that automatically clamp and unclamp a photomask as the handling stage moves vertically. The set of plates completely surrounds the photomask such that the clamped photomask and the set of plates form a continuous surface.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
  • G03F 1/80 - Etching

23.

ION EXTRACTION OPTICS HAVING NOVEL BLOCKER CONFIGURATION

      
Application Number US2023082708
Publication Number 2024/129469
Status In Force
Filing Date 2023-12-06
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Biloiu, Costel
  • Calkins, Adam
  • Rockwell, Tyler
  • Daniels, Kevin M.
  • Campbell, Christopher

Abstract

A processing system may include a plasma chamber and an extraction optics, disposed along a side of the plasma chamber. The extraction optics may include an extraction plate, having an outer side and an inner side, where the extraction plate defines at least one extraction aperture. The extraction optics may include a beam blocker, overlapping the at least one extraction aperture, and disposed towards the inner side of the extraction plate. The beam blocker may have a cross-section that defines a boomerang shape, and may comprise a first metallic material, where the extraction plate comprises a second metallic material. The processing system may further include a substrate platen, disposed outside of the plasma chamber, and movable along a scan direction with respect to the extraction aperture.

IPC Classes  ?

  • H01J 37/08 - Ion sources; Ion guns
  • H01J 37/04 - Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
  • H01J 37/09 - Diaphragms; Shields associated with electron- or ion-optical arrangements; Compensation of disturbing fields
  • H01J 37/305 - Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating, or etching
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

24.

OVERHANG PATTERN FOR ADVANCED OLED PATTERNING

      
Application Number US2023083899
Publication Number 2024/129902
Status In Force
Filing Date 2023-12-13
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lin, Yu-Hsin
  • Anjiki, Takashi
  • Chen, Chung-Chia
  • Jeong, Jae Wook
  • Choung, Ji Young
  • Lee, Jungmin

Abstract

Embodiments described herein relate to a device. The device includes a substrate, overhang structures disposed over the substrate, and a plurality of sub- pixels. Each overhang structure has a second structure disposed over a first structure. The second structure has an overhang extension extending laterally past the first structure. The first structure includes a first sidewall opposing a second sidewall. The first sidewall and the second sidewall are connected to each other. The plurality of sub-pixels each include an organic light-emitting diode (OLED) material, and a cathode disposed over the OLED material. The cathode extends under the overhang extension such that the cathode contacts the first sidewall and the second sidewall of the first structure under the overhang extension.

IPC Classes  ?

  • H10K 59/122 - Pixel-defining structures or layers, e.g. banks
  • H10K 59/80 - Constructional details
  • H10K 59/35 - Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
  • H10K 59/12 - Active-matrix OLED [AMOLED] displays
  • H10K 71/60 - Forming conductive regions or layers, e.g. electrodes
  • H10K 102/00 - Constructional details relating to the organic devices covered by this subclass

25.

CARRIER WITH ROTATION PREVENTION FEATURE

      
Application Number US2023083239
Publication Number 2024/129547
Status In Force
Filing Date 2023-12-08
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Cox, Damon K.
  • Gondihosalli, Manjunatha
  • Muthukamatchi, Karuppasamy

Abstract

A carrier includes a carrier body, fingers attached to the carrier body, and a rotation prevention component attached to the carrier body. The fingers are configured to support a process kit ring. The rotation prevention component is configured to be disposed proximate a flat inner surface of the process kit ring to prevent rotation of the process kit ring.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

26.

POST-TREATMENT FOR REMOVING RESIDUES FROM DIELECTRIC SURFACE

      
Application Number US2023083213
Publication Number 2024/129544
Status In Force
Filing Date 2023-12-08
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Tavakoli, Mohammad Mahdi
  • Gelatos, Avgerinos V.
  • Cen, Jiajie
  • Kashefi, Kevin
  • Lee, Joung Joo
  • Liu, Zhihui
  • Zhou, Yang
  • Wu, Zhiyuan
  • Wu, Meng-Shan

Abstract

A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 Å and 40 Å.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

27.

APPARATUS AND METHOD FOR CONTACTLESS TRANSPORTATION OF A CARRIER

      
Application Number US2023079455
Publication Number 2024/129278
Status In Force
Filing Date 2023-11-13
Publication Date 2024-06-20
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Meiss, Thorsten
  • Sendobry, Alexander

Abstract

An apparatus for contactless transportation of a carrier is provided. The apparatus includes the carrier, being a substrate carrier or a mask carrier. The apparatus includes a linear reluctance motor for providing both a contactless levitation and a contactless drive of the carrier. The linear reluctance motor includes one or more linear stators defining a transportation track for the carrier. The linear reluctance motor includes a mover attached to the carrier. The linear reluctance motor includes a set of electromagnets and a first magnetic material. The one or more linear stators include the set of electromagnets and the mover includes the first magnetic material, or the mover includes the set of electromagnets and the one or more linear stators include the first magnetic material. The apparatus includes a controller connected to the set of electromagnets.

IPC Classes  ?

  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • B65G 54/02 - Non-mechanical conveyors not otherwise provided for electrostatic, electric, or magnetic
  • B65G 49/06 - Conveying systems characterised by their application for specified purposes not otherwise provided for for fragile or damageable materials or articles for fragile sheets, e.g. glass

28.

Portion of a display panel with a graphical user interface

      
Application Number 29837666
Grant Number D1031743
Status In Force
Filing Date 2022-05-06
First Publication Date 2024-06-18
Grant Date 2024-06-18
Owner Applied Materials, Inc. (USA)
Inventor
  • Bhatia, Sidharth
  • Zhu, Zhaozhao
  • Au, Jeffrey Yat Shan
  • Levesque, Shawn
  • Howells, Michael
  • Jetti, Raja Sekhar

29.

MEDEOR

      
Application Number 1793754
Status Registered
Filing Date 2024-03-22
Registration Date 2024-03-22
Owner Applied Materials, Inc. (USA)
NICE Classes  ? 09 - Scientific and electric apparatus and instruments

Goods & Services

Semiconductor manufacturing software used to provide wafer doping uniformity.

30.

VERIDIAN

      
Application Number 1793755
Status Registered
Filing Date 2024-03-22
Registration Date 2024-03-22
Owner Applied Materials, Inc. (USA)
NICE Classes  ? 07 - Machines and machine tools

Goods & Services

Semiconductor wafer processing equipment for modifying film properties of substrates.

31.

CHELATING AGENTS FOR QUANTUM DOT PRECURSOR MATERIALS IN COLOR CONVERSION LAYERS FOR MICRO-LEDS

      
Application Number 18444277
Status Pending
Filing Date 2024-02-16
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Luo, Yingdong
  • Zhang, Daihua
  • Ng, Hou T.
  • Ganapathiappan, Sivapackia
  • Patibandla, Nag B.

Abstract

A photocurable composition includes quantum dots, quantum dot precursor materials, a chelating agent, one or more monomers, and a photoinitiator. The quantum dots are selected to emit radiation in a first wavelength band in the visible light range in response to absorption of radiation in a second wavelength band in the UV or visible light range. The second wavelength band is different than the first wavelength band. The quantum dot precursor materials include metal atoms or metal ions corresponding to metal components present in the quantum dots. The chelating agent is configured to chelate the quantum dot precursor materials. The photoinitiator initiates polymerization of the one or more monomers in response to absorption of radiation in the second wavelength band.

IPC Classes  ?

  • H01L 33/50 - Wavelength conversion elements
  • H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
  • H01L 33/30 - Materials of the light emitting region containing only elements of group III and group V of the periodic system

32.

METHODS AND APPLICATIONS OF NOVEL AMORPHOUS HIGH-K METAL-OXIDE DIELECTRICS BY SUPER-CYCLE ATOMIC LAYER DEPOSITION

      
Application Number 18555342
Status Pending
Filing Date 2021-04-22
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Sun, Zhelin
  • Huh, Kwang Soo
  • Zhao, Lai
  • Choi, Soo Yong

Abstract

Embodiments of the disclosure relate to articles and transistor structures and methods of preparation and use thereof, including a substrate and an amorphous oxide film overlaying at least a portion of the substrate, where the amorphous oxide film includes a first oxide and a second oxide. The first oxide can include zirconium oxide (ZrO2), hafnium oxide (HfO2) or a combination thereof, the second oxide can include silicon dioxide (SiO2), aluminum oxide (Al2O3), nitric oxide (NO) or combinations thereof. The amorphous oxide film can conformal and have a porosity of less than about 1% and may have a dielectric constant (k) of about 8 to about 28.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/786 - Thin-film transistors

33.

METAL BASED HYDROGEN BARRIER

      
Application Number 18581598
Status Pending
Filing Date 2024-02-20
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Gandikota, Srinivas
  • Hung, Steven C.H.
  • Nemani, Srinivas D.
  • Yang, Yixiong
  • Singha Roy, Susmit
  • Bekiaris, Nikolaos

Abstract

A method of forming an electronic device is disclosed. The method comprises forming depositing a metal on a substrate, the metal comprising one or more of copper (Cu), titanium (Ti), or tantalum (Ta). A metal cap is deposited on the metal. The metal cap comprises one or more of molybdenum (Mo), ruthenium (Ru), iridium (Ir), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), platinum (Pt), or gold (Au). The substrate is then exposed to an anneal process, e.g., a hydrogen high-pressure anneal. The formation of the metal cap on the metal minimizes parasitic adsorption of hydrogen by the underlying metal.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

34.

METHODS FOR CALIBRATING AN OPTICAL EMISSION SPECTROMETER

      
Application Number 18581626
Status Pending
Filing Date 2024-02-20
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Lo, Kin Pong
  • Hawrylchak, Lara
  • Bevan, Malcolm J.
  • Guarini, Theresa Kramer
  • Liu, Wei
  • Hwang, Bernard L.

Abstract

One or more embodiments described herein generally relate to systems and methods for calibrating an optical emission spectrometer (OES) used for processing semiconductor substrates. In embodiments herein, a light fixture is mounted to a plate within a process chamber. A light source is positioned within the light fixture such that it provides an optical path that projects directly at a window through which the OES looks into the process chamber for its reading. When the light source is on, the OES measures the optical intensity of radiation from the light source. To calibrate the OES, the optical intensity of the light source is compared at two separate times when the light source is on. If the optical intensity of radiation at the first time is different than the optical intensity of radiation at the second time, the OES is modified.

IPC Classes  ?

  • G01J 3/28 - Investigating the spectrum
  • G01J 3/02 - Spectrometry; Spectrophotometry; Monochromators; Measuring colours - Details
  • G01J 3/10 - Arrangements of light sources specially adapted for spectrometry or colorimetry
  • G01J 3/443 - Emission spectrometry

35.

BLUE COLOR CONVERTER FOR MICRO LED DEVICES

      
Application Number 18586175
Status Pending
Filing Date 2024-02-23
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Luo, Yingdong
  • Xu, Lisong
  • Ganapathiappan, Sivapackia
  • Ng, Hou T.
  • Kwak, Byung Sung
  • Zhu, Mingwei
  • Patibandla, Nag B.

Abstract

A display includes a light emitting diode and a color conversion layer that includes a polymer matrix, a blue photoluminescent material, and a components of a photoinitiator that initiated polymerization to form the polymer matrix. The blue photoluminescent material is selected to absorb ultraviolet light with a maximum wavelength in a range of about 300 nm to about 430 nm and to emit blue light. The blue photoluminescent material also has an emission peak in a range of about 420 nm to about 480 nm. The full width at half maximum of the emission peak is less than 100 nm, and the photoluminescence quantum yield is in a range of 5% to 100%.

IPC Classes  ?

  • H01L 33/50 - Wavelength conversion elements
  • C09K 11/02 - Use of particular materials as binders, particle coatings or suspension media therefor
  • C09K 11/06 - Luminescent, e.g. electroluminescent, chemiluminescent, materials containing organic luminescent materials
  • H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof

36.

AUTOMATED SUBSTRATE PLACEMENT TO CHAMBER CENTER

      
Application Number 18586310
Status Pending
Filing Date 2024-02-23
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor Aderhold, Wolfgang

Abstract

Embodiments disclosed herein include a method of centering a substrate in a chamber. In an embodiment, the method comprises inserting the substrate into the chamber with a robot arm, obtaining a delta time value for a second pyrometer relative to a first pyrometer, where the delta time value is a duration of time between when the first pyrometer is covered by the substrate and when the second pyrometer is covered by the substrate, calculating a time offset value of the delta time value relative to an ideal delta time value, where the ideal delta time value is the delta time value when the substrate is perfectly centered in a first direction perpendicular to the motion of the substrate, and comparing the time offset value to a graph or a lookup table that correlates the time offset value to a distance offset value.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B25J 11/00 - Manipulators not otherwise provided for
  • G05B 19/00 - Programme-control systems
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

37.

LEARNING BASED TUNING IN A RADIO FREQUENCY PLASMA PROCESSING CHAMBER

      
Application Number 18076725
Status Pending
Filing Date 2022-12-07
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Guo, Yue
  • Ramaswamy, Kartik
  • Yang, Yang

Abstract

Some embodiments are directed to a method of processing a substrate in a plasma processing system. The method generally includes tuning a first capacitor and a second capacitor of a tuning circuit to match a first impedance corresponding to a first stage of a waveform, while a frequency of a radio frequency (RF) generator is preset to a first frequency; tuning a third capacitor of the tuning circuit and the frequency of the RF generator to match a second impedance corresponding to a second stage of the waveform, wherein the frequency of the RF generator is tuned to a second frequency; recording setting values of the first frequency and the second frequency that match different impedances at different stages of the waveform; and switching between the first frequency and the second frequency to match the different impedances at the different stages of the waveform.

IPC Classes  ?

38.

TWO STEP IMPLANT TO IMPROVE LINE EDGE ROUGHNESS AND LINE WIDTH ROUGHNESS

      
Application Number 18077809
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Hautala, John
  • Dai, Huixiong

Abstract

Methods of processing patterned photoresist to reduce line edge roughness and line width roughness on a semiconductor workpiece are disclosed. The method is performed after the photoresist has been patterned and before the etching process is commenced. Two implants, using different species, are performed at high tilt angles. In certain embodiments, the tilt angle may be 45° or more. Further, the implants are performed at twist angles such that the trajectory of the ions is nearly parallel to the patterned photoresist lines. In this way, the ions from the two implants glance the top and sidewalls of the photoresist lines. Using this technique, the LER and LWR of the photoresist lines may be reduced with minimal impact on the CD.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

39.

CARRIER WITH ROTATION PREVENTION FEATURE

      
Application Number 18079755
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Cox, Damon K.
  • Gondihosalli, Manjunatha
  • Muthukamatchi, Karuppasamy

Abstract

A carrier includes a carrier body, fingers attached to the carrier body, and a rotation prevention component attached to the carrier body. The fingers are configured to support a process kit ring. The rotation prevention component is configured to be disposed proximate a flat inner surface of the process kit ring to prevent rotation of the process kit ring.

IPC Classes  ?

  • B25J 19/00 - Accessories fitted to manipulators, e.g. for monitoring, for viewing; Safety devices combined with or specially adapted for use in connection with manipulators
  • B25J 15/08 - Gripping heads having finger members

40.

THIN FILM TRANSISTORS FOR CIRCUITS FOR USE IN DISPLAY DEVICES

      
Application Number 18556460
Status Pending
Filing Date 2021-05-07
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Yim, Dong Kil
  • Choi, Soo Young
  • Kim, Jung Bae

Abstract

Disclosed herein is a device including a driving thin film transistor. The driving thin film transistor includes a metal oxide channel, a source electrode in contact with the driving metal oxide channel, and a top gate electrode disposed above the metal oxide channel and physically connected to the driving source electrode.

IPC Classes  ?

  • G09G 3/3266 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] - Details of drivers for scan electrodes
  • H01L 29/786 - Thin-film transistors

41.

LEARNING BASED TUNING IN A RADIO FREQUENCY PLASMA PROCESSING CHAMBER

      
Application Number US2023010752
Publication Number 2024/123375
Status In Force
Filing Date 2023-01-13
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Guo, Yue
  • Ramaswamy, Kartik
  • Yang, Yang

Abstract

Some embodiments are directed to a method of processing a substrate in a plasma processing system. The method generally includes tuning a first capacitor and a second capacitor of a tuning circuit to match a first impedance corresponding to a first stage of a waveform, while a frequency of a radio frequency (RF) generator is preset to a first frequency; tuning a third capacitor of the tuning circuit and the frequency of the RF generator to match a second impedance corresponding to a second stage of the waveform, wherein the frequency of the RF generator is tuned to a second frequency; recording setting values of the first frequency and the second frequency that match different impedances at different stages of the waveform; and switching between the first frequency and the second frequency to match the different impedances at the different stages of the waveform.

IPC Classes  ?

42.

CHAMBER IMPEDANCE MANAGEMENT IN A PROCESSING CHAMBER

      
Application Number US2023010922
Publication Number 2024/123377
Status In Force
Filing Date 2023-01-17
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Cui, Linying
  • Rogers, James
  • Hernandez, Keith
  • Chin, William
  • Dorf, Leonid

Abstract

Embodiments of the disclosure include an apparatus and a method for controlling plasma uniformity by controlling plasma density in the bulk plasma over the center region and circumferential edge region of the substrate. Plasma uniformity can be controlled by use of an RF tuning circuit coupled to one of a plurality of electrodes positioned relative to a substrate during plasma processing. By adjusting the electrical characteristics of at least one of the RF tuning circuits, the effect that the generated RF fundamental frequency and related RF harmonic frequencies have on the plasma processing results can be controlled. Beneficially, the use of one or more of the tuning circuits and methods of using the same may be used to provide individual tuning knobs for controlling reactive neutral species concentration, ion energy and angular distribution, ion directionality and directionality uniformity, and separately controlling ion flux and reactive neutral species uniformity across the surface of the substrate.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

43.

INTERLAYER FOR RESISTIVITY REDUCTION IN METAL DEPOSITION APPLICATIONS

      
Application Number US2023035687
Publication Number 2024/123427
Status In Force
Filing Date 2023-10-23
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Patel, Sahil Jaykumar
  • Zhao, Xianyuan
  • Lei, Wei
  • Zhang, Aixi
  • Xu, Yi
  • Lei, Yu

Abstract

Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes depositing an amorphous interlayer atop a first layer on a substrate, wherein the first layer is a metal-containing layer; and depositing a metal layer atop the amorphous interlayer.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material

44.

METHOD OF SELECTIVE METAL DEPOSITION USING SEPARATED REACTANT ACTIVATION AND PLASMA DISCHARGING ZONES

      
Application Number US2023035841
Publication Number 2024/123432
Status In Force
Filing Date 2023-10-25
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Jiang, Ying-Bing
  • Lee, Joung Joo
  • Tang, Xianmin
  • Lu, Jiang
  • Gelatos, Avgerinos V.
  • Wu, Dien-Yeh
  • Ye, Weifeng
  • Wan, Yiyang
  • How, Gary
  • Hernandez, Joseph

Abstract

Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.

IPC Classes  ?

  • C23C 16/42 - Silicides
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/452 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials by activating reactive gas streams before introduction into the reaction chamber, e.g. by ionization or by addition of reactive species
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges

45.

EUV PHOTORESIST AND UNDERLAYER ADHESION MODULATION

      
Application Number US2023037080
Publication Number 2024/123453
Status In Force
Filing Date 2023-11-09
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Huang, Zhiyu
  • Cao, Bocheng
  • Zhu, Siyu
  • Yu, Hang
  • Lin, Yung-Chen
  • Lang, Chi-I

Abstract

Embodiments disclosed herein include a method of developing a patterning stack. In an embodiment, the method comprises providing a patterning stack, where the patterning stack comprises an underlayer and a photoresist over the underlayer, and where the underlayer has a first adhesion strength with the photoresist. The method may further comprise exposing and developing the photoresist with electromagnetic radiation and a developer, where scum remains on a surface of the underlayer. In an embodiment, the method further comprises treating the underlayer so that the underlayer has a second adhesion strength with the scum, and removing the scum.

IPC Classes  ?

  • G03F 7/40 - Treatment after imagewise removal, e.g. baking
  • G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
  • G03F 7/039 - Macromolecular compounds which are photodegradable, e.g. positive electron resists

46.

TWO STEP IMPLANT TO IMPROVE LINE EDGE ROUGHNESS AND LINE WIDTH ROUGHNESS

      
Application Number US2023080024
Publication Number 2024/123519
Status In Force
Filing Date 2023-11-16
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Hautala, John
  • Dai, Huixiong

Abstract

Methods of processing patterned photoresist to reduce line edge roughness and line width roughness on a semiconductor workpiece are disclosed. The method is performed after the photoresist has been patterned and before the etching process is commenced. Two implants, using different species, are performed at high tilt angles. In certain embodiments, the tilt angle may be 45 or more. Further, the implants are performed at twist angles such that the trajectory of the ions is nearly parallel to the patterned photoresist lines. In this way, the ions from the two implants glance the top and sidewalls of the photoresist lines. Using this technique, the LER and LWR of the photoresist lines may be reduced with minimal impact on the CD.

IPC Classes  ?

  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/3105 - After-treatment
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

47.

SEMICONDUCTOR FILM THICKNESS PREDICTION USING MACHINE-LEARNING

      
Application Number US2023082213
Publication Number 2024/123635
Status In Force
Filing Date 2023-12-02
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Motamedi, Nojan
  • Benvegnu, Dominic J.
  • Shrestha, Kiran L.

Abstract

A machine-learning model may be used to estimate a film thickness from a spectral image captured from a semiconductor substrate during processing. Instead of using actual measurements from physical substrates to train the model, simulated images may be generated for a wide variety of predefined thickness profiles. Simulated training data may be rapidly generated by receiving a film thickness profile representing a film on a semiconductor substrate design. A light source may be simulated being reflected off of the film on the semiconductor substrate and being captured by a camera. The spectral data captured by the camera may be converted into one or more images for a wafer with the film thickness profile. The images may then be labeled with thicknesses from the film thickness profile for training a machine-learning model.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
  • G06T 7/00 - Image analysis
  • G06T 7/60 - Analysis of geometric attributes
  • G06N 20/00 - Machine learning
  • G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model

48.

THERMAL CHOKE PLATE

      
Application Number US2023082227
Publication Number 2024/123641
Status In Force
Filing Date 2023-12-04
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Nagappan, Vellaichamy
  • Kalsekar, Viren
  • Lee, Jeongmin
  • Prabhakar, Vinay K.
  • Chandran, Pratap
  • Srichurnam, Dharma Ratnam
  • Khan, Azhar
  • Singh, Sumit Subhash
  • Chandrasekar, Siva
  • Radhakrishnan, Satish

Abstract

Exemplary choke plates for use in a substrate processing system may include a plate defining a first aperture through the plate and a second aperture through the plate. The second aperture may be laterally offset from the first aperture. The plate may include a flange that defines a purging inlet. The plate may include a rim defining a plurality of purging outlets that are fluidly coupled with the purging inlet. Each of the plurality of purging outlets may be fluidly coupled with the first aperture.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

49.

Interlayer for Resistivity Reduction in Metal Deposition Applications

      
Application Number 18197846
Status Pending
Filing Date 2023-05-16
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Patel, Sahil Jaykumar
  • Zhao, Xianyuan
  • Lei, Wei
  • Zhang, Aixi
  • Xu, Yi
  • Lei, Yu

Abstract

Methods and apparatus for processing a substrate are provided. In some embodiments, a method includes depositing an amorphous interlayer atop a first layer on a substrate, wherein the first layer is a metal-containing layer, and depositing a metal layer atop the amorphous interlayer.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

50.

DESIGN, CONTROL, AND OPTIMIZATION OF PHOTOSENSITIVITY MODULATION ALONG PHOTORESIST FILM DEPTH

      
Application Number 18379102
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Hao, Ruiying
  • De Cecco, Paola
  • Sachan, Madhur
  • Lee, Kwangduk D.
  • Sanchez, Martha
  • Bozano, Luisa

Abstract

Embodiments disclosed herein include a method for forming a photoresist stack. In an embodiment, the method comprises forming a first photoresist layer over a substrate, where the first photoresist layer is formed with a first dry deposition process, and forming a second photoresist layer over the first photoresist layer, where the second photoresist layer is formed with a second dry deposition process that is different than the first deposition process.

IPC Classes  ?

  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

51.

MULTILAYER INNER SPACER FOR GATE-ALL-AROUND DEVICE

      
Application Number 18383182
Status Pending
Filing Date 2023-10-24
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Yeong, Sai Hooi
  • Jiang, Liu
  • Singha Roy, Susmit
  • Mallick, Abhijit Basu
  • Bazizi, El Mehdi
  • Colombeau, Benjamin

Abstract

Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

52.

POST-TREATMENT FOR REMOVING RESIDUES FROM DIELECTRIC SURFACE

      
Application Number 18534333
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Tavakoli, Mohammad Mahdi
  • Gelatos, Avgerinos V.
  • Cen, Jiajie
  • Kashefi, Kevin
  • Lee, Joung Joo
  • Liu, Zhihui
  • Zhou, Yang
  • Wu, Zhiyuan
  • Wu, Meng-Shan

Abstract

A semiconductor structure includes a first level comprising a metal layer within a first dielectric layer formed on a substrate, a second level formed on the first level, the second level comprising an interconnect within a second dielectric layer and a barrier layer formed around the interconnect, and a metal capping layer disposed at an interface between the metal layer and the interconnect, wherein the metal capping layer comprises tungsten (W) and has a thickness of between 20 Å and 40 Å.

IPC Classes  ?

  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

53.

MODULAR MAINFRAME LAYOUT FOR SUPPORTING MULTIPLE SEMICONDUCTOR PROCESS MODULES OR CHAMBERS

      
Application Number 18586209
Status Pending
Filing Date 2024-02-23
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Harris, Randy A.
  • Grove, Coby Scott
  • Wirth, Paul Zachary
  • Shantaram, Avinash
  • Yilmaz, Alpay
  • Nissan, Amir
  • Bhimjiyani, Jitendra Ratilal
  • Pingle, Niranjan
  • Dicaprio, Vincent

Abstract

Methods and apparatus for bonding chiplets to substrates are provided herein. In some embodiments, a multi-chamber processing tool for processing substrates includes: an equipment front end module (EFEM) having one or more loadports for receiving one or more types of substrates; and a plurality of automation modules coupled to each other and having a first automation module coupled to the EFEM, wherein each of the plurality of automation modules include a transfer chamber and one or more process chambers coupled to the transfer chamber, wherein the transfer chamber includes a buffer, and wherein the transfer chamber includes a transfer robot configured to transfer the one or more types of substrates, wherein at least one of the plurality of automation modules include a bonder chamber and at least one of the plurality of automation modules include a wet clean chamber.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

54.

CHAMBER IMPEDANCE MANAGEMENT IN A PROCESSING CHAMBER

      
Application Number 18063888
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Cui, Linying
  • Rogers, James
  • Hernandez, Keith
  • Chin, William
  • Dorf, Leonid

Abstract

Embodiments of the disclosure include an apparatus and a method for controlling plasma uniformity by controlling plasma density in the bulk plasma over the center region and circumferential edge region of the substrate. Plasma uniformity can be controlled by use of an RF tuning circuit coupled to one of a plurality of electrodes positioned relative to a substrate during plasma processing. By adjusting the electrical characteristics of at least one of the RF tuning circuits, the effect that the generated RF fundamental frequency and related RF harmonic frequencies have on the plasma processing results can be controlled. Beneficially, the use of one or more of the tuning circuits and methods of using the same may be used to provide individual tuning knobs for controlling reactive neutral species concentration, ion energy and angular distribution, ion directionality and directionality uniformity, and separately controlling ion flux and reactive neutral species uniformity across the surface of the substrate.

IPC Classes  ?

55.

ELECTROCHEMICAL REDUCTION OF SURFACE METAL OXIDES

      
Application Number 18077225
Status Pending
Filing Date 2022-12-07
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Shin, Yoon Ah
  • Mebarki, Bencherki
  • Lee, Joung Joo
  • Tang, Xianmin
  • Chua, Thai Cheng
  • Valencia, Christian W.

Abstract

Embodiments of the disclosure relate to methods for reducing metal oxide layers to pure metal using microwave radiation. Specific embodiments provide methods of reducing a native metal oxide on a metal interconnect within a substrate feature comprising dielectric sidewalls. In some embodiments, surrounding dielectric materials are undamaged by the disclosed processes.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

56.

TWO STEP IMPLANT TO CONTROL TIP-TO-TIP DISTANCE BETWEEN TRENCHES

      
Application Number 18077812
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Hautala, John
  • Dai, Huixiong

Abstract

Methods of processing patterned photoresist to control tip-to-tip distance on a semiconductor workpiece are disclosed. The method is performed after the photoresist has been patterned and before the etching process is commenced. Two implants, using different species, are performed at high tilt angles. In certain embodiments, the tilt angle may be 45° or more. Further, the implants are performed at twist angles such that the trajectory of the ions is nearly parallel to the patterned photoresist lines. In this way, the ions from the two implants glance the top and sidewalls of the photoresist lines. Using this technique, the tip-to-tip distance between patterned photoresist lines may be reduced with minimal impact on the CD.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

57.

Selective Implantation into STI of ETSOI Device

      
Application Number 18079817
Status Pending
Filing Date 2022-12-12
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Zhang, Qintao
  • Zou, Wei

Abstract

Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.

IPC Classes  ?

58.

ION EXTRACTION OPTICS HAVING NOVEL BLOCKER CONFIGURATION

      
Application Number 18080555
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner Applied Materials, Inc. (USA)
Inventor
  • Biloiu, Costel
  • Calkins, Adam
  • Rockwell, Tyler
  • Daniels, Kevin M.
  • Campbell, Christopher

Abstract

A processing system may include a plasma chamber and an extraction optics, disposed along a side of the plasma chamber. The extraction optics may include an extraction plate, having an outer side and an inner side, where the extraction plate defines at least one extraction aperture. The extraction optics may include a beam blocker, overlapping the at least one extraction aperture, and disposed towards the inner side of the extraction plate. The beam blocker may have a cross-section that defines a boomerang shape, and may comprise a first metallic material, where the extraction plate comprises a second metallic material. The processing system may further include a substrate platen, disposed outside of the plasma chamber, and movable along a scan direction with respect to the extraction aperture.

IPC Classes  ?

  • H01J 37/09 - Diaphragms; Shields associated with electron- or ion-optical arrangements; Compensation of disturbing fields

59.

AUTOMATIC SEGMENTATION OF AN IMAGE OF A SEMICONDUCTOR SPECIMEN AND USAGE IN METROLOGY

      
Application Number 18537693
Status Pending
Filing Date 2023-12-12
First Publication Date 2024-06-13
Owner Applied Materials Israel Ltd. (Israel)
Inventor
  • Akerman, Lior
  • Peled, Tomer Haim

Abstract

There is provided a method and a system in which a processing circuitry is configured to obtain an inspection image representative of 2D information of an inspection area of a semiconductor specimen, and feed the inspection image to a trained machine learning model operative to segment the inspection image into at least a first segment S′1 and a second segment S′2, wherein the first segment S′1 corresponds to a first region of the inspection area which has a height profile pattern corresponding to a first height profile pattern, and the second segment S′2 corresponds to a second region of the area which has a height profile pattern corresponding to a second height profile pattern, wherein the first height profile pattern is different from the second height profile pattern.

IPC Classes  ?

60.

Integrated process sequence for hybrid bonding applications

      
Application Number 18078416
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Pingle, Niranjan
  • Bhimjiyani, Jitendra Ratilal
  • Jaiswal, Shreshtha Kumar

Abstract

A method for sequencing a hybrid bonding process by double linking a source of dies and a target. The method may include selecting a source of dies for bonding, selecting a target on which the dies will be bonded, linking the source to the target, linking the target to the source, forming an integrated bonding product sequence that includes a first linked bonding sequence for the source and a second linked bonding sequence for the target, determining bonding process chamber allocations and process timing for the source and the target based on the integrated bonding product sequence, and bonding a die from the source to the target using the integrated bonding product sequence.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

61.

Method of Selective Metal Deposition Using Separated Reactant Activation and Plasma Discharging Zone

      
Application Number 18078841
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Jiang, Ying-Bing
  • Lee, Joung Joo
  • Tang, Xianmin
  • Lu, Jiang
  • Gelatos, Avgerinos V.
  • Wu, Dien-Yeh
  • Ye, Weifeng
  • Wan, Yiyang
  • How, Gary
  • Hernandez, Joseph

Abstract

Methods of depositing a metal silicide on a substrate are provided herein. In some embodiments, a method of depositing a metal silicide on a substrate having a silicon containing surface includes: creating a plasma comprising a first gas in a plasma region in a chemical vapor deposition (CVD) chamber, wherein the plasma region is disposed between a lid heater and a showerhead; flowing the first gas through a plurality of first openings of the showerhead to an activation region in the CVD chamber disposed between the showerhead and the substrate; flowing a second gas comprising a metal precursor in a non-plasma state through a plurality of second openings of the showerhead to the activation region, wherein the plurality of second openings are fluidly independent from the plurality of first openings within the showerhead; mixing the first gas with the second gas to activate the second gas in the activation region; and exposing the silicon containing surface of the substrate to the activated second gas.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/42 - Silicides
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • H01J 37/32 - Gas-filled discharge tubes

62.

MULTILAYER INNER SPACER FOR GATE-ALL-AROUND DEVICE

      
Application Number US2023035769
Publication Number 2024/123430
Status In Force
Filing Date 2023-10-24
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yeong, Sai Hooi
  • Jiang, Liu
  • Singha Roy, Susmit
  • Mallick, Abhijit Basu
  • Bazizi, El Mehdi
  • Colombeau, Benjamin

Abstract

in situin situ in an integrated deposition and etch processing system.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

63.

TWO STEP IMPLANT TO CONTROL TIP-TO-TIP DISTANCE BETWEEN TRENCHES

      
Application Number US2023080042
Publication Number 2024/123520
Status In Force
Filing Date 2023-11-16
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Hautala, John
  • Dai, Huixiong

Abstract

Methods of processing patterned photoresist to control tip-to-tip distance on a semiconductor workpiece are disclosed. The method is performed after the photoresist has been patterned and before the etching process is commenced. Two implants, using different species, are performed at high tilt angles. In certain embodiments, the tilt angle may be 45° or more. Further, the implants are performed at twist angles such that the trajectory of the ions is nearly parallel to the patterned photoresist lines. In this way, the ions from the two implants glance the top and sidewalls of the photoresist lines. Using this technique, the tip-to-tip distance between patterned photoresist lines may be reduced with minimal impact on the CD.

IPC Classes  ?

  • H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
  • H01L 21/3105 - After-treatment
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

64.

ELECTROCHEMICAL REDUCTION OF SURFACE METAL OXIDES

      
Application Number US2023081095
Publication Number 2024/123553
Status In Force
Filing Date 2023-11-27
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Shin, Yoon Ah
  • Mebarki, Bencherki
  • Lee, Joung Joo
  • Tang, Xianmin
  • Chua, Thai Cheng
  • Valencia, Christian W.

Abstract

Embodiments of the disclosure relate to methods for reducing metal oxide layers to pure metal using microwave radiation. Specific embodiments provide methods of reducing a native metal oxide on a metal interconnect within a substrate feature comprising dielectric sidewalls. In some embodiments, surrounding dielectric materials are undamaged by the disclosed processes.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

65.

INTEGRATED PROCESS SEQUENCE FOR HYBRID BONDING APPLICATIONS

      
Application Number US2023082065
Publication Number 2024/123616
Status In Force
Filing Date 2023-12-01
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Pingle, Niranjan
  • Bhimjiyani, Jitendra Ratilal
  • Jaiswal, Shreshtha Kumar

Abstract

A method for sequencing a hybrid bonding process by double linking a source of dies and a target. The method may include selecting a source of dies for bonding, selecting a target on which the dies will be bonded, linking the source to the target, linking the target to the source, forming an integrated bonding product sequence that includes a first linked bonding sequence for the source and a second linked bonding sequence for the target, determining bonding process chamber allocations and process timing for the source and the target based on the integrated bonding product sequence, and bonding a die from the source to the target using the integrated bonding product sequence.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

66.

METHOD OF PROCESSING A SUBSTRATE AND PROCESSING APPARATUS

      
Application Number EP2022084770
Publication Number 2024/120628
Status In Force
Filing Date 2022-12-07
Publication Date 2024-06-13
Owner APPLIED MATERIALS, INC. (USA)
Inventor Lee, Ming-Chun

Abstract

A method of processing a substrate. The substrate is a glass substrate for display manufacturing. The method includes chucking the substrate to a monopolar electrostatic chuck by providing a voltage to an electrode of the electrostatic chuck, and providing a chucking plasma at a first power. The method further includes processing the substrate in a DC sputtering deposition process, and de-chucking the substrate. The de-chucking includes generating a de-chucking plasma.

IPC Classes  ?

  • C23C 14/50 - Substrate holders
  • C23C 14/34 - Sputtering
  • C23C 14/18 - Metallic material, boron or silicon on other inorganic substrates
  • H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
  • C03C 17/09 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with metals by deposition from the vapour phase
  • C03C 17/245 - Oxides by deposition from the vapour phase

67.

MAGNUS

      
Application Number 1792424
Status Registered
Filing Date 2024-03-22
Registration Date 2024-03-22
Owner Applied Materials, Inc. (USA)
NICE Classes  ? 07 - Machines and machine tools

Goods & Services

Semiconductor manufacturing equipment used to remove material from substrates.

68.

DETECTOR FOR PROCESS KIT RING WEAR

      
Application Number 18401881
Status Pending
Filing Date 2024-01-02
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Vishwanath, Yogananda Sarode
  • Criminale, Phillip A.

Abstract

A diagnostic disc includes a disc body having a sidewall around a circumference of the disc body and at least one protrusion extending outwardly from a top of the sidewall. A non-contact sensor is attached to an underside of each of the at least one protrusion. A printed circuit board (PCB) is positioned within an interior formed by the disc body. Circuitry is disposed on the PCB and coupled to each non-contact sensor, the circuitry including at least a wireless communication circuit, a memory, and a battery. A cover is positioned over the circuitry inside of the sidewall, where the cover seals the circuitry within the interior formed by the disc body from an environment outside of the disc body.

IPC Classes  ?

  • G01B 11/30 - Measuring arrangements characterised by the use of optical techniques for measuring roughness or irregularity of surfaces
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

69.

METHODS AND APPARATUS FOR REDUCING SPUTTERING OF A GROUNDED SHIELD IN A PROCESS CHAMBER

      
Application Number 18418930
Status Pending
Filing Date 2024-01-22
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Ritchie, Alan
  • Forster, John C.
  • Rasheed, Muhammad

Abstract

Methods and apparatus for physical vapor deposition are provided herein. In some embodiments, a process kit shield for use in a physical vapor deposition chamber may include an electrically conductive body having one or more sidewalls defining a central opening, wherein the body has a ratio of a surface area of inner facing surfaces of the one or more sidewalls to a height of the one or more sidewalls of about 2 to about 3.

IPC Classes  ?

70.

MONOLITHIC MODULAR MICROWAVE SOURCE WITH INTEGRATED PROCESS GAS DISTRIBUTION

      
Application Number 18419389
Status Pending
Filing Date 2024-01-22
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Carducci, James
  • Fovell, Richard C.
  • Elizaga, Larry D.
  • Rodrigues, Silverst
  • Knyazik, Vladimir
  • Kraus, Philip Allan
  • Chua, Thai Cheng

Abstract

Embodiments disclosed herein include a housing for a source array. In an embodiment, the housing comprises a conductive body, where the conductive body comprises a first surface and a second surface opposite from the first surface. In an embodiment a plurality of openings are formed through the conductive body and a channel is disposed into the second surface of the conductive body. In an embodiment, a cover is over the channel, and the cover comprises first holes that pass through a thickness of the cover. In an embodiment, the housing further comprises a second hole through a thickness of the conductive body. In an embodiment, the second hole intersects with the channel.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/511 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using microwave discharges

71.

WORDLINE CONTACT FORMATION FOR NAND DEVICE

      
Application Number 18523401
Status Pending
Filing Date 2023-11-29
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Lee, Hsiangyu
  • Subrahmanyan, Pradeep
  • Sun, Changwoo

Abstract

Disclosed are approaches for direct wordline contact formation for 3-D NAND devices. One method may include providing a film stack including a plurality of alternating first layers and second layers, and forming a plurality of contact openings in the film stack, wherein each contact opening is formed to a different etch depth relative to an upper surface of the film stack. The method may further include depositing a liner over the film stack including within each of the contact openings, removing the first layers to form a plurality of wordline openings in the film stack, and forming a plurality of wordlines by depositing a first conductive material within the wordline openings. The method may further include removing the liner from a bottom of each contact opening, and depositing a second conductive material within the contact openings to form a plurality of wordline contacts.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

72.

WORDLINE CONTACT FORMATION FOR NAND DEVICE

      
Application Number 18525198
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Lee, Hsiangyu
  • Subrahmanyan, Pradeep
  • Sun, Changwoo

Abstract

Disclosed are approaches for direct wordline contact formation for 3D NAND devices. One method may include providing a first film stack comprising a first plurality of alternating first layers and second layers, and forming a first plurality of contact openings in the first film stack, wherein each contact opening is formed to a different etch depth. The method may further include forming a sacrificial gapfill within the first plurality of contact openings, and forming a second film stack atop the first film stack, wherein the second film stack comprises a second plurality of alternating first layers and second layers. The method may further include forming a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill, and removing the sacrificial gapfill from the first plurality of contact openings.

IPC Classes  ?

  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

73.

MULTI-PULSE DEPOSITION PROCESSES

      
Application Number 18074197
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Huang, Tianyi
  • Gandikota, Srinivas
  • Yang, Yixiong
  • Mao, Elizabeth
  • Lin, Chi-Chou

Abstract

Embodiments of the present disclosure advantageously provide improved control over precursor/reactant pulse/purge time, greater growth per cycle, and higher throughput during formation of a metal-containing film on a substrate surface (including substrate surfaces having at least one feature) compared to traditional atomic layer deposition (ALD) processes. In some embodiments, forming the metal-containing film comprises exposing a substrate to a constant flow of an inert carrier gas and a co-flow of a pulse of a metal-containing precursor and a pulse of a reactant. The pulse of the metal-containing precursor and the pulse of the reactant may be interrupted by a mini purge. The metal-containing precursor and/or the reactant may be charged during the mini purge to avoid precursor/reactant depletion.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/34 - Nitrides
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

74.

Method to Deposit Metal Cap for Interconnect

      
Application Number 18074335
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Qu, Ge
  • Zhu, Qihao
  • Ju, Zheng
  • Zhou, Yang
  • Cen, Jiajie
  • Liu, Feng Q.
  • Wu, Zhiyuan
  • Chen, Feng
  • Kashefi, Kevin
  • Tang, Xianmin
  • Anthis, Jeffrey W.
  • Saly, Mark Joseph

Abstract

Methods to deposit a metal cap for an interconnect are disclosed. In embodiments, a method comprises contacting the substrate with an alkyl halide and a ruthenium metal precursor to form a metal cap for an interconnect.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers

75.

Heated Pedestal With Impedance Matching Radio Frequency (RF) Rod

      
Application Number 18074385
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yang, Yao-Hung
  • Chang, Chih-Yang
  • Chen, Yikai
  • Wang, Rongping

Abstract

Embodiments of substrate supports for process chambers are provided herein. In some embodiments, a substrate support for a process chamber includes: a pedestal having a support surface for supporting a substrate, one or more heating elements disposed therein, and a radio frequency (RF) electrode disposed therein; a hollow shaft coupled to a lower surface of the pedestal; and an RF rod extending through the hollow shaft and coupled to the RF electrode, wherein an impedance of the RF rod is less than about 0.2 ohms.

IPC Classes  ?

76.

SEMICONDUCTOR FILM THICKNESS PREDICTION USING MACHINE-LEARNING

      
Application Number 18075216
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Motamedi, Nojan
  • Benvegnu, Dominic J.
  • Shrestha, Kiran L.

Abstract

A machine-learning model may be used to estimate a film thickness from a spectral image captured from a semiconductor substrate during processing. Instead of using actual measurements from physical substrates to train the model, simulated images may be generated for a wide variety of predefined thickness profiles. Simulated training data may be rapidly generated by receiving a film thickness profile representing a film on a semiconductor substrate design. A light source may be simulated being reflected off of the film on the semiconductor substrate and being captured by a camera. The spectral data captured by the camera may be converted into one or more images for a wafer with the film thickness profile. The images may then be labeled with thicknesses from the film thickness profile for training a machine-learning model.

IPC Classes  ?

77.

THERMAL CHOKE PLATE

      
Application Number 18076234
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Nagappan, Vellaichamy
  • Kalsekar, Viren
  • Lee, Jeongmin
  • Prabhakar, Vinay K.
  • Chandran, Pratap
  • Srichurnam, Dharma Ratnam
  • Khan, Azhar
  • Singh, Sumit Subhash
  • Chandrasekar, Siva
  • Radhakrishnan, Satish

Abstract

Exemplary choke plates for use in a substrate processing system may include a plate defining a first aperture through the plate and a second aperture through the plate. The second aperture may be laterally offset from the first aperture. The plate may include a flange that defines a purging inlet. The plate may include a rim defining a plurality of purging outlets that are fluidly coupled with the purging inlet. Each of the plurality of purging outlets may be fluidly coupled with the first aperture.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

78.

GAS RECYCLING SYSTEMS, SUBSTRATE PROCESSING SYSTEMS, AND RELATED APPARATUS AND METHODS FOR SEMICONDUCTOR MANUFACTURING

      
Application Number US2023027684
Publication Number 2024/118117
Status In Force
Filing Date 2023-07-13
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Sowwan, Mukhles
  • Lau, Shu-Kwan

Abstract

The present disclosure generally relates to gas recycling systems, substrate processing systems, and related apparatus and methods for semiconductor manufacturing. In one or more implementations, unreacted gases from chambers can be used, recycled, and used one or more additional times. In one implementation, a gas recycling system includes a pump configured to fluidly connect to one or more outlet passages of a processing chamber to exhaust a gas from the processing chamber. The system includes one or more filtration devices in fluid communication with the pump such that the gas flows from the pump to the one or more filtration devices. The one or more filtration devices are configured to remove one or more impurities from the gas. The system includes a gas supply system in fluid communication with the one or more filtration devices such that the filtered gas flows to the gas supply system.

IPC Classes  ?

  • C30B 25/14 - Feed and outlet means for the gases; Modifying the flow of the reactive gases
  • C30B 25/16 - Controlling or regulating
  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber

79.

MODELING FOR INDEXING AND SEMICONDUCTOR DEFECT IMAGE RETRIEVAL

      
Application Number US2023035335
Publication Number 2024/118162
Status In Force
Filing Date 2023-10-17
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Guo, Yuanhong
  • Dangayach, Sachin
  • Komatireddi, Rahul Reddy
  • Wu, Tianyuan

Abstract

The subject matter of this specification can be implemented in, among other things, methods, systems, computer-readable storage medium. A method can include a processing device storing a plurality of feature vectors representative of previously processed image frames that correspond to various substrate processing defects. The method further includes receiving first image data comprising one or more image frames indicative of a first substrate processing defect. The method further includes determining a first feature vector corresponding to the first image data. The method further includes determining a selection of the plurality of feature vectors based on a proximity between the first feature vector and each of the selection of the plurality of feature vectors. The method further includes determining second image data comprising one or more image frames corresponding to the selection of the plurality of embedding vectors and performing an action based on determining the second image data.

IPC Classes  ?

80.

LATTICE BASED VOLTAGE STANDOFF

      
Application Number US2023035396
Publication Number 2024/118163
Status In Force
Filing Date 2023-10-18
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Mclaughlin, Adam M.
  • Chaney, Craig R.

Abstract

An insulator that has a lattice is disclosed. The insulator may have a shaft with two ends. The lattice may be disposed on the outer surface of the shaft. In some embodiments, one or more sheaths are used to cover portions of the shaft. A lattice may also be disposed on the inner wall and/or outer walls of the sheaths. The lattice serves to increase the tracking length between the two ends of the shaft. This results in longer times before failure. This insulator may be used in an ion implantation system to physically and electrically separate two components.

IPC Classes  ?

  • H01J 37/08 - Ion sources; Ion guns
  • H01J 27/02 - Ion sources; Ion guns
  • H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation

81.

METHOD FOR GAPFILL

      
Application Number US2023035658
Publication Number 2024/118172
Status In Force
Filing Date 2023-10-22
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Xu, Yi
  • Lei, Yu
  • Zhang, Aixi
  • Wang, Rongjun

Abstract

A method of gap fill may include depositing a sacrificial Si layer in an opening of a feature and on a field of a substrate. In addition, the method may include depositing a metal layer in the opening and on the field, where at least a portion of the sacrificial Si layer is replaced with the metal layer. The method may also include depositing a metal gapfill material in the opening and on the field directly over the metal layer, where the metal gapfill material completely fills the opening.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation

82.

SOLID-STATE SWITCH BASED HIGH-SPEED PULSER WITH PLASMA IEDF MODIFICATION CAPABILITY THROUGH MULTILEVEL OUTPUT FUNCTIONALITY

      
Application Number US2023078403
Publication Number 2024/118289
Status In Force
Filing Date 2023-11-01
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Ramaswamy, Kartik
  • Guo, Yue
  • Yang, Yang
  • Silveira, Fernando
  • Azad, A.N.M. Wasekul

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having three MOSFETs and three series-connected capacitors. The capacitors are connected across a DC power supply and, depending on the value of the capacitors, voltage across each of them may be varied. Each of the top two capacitors is followed by a diode. The bottom capacitor is connected to the ground. The drain terminal of each MOSFET is connected to higher potential end of the series connected capacitors. Each MOSFET is followed by a diode and the cathode ends of the diodes are connected together. An electrode is connected between the common cathode and ground.

IPC Classes  ?

83.

LOW RESISTIVITY GAPFILL

      
Application Number US2023080470
Publication Number 2024/118370
Status In Force
Filing Date 2023-11-20
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yang, Tsung-Han
  • Liu, Zhen
  • Gao, Yongqian
  • Hou, Wenting
  • Wang, Rongjun

Abstract

Embodiments of the disclosure relate to methods for metal gapfill with lower resistivity. Specific embodiments provide methods of forming a tungsten gapfill without a high resistance nucleation layer. Some embodiments of the disclosure utilize a nucleation underlayer to promote growth of the metal gapfill.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks
  • C23C 16/14 - Deposition of only one other metal element

84.

DETERMINING EQUIPMENT CONSTANT UPDATES BY MACHINE LEARNING

      
Application Number US2023080592
Publication Number 2024/118382
Status In Force
Filing Date 2023-11-20
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Bhatia, Sidharth
  • Lindley, Roger
  • Ummethala, Upendra
  • Li, Thomas
  • Howells, Michael
  • Babayan, Steven
  • Dao, Mimi-Diemmy

Abstract

A method includes providing, as input to a first trained machine learning model, trace data associated with one or more substrate processing procedures. The input further includes equipment constants associated with the one or more substrate processing procedures. The input further includes trace data of a first processing chamber. The input further includes equipment constants of the first processing chamber. The method further includes obtaining, as output from the first trained machine learning model, a recommended update to a first equipment constant of the first processing chamber. The method further includes updated the first equipment constant of the first processing chamber responsive to obtaining the output from the first trained machine learning model.

IPC Classes  ?

  • G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • G06N 20/00 - Machine learning

85.

CONTROL OF AG INK FLOW VIA INKJET REMOVABLE MASK FOR AR DEVICES

      
Application Number US2023081164
Publication Number 2024/118506
Status In Force
Filing Date 2023-11-27
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Luo, Yingdong
  • Galiazzo, Marco
  • Yao, Zhengping
  • Zhang, Daihua
  • Deng, Xiaopei
  • Hourani, Rami
  • Godet, Ludovic

Abstract

A method and apparatus for forming a device, including depositing a mask layer on a first portion of a surface, the mask layer forming a feature over the surface, depositing the mirror layer on the second portion of the surface within the feature, and removing the mask layer from the surface.

IPC Classes  ?

  • G02B 5/08 - Mirrors
  • G02B 1/12 - Optical coatings produced by application to, or surface treatment of, optical elements by surface treatment, e.g. by irradiation
  • G02B 5/18 - Diffracting gratings
  • G02B 27/01 - Head-up displays

86.

CALCULATE WAFERS THICKNESS OUT OF WAFER MAPPING PROCESS

      
Application Number US2023081676
Publication Number 2024/118833
Status In Force
Filing Date 2023-11-29
Publication Date 2024-06-06
Owner
  • APPLIED MATERIALS ISRAEL LTD. (Israel)
  • APPLIED MATERIALS, INC. (USA)
Inventor Dudovitch, Ofer

Abstract

A method of operating a substrate processing system that includes a substrate processing chamber, a substrate storage container and robot configured to select a substrate from the substrate storage container and transfer a selected substrate into the substrate processing chamber, the method comprising: detecting a lower edge and upper edge of the substrate; calculating a thickness of the substrate based on the detected lower and upper edges of the substrate; comparing the calculated thickness of the substrate to an expected thickness of the substrate; and (i) if the calculated thickness matches the expected thickness, controlling the robot to transfer the substrate into the substrate processing chamber, (ii) if the calculated thickness does not match the expected thickness, generating an alert indicating a thickness mismatch.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • G01B 21/08 - Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness for measuring thickness

87.

WORDLINE CONTACT FORMATION FOR NAND DEVICE

      
Application Number US2023081902
Publication Number 2024/118963
Status In Force
Filing Date 2023-11-30
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Lee, Hsiangyu
  • Subrahmanyan, Pradeep
  • Sun, Changwoo

Abstract

Disclosed are approaches for direct wordline contact formation for 3D NAND devices. One method may include providing a first film stack comprising a first plurality of alternating first layers and second layers, and forming a first plurality of contact openings in the first film stack, wherein each contact opening is formed to a different etch depth. The method may further include forming a sacrificial gapfill within the first plurality of contact openings, and forming a second film stack atop the first film stack, wherein the second film stack comprises a second plurality of alternating first layers and second layers. The method may further include forming a second plurality of contact openings in the second film stack, wherein a first set of contact openings of the second plurality of contact openings extends to the sacrificial gapfill, and removing the sacrificial gapfill from the first plurality of contact openings.

IPC Classes  ?

  • H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
  • H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

88.

HEATED PEDESTAL WITH IMPEDANCE MATCHING RADIO FREQUENCY (RF) ROD

      
Application Number US2023082199
Publication Number 2024/119161
Status In Force
Filing Date 2023-12-01
Publication Date 2024-06-06
Owner APPLIED MATERIALS, INC. (USA)
Inventor
  • Yang, Yao-Hung
  • Chang, Chih-Yang
  • Chen, Yikai
  • Wang, Rongping

Abstract

Embodiments of substrate supports for process chambers are provided herein. In some embodiments, a substrate support for a process chamber includes: a pedestal having a support surface for supporting a substrate, one or more heating elements disposed therein, and a radio frequency (RF) electrode disposed therein; a hollow shaft coupled to a lower surface of the pedestal; and an RF rod extending through the hollow shaft and coupled to the RF electrode, wherein an impedance of the RF rod is less than about 0.2 ohms.

IPC Classes  ?

89.

USING LASER BEAM FOR SEM BASE TOOLS, WORKING DISTANCE MEASUREMENT AND CONTROL WORKING DISTANCE SEM TO TARGET

      
Application Number US2023080810
Publication Number 2024/118409
Status In Force
Filing Date 2023-11-21
Publication Date 2024-06-06
Owner APPLIED MATERIALS ISRAEL LTD. (Israel)
Inventor
  • Dudovitch, Ofer
  • Ben Noon, Ido
  • Zertser, Efi

Abstract

A system for processing a sample comprising: a vacuum chamber having a window formed along one of its walls; a sample support configured to hold a sample within the vacuum chamber during a sample processing operation and move the substrate within the vacuum chamber along the X, Y and Z axes; a charged particle beam column configured to direct a charged particle beam into the vacuum chamber and focus the beam to collide with a region of interest on the sample; an optical distance measurement device configured to generate and direct electromagnetic radiation into the vacuum chamber through the window, detect photons from the electromagnetic radiation reflected off the sample, and determine a working distance between the sample and charged particle column based on the generated electromagnetic radiation and the detected photons; and one or more mirrors disposed within the vacuum chamber and positioned to direct the electromagnetic radiation generated by the optical distance measurement system to a measured location on the sample that is in close proximity to the region of interest, the one or more mirrors comprising at least one mirror positioned directly under a portion of the charged particle column.

IPC Classes  ?

  • H01J 37/147 - Arrangements for directing or deflecting the discharge along a desired path
  • H01J 37/12 - Lenses electrostatic
  • H01J 37/244 - Detectors; Associated components or circuits therefor
  • H01J 37/28 - Electron or ion microscopes; Electron- or ion-diffraction tubes with scanning beams

90.

EUV PHOTORESIST AND UNDERLAYER ADHESION MODULATION

      
Application Number 18379106
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Huang, Zhiyu
  • Cao, Bocheng
  • Zhu, Siyu
  • Yu, Hang
  • Lin, Yung-Chen
  • Lang, Chi-I

Abstract

Embodiments disclosed herein include a method of developing a patterning stack. In an embodiment, the method comprises providing a patterning stack, where the patterning stack comprises an underlayer and a photoresist over the underlayer, and where the underlayer has a first adhesion strength with the photoresist. The method may further comprise exposing and developing the photoresist with electromagnetic radiation and a developer, where scum remains on a surface of the underlayer. In an embodiment, the method further comprises treating the underlayer so that the underlayer has a second adhesion strength with the scum, and removing the scum.

IPC Classes  ?

  • G03F 7/11 - Photosensitive materials - characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers

91.

HIGH-DENSITY MICRO-LED ARRAYS WITH REFLECTIVE SIDEWALLS

      
Application Number 18413013
Status Pending
Filing Date 2024-01-15
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Ding, Kai
  • Xu, Lisong
  • Zhu, Mingwei
  • Li, Zhiyong
  • Ng, Hou T.
  • Ganapathiappan, Sivapackia
  • Patibandla, Nag

Abstract

Micro-LED structures include an LED epilayer that may be formed before the micro-LED structure is coupled to a backplane substrate. In order to prevent light leakage and maximize light output, the sidewalls and other surfaces of the LED epilayer may be coated with a reflective coating. For example, the reflective coating may include a metal layer that is electrically insulated between dielectric layers from the micro-LED electrodes. The reflective coating may also be formed using multiple layers in a distributed Bragg reflector configuration. This reflective coating may be formed during the LED fabrication process before the micro-LED structure is coupled to the backplane. The pixel isolation structures on the backplane may also include a reflective coating that is applied above the LED epilayers.

IPC Classes  ?

  • H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

92.

FLEXIBLE MULTI-LAYERED COVER LENS STACKS FOR FOLDABLE DISPLAYS

      
Application Number 18437844
Status Pending
Filing Date 2024-02-09
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Thothadri, Manivannan
  • You, Harvey
  • Nominanda, Helinda
  • Morrison, Neil
  • Forster, Daniel Paul
  • Chadha, Arvinder

Abstract

Embodiments described and discussed herein generally relate to flexible or foldable display devices, and more specifically to flexible cover lens assemblies. In one or more embodiments, a flexible cover lens assembly contains a glass layer, an adhesion promotion layer on the glass layer, an anti-reflectance layer disposed on the adhesion promotion layer, a dry hardcoat layer having a nano-indentation hardness in a range from about 1 GPa to about 5 GPa and disposed on the anti-reflectance layer, and an anti-fingerprint coating layer disposed on the dry hardcoat layer.

IPC Classes  ?

93.

METHOD OF BUILDING A 3D FUNCTIONAL OPTICAL MATERIAL STACKING STRUCTURE

      
Application Number 18439434
Status Pending
Filing Date 2024-02-12
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Young, Michael Yu-Tak
  • Godet, Ludovic
  • Visser, Robert Jan
  • Argaman, Naamah
  • Bencher, Christopher Dennis
  • Mcmillan, Wayne

Abstract

Embodiments herein describe a sub-micron 3D diffractive optics element and a method for forming the sub-micron 3D diffractive optics element. In a first embodiment, a method is provided for forming a sub-micron 3D diffractive optics element on a film stack disposed on a substrate without planarization. The method includes forming a hardmask on a top surface of a film stack. Forming a mask material on a portion of the top surface and a portion of the hardmask. Etching the top surface. Trimming the mask. Etching the top surface again. Trimming the mask a second time. Etching the top surface yet again and then stripping the mask material.

IPC Classes  ?

  • G02B 5/18 - Diffracting gratings
  • G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
  • G02B 30/26 - Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer’s left and right eyes of the autostereoscopic type
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor

94.

CONTROLLING LIGHT SOURCE WAVELENGTHS FOR SELECTABLE PHASE SHIFTS BETWEEN PIXELS IN DIGITAL LITHOGRAPHY SYSTEMS

      
Application Number 18440727
Status Pending
Filing Date 2024-02-13
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Laidig, Thomas L.
  • Bencher, Christopher
  • Jeong, Hwan J.
  • Hollerbach, Uwe

Abstract

A digital lithography system may adjust a wavelength of the light source to compensate for tilt errors in micromirrors while maintaining a perpendicular direction for the reflected light. Adjacent pixels may have a phase shift that is determined by an optical path difference between their respective light beams. This phase shift may be preselected to be any value by generating a corresponding wavelength at the light source based on the optical path difference. To generate a specific wavelength corresponding to the desired phase shift, the light source may produce multiple light components that have wavelengths that bracket the wavelength of the selected phase shift. The intensities of these components may then be controlled individually to produce an effect that approximates the selected phase shift on the substrate.

IPC Classes  ?

  • G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
  • G02B 27/30 - Collimators
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor

95.

METHODS AND APPARATUS FOR PRECLEANING AND TREATING WAFER SURFACES

      
Application Number 18442234
Status Pending
Filing Date 2024-02-15
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Xie, Xiangjin
  • Leal Cervantes, Carmen
  • Chen, Feng
  • Chen, Lu
  • Xu, Wenjing
  • Kamath, Aravind
  • Tsai, Cheng-Hsiung Matthew
  • Ha, Tae Hong
  • Jansen, Alexander
  • Tang, Xianmin

Abstract

Methods and apparatus for processing a substrate include cleaning and self-assembly monolayer (SAM) formation for subsequent reverse selective atomic layer deposition. An apparatus may include a process chamber with a processing volume and a substrate support including a pedestal, a remote plasma source fluidly coupled to the process chamber and configured to produce radicals or ionized gas mixture with radicals that flow into the processing volume to remove residue or oxides from a surface of the substrate, a first gas delivery system with a first ampoule configured to provide at least one first chemical into the processing volume to produce a SAM on the surface of the substrate, a heating system located in the pedestal and configured to heat a substrate by flowing gas on a backside of the substrate, and a vacuum system fluidly coupled to the process chamber and configured to control heating of the substrate.

IPC Classes  ?

  • C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
  • H01J 37/32 - Gas-filled discharge tubes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

96.

3D MEMORY INCLUDING HOLLOW EPITAXIAL CHANNELS

      
Application Number 18525633
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Lee, Hsiangyu
  • Subrahmanyan, Pradeep
  • Sun, Changwoo

Abstract

Disclosed are approaches for fabricating 3D NAND flash memory structures including hollow epitaxial channels. One approach for fabricating a 3D NAND memory structure may include forming a plurality of alternating material layers arranged in a vertical stack on a substrate, etching a channel hole that extends through the plurality of alternating material layers to the substrate, and forming a tunneling layer around the channel hole contacting the plurality of alternating material layers. The method may further include forming a channel liner along the tunneling layer, forming a core gap material within the channel liner, removing the channel liner from the channel hole, and epitaxially growing a hollow epitaxial silicon core from the substrate through the channel hole, between the tunneling layer and the core gap material.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

97.

AREA SELECTIVE DEPOSITION THROUGH SURFACE SILYLATION

      
Application Number 17991931
Status Pending
Filing Date 2022-11-22
First Publication Date 2024-06-06
Owner
  • Applied Materials, Inc. (USA)
  • National University of Singapore (Singapore)
Inventor
  • Wang, Xinke
  • Shen, Zeqing
  • Singha Roy, Susmit
  • Mallick, Abhijit Basu
  • Bhuyan, Bhaskar Jyoti
  • Tang, Jiecong
  • Sudijono, John
  • Liu, Long

Abstract

Methods of selectively depositing a selectively deposited layer are described. Exemplary processing methods may include treating a substrate comprising a non-hydroxyl-containing surface and a second surface with one or more of ozone, hydrogen peroxide, or a hydrogen plasma to passivate the second surface. In one or more embodiments, a selectively deposited layer is then selectively deposited on the non-hydroxyl-containing surface and not on the second surface by flowing a first precursor over the substrate to form a first portion of an initial carbon-containing film on the non-hydroxyl-containing surface and not on the second surface. The methods may include removing a first precursor effluent from the substrate. A second precursor may then be flowed over the substrate to react with the first portion of the initial selectively deposited layer. The methods may include removing a second precursor effluent from the substrate.

IPC Classes  ?

  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/02 - Pretreatment of the material to be coated
  • C23C 16/04 - Coating on selected surface areas, e.g. using masks

98.

DRAM TRANSISTOR INCLUDING HORIZONAL BODY CONTACT

      
Application Number 18061733
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Gu, Sipeng
  • Zhang, Qintao

Abstract

Disclosed herein are approaches for forming a dynamic random-access memory device (DRAM). One DRAM device may include plurality of pillars extending from a base layer, and a spacer layer formed along just a lower portion of each of the plurality of pillars. The DRAM further includes a body contact and a cap between the plurality of pillars, wherein the body contact is formed over the spacer layer, and a gate formed around the plurality of pillars. The DRAM further includes a bottom source/drain formed in the base layer and a top source/drain formed in each pillar of the plurality of pillars, wherein the top source/drain extends above the gate.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

99.

PASSIVE SEPARATION CASSETTE AND CARRIER

      
Application Number 18073229
Status Pending
Filing Date 2022-12-01
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Exley, James B.
  • Bandy, Ross
  • Strassner, James D.

Abstract

A system for holding and transporting one or more workpieces is disclosed. The system includes a cassette that is configured to support a carrier and a workpiece at two different elevations. In this way, as the carrier with the workpiece is placed on the cassette by a first robot, the carrier moves down further, as the workpiece is supported by taller support posts. The end effector of a second robot may then later remove only the workpiece from the cassette for processing. The processed workpiece is later placed back in the cassette by the second robot. This processed workpiece is then removed, along with the carrier, by the first robot. Carriers may be created to accommodate different sized workpieces such that the cassette remains unchanged.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
  • H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches

100.

METHODS AND MECHANISMS FOR AUTOMATIC SENSOR GROUPING TO IMPROVE ANOMALY DETECTION

      
Application Number 18075055
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-06-06
Owner Applied Materials, Inc. (USA)
Inventor
  • Lindner, Peter J.
  • Albright, John G.
  • Iskandar, Jimmy
  • Armacost, Michael D.

Abstract

An electronic device manufacturing system configured to obtain, by a processor, a plurality of datasets associated with a process recipe, wherein each dataset of the plurality of datasets comprises data generated by a plurality of sensors during a corresponding process run performed using the process recipe. The processor is further configured to determine, using the plurality of data sets associated with the process recipe, a correlation value between two or more sensors of the plurality of sensors. Responsive to the correlation value satisfying a threshold criterion, the processor assigns the two or more sensors to a cluster. During a subsequent process run, the processor generates an anomaly score associated with the cluster and indicative of an anomaly associated with at least one step of the subsequent process run.

IPC Classes  ?

  • G06F 18/25 - Fusion techniques
  • G06F 18/21 - Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
  • G06F 18/2113 - Selection of the most significant subset of features by ranking or filtering the set of features, e.g. using a measure of variance or of feature cross-correlation
  • G06F 18/23 - Clustering techniques
  • G06F 18/2433 - Single-class perspective, e.g. one-against-all classification; Novelty detection; Outlier detection
  1     2     3     ...     100        Next Page