Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.
A method of polishing includes bringing a substrate into contact with a polishing pad and generating relative motion between the substrate and the polishing pad, retaining the substrate on the polishing pad with a retainer, and during polishing of the substrate alternating between reducing a diameter of an inner surface of the retainer to clamp the substrate and increasing the diameter of the inner surface of the retainer to release the substrate from clamping while continuing to retain the substrate.
Embodiments of the present disclosure generally relate to apparatus and methods for reducing substrate backside damage during semiconductor device processing. In one implementation, a method of chucking a substrate in a substrate process chamber includes exposing the substrate to a plasma preheat treatment prior to applying a chucking voltage to a substrate support. In one implementation, a substrate support is provided and includes a body having an electrode and thermal control device disposed therein. A plurality of substrate supporting features are formed on an upper surface of the body, each of the substrate supporting features having a substrate supporting surface and a rounded edge.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/26 - Bombardment with wave or particle radiation
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
4.
GROUNDING TECHNIQUES FOR ESD POLYMERIC FLUID LINES
A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
F16L 11/127 - Hoses, i.e. flexible pipes made of rubber or flexible plastics with arrangements for particular purposes, e.g. specially profiled, with protecting layer, heated, electrically conducting electrically conducting
5.
FLUID-TIGHT ELECTRICAL CONNECTION TECHNIQUES FOR SEMICONDUCTOR PROCESSING
A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Embodiments of the disclosure relate to methods for forming silicon based gapfill within substrate features. A flowable silicon film is formed within the feature with a greater thickness on the bottom and top surfaces than the sidewall surface. An etch plasma removes the silicon film from the sidewall surface. A conversion plasma is used to convert the silicon film to a silicon based gapfill (e.g., silicon oxide). In some embodiments, the silicon film is preferentially converted on the top and bottom surface before being etched from the sidewall surface.
A method of reducing gallium particle formation in an ion implanter. The method may include performing a gallium implant process in the ion implanter, the gallium implant process comprising implanting a first dose of gallium ions from a gallium ion beam into a first set of substrates, while the first set of substrates are disposed in a process chamber of the beamline ion implanter. As such, a metallic gallium material may be deposited on one or more surfaces within a downstream portion of the ion implanter. The method may include performing a reactive gas bleed operation into at least one location of the downstream portion of the ion implanter, the reactive bleed operation comprising providing a reactive gas through a gas injection assembly, wherein the metallic gallium material is altered by reaction with the reactive gas.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
8.
SYSTEMS AND METHODS FOR OPTIMIZING FULL HORIZONTAL SCANNED BEAM DISTANCE
Provided herein are approaches for optimizing a full horizontal scanned beam distance of an accelerator beam. In one approach, a method may include positioning a first Faraday cup along a first side of an intended beam-scan area, positioning a second Faraday cup along a second side of the intended beam-scan area, scanning an ion beam along the first and second sides of the intended beam-scan area, measuring a first beam current of the ion beam at the first Faraday cup and measuring a second beam current of the ion beam at the second Faraday cup, and determining an optimal scan distance of the ion beam across the intended beam-scan area based on the first beam current and the second beam current.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
Embodiments disclosed herein include a method for cleaning a bevel area of a substrate support disposed within a plasma processing chamber. In one example the method begins by placing a cover substrate on a substrate support disposed in an interior volume of a processing chamber. A cleaning gas is provided into the interior volume of the processing chamber. A plasma is struck in the interior volume of the processing chamber. A cleaning gas is provided through the substrate support to a bevel edge area defined between an outer diameter of the cover substrate and an edge ring disposed on the substrate support.
Embodiments of the present disclosure generally relate to methods of modifying and engineering the effective thickness of an optical device substrate. The methods provide for depositing a material that is index-matched to the substrate to alter a thickness distribution of the optical device. By adjusting the thickness distribution, the optical path of light is modulated to direct the light to the output coupling grating.
Exemplary methods of OLED device processing are described. The methods may include forming an anode on a substrate. Forming the anode may include forming a first metal oxide material on the substrate, forming a metal layer over the first metal oxide material, forming a protective barrier over the metal layer, and forming a second metal oxide material over the amorphous protection material. The protective barrier may be an amorphous protection material overlying the metal layer.
H01L 51/44 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation - Details of devices
H01L 51/52 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED) - Details of devices
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
12.
PROCESS KITS AND RELATED METHODS FOR PROCESSING CHAMBERS TO FACILITATE DEPOSITION PROCESS ADJUSTABILITY
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide applicable for use in semiconductor manufacturing, includes a plate having a first face and a second face opposing the first face. The flow guide includes a first fin set extending from the second face, and a second fin set extending from the second face. The second fin set is spaced from the first fin set to define a flow path between the first fin set and the second fin set. The flow path has a serpentine pattern between the first fin set and the second fin set.
C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
13.
SPIN-ORBIT TORQUE MRAM STRUCTURE AND MANUFACTURE THEREOF
Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a semiconductor processing chamber, where a substrate may be positioned. The substrate may include a trench formed between two columns and molybdenum-containing metal regions in a plurality of recesses formed in at least one of the columns. At least two of the molybdenum-containing metal regions may be connected by a molybdenum-containing first liner formed on at least a portion of a sidewall of the trench. The methods may include forming a plasma of the oxygen-containing precursor. The methods may include contacting the molybdenum-containing first liner with plasma effluents of the oxygen-containing precursor, thereby forming an oxidized portion of molybdenum. The methods may include providing a halide precursor. The methods may include contacting oxidized portion of the molybdenum with plasma effluents of the halide precursor, thereby removing the oxidized portion of molybdenum from the sidewall of the trench.
A method of training a neural network includes obtaining two ground truth thickness profiles a test substrate, obtaining two thickness profiles for the test substrate as measured by an in-situ monitoring system while the test substrate is on polishing pads of different thicknesses, generating an estimated thickness profile for another thickness value that is between the two thickness values by interpolating between the two profiles, and training a neural network using the estimated thickness profile.
A carrier head for chemical mechanical polishing includes a housing, a substrate mounting surface, and a retaining ring assembly. The retaining ring assembly includes an inner ring surrounding the substrate mounting surface and having an inner surface to retain the substrate below the substrate mounting surface, a first actuator to adjust a vertical load on the inner ring, an outer ring surrounding the inner ring, and a second actuator positioned between the inner ring and the outer ring. The inner ring has a plurality of slots that are formed in a lower surface and that extend from the inner surface to an outer surface of the inner ring to divide the inner ring into a plurality of arcuate segments suspended from an upper portion. The second actuator applies a radially inward pressure such that the plurality of arcuate segments flex inwardly relative to the upper portion.
Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.
Molybdenum(0) and coordination complexes are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum disulfide, molybdenum nitride). The exposures can be sequential or simultaneous.
C07F 11/00 - Compounds containing elements of Groups 6 or 16 of the Periodic System
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
20.
METHODS AND MECHANISMS FOR PREVENTING FLUCTUATION IN MACHINE-LEARNING MODEL PERFORMANCE
An electronic device manufacturing system configured to receive, by a processor, input data reflecting a feature related to a manufacturing process of a substrate. The manufacturing system is further configured to generate a characteristic sequence defining a relationship between at least two manufacturing parameters, and determine a relationship between one or more variables related to the feature and the characteristic sequence. The manufacturing system is further configured to determine a weight based on the determined relationship and apply the weight to the feature. The manufacturing system is further configured to train a machine-learning model in view of the weighted feature.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
A sensor device comprises a quartz crystal microbalance (QCM) and a coating on at least a portion of a surface of the QCM, wherein the coating selectively reacts with radicals of a target gas and does not react with stable molecules of the target gas. The QCM is configured such that a resonant frequency of the QCM changes in response to reaction of the radicals of the target gas with the coating, wherein the change in the resonant frequency of the QCM correlates to an amount of the radicals of the target gas that have reacted with the coating.
A system for nanoimprint lithography includes a master holder, a spacer, and a stamp support. The spacer supports the stamp support as a stamp material is cured to create a stamp. A method of forming an optical device using the nanoimprint lithography system with a spacer is provided. A system for the nanoimprint lithography may also include a master and a stamp support holder. The stamp support holder includes a plurality of projections defining a plurality of vacuum channels. The vacuum channels are in fluid communication with a vacuum source to support a stamp support as a stamp material is cured to create a stamp.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
A lamp and epitaxial processing apparatus are described herein. In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.
A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the upper insulator structure surface. The first portion of the upper insulator structure surface forms an interior volume with the lower plate structure surface.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
25.
SEMICONDUCTOR DEVICE PACKAGES WITH ENHANCED THERMO-MECHANICAL RELIABILITY
The present disclosure relates to thin-form-factor semiconductor device packages, and methods and systems for forming the same. Embodiments of the disclosure include methods and apparatus for forming semiconductor device packages that include frames that are coated with a layer of a coupling agent on which subsequently layers are formed. The utilization of the coupling agent between the frame and subsequently formed layers enhances the thermo-mechanical reliability of the package frames by mitigating the stress induced by any subsequently formed insulation layers and/or RDLs, and by providing improved coupling between such layers and the relatively smooth surfaces of the frames.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.
Methods and systems for monitoring wafer processing results continuously and in real-time. In some embodiments, a system may comprise at least one non-active chamber with at least one feedthrough access port which is configured to interact with a metrology apparatus. The feedthrough access port has a surface exposed to an inner volume of the non-active chamber and has a fluorine-based coating covering the surface. The non-active chamber has a wafer access port to one or more other chambers. The metrology apparatus is positioned external to the non-active chamber and is oriented to detect metrology data through one of the feedthrough access ports. A data collection apparatus is connected to the metrology apparatus and configured to continuously receive data from the metrology apparatus.
Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate comprises forming a plasma reaction between titanium tetrachloride (TlCl4), hydrogen (H2), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.
C23C 16/507 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using external electrodes, e.g. in tunnel type reactors
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes determining, based on a guardband, guardband violation data points of the plurality of data points of the trace data. The method further includes determining, based on the guardband violation data points, guardband violation shape characterization. Classification of additional guardband violation data points of additional trace data is to be based on the guardband violation shape characterization. Performance of a corrective action associated with the substrate processing system is based on the classification.
A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.
Embodiments of the disclosure include an apparatus and method of forming a memory device with high-mobility oxide semiconductor channels. In some embodiments, the apparatus, for example, includes a plurality of alternating layers formed over a surface of a substrate; a gate coupled to each of the word line layers of the plurality of alternating layers; a multi-layer channel memory cell having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region, the multi-layer channel also having a first conductive layer and a second conductive layer, the first conductive layer being different from the second conductive layer; and an ONO layer stack disposed between the gates and the multi-layer channel, wherein the ONO layer stack extends in the first direction between the source region and the drain region.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
32.
HARDWARE TO UNIFORMLY DISTRIBUTE ACTIVE SPECIES FOR SEMICONDUCTOR FILM PROCESSING
A substrate processing system is provided having a processing chamber. The processing chamber includes a lid plate, one or more chamber sidewalls, and a chamber base that collectively define a processing volume. An annular plate is coupled to the lid plate, and an edge manifold is fluidly coupled to the processing chamber through the annular plate and the lid plate. The substrate processing system includes a center manifold that is coupled to the lid plate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
34.
REGENERATION ANNEAL OF METAL OXIDE THIN-FILM TRANSISTORS
A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150° C. to about 275° C.
Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-κ metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-κ metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates that have property values that meet threshold values. The method further includes determining, based on the trace data, a dynamic acceptable area outside of guardband limits. The method further includes causing, based on the dynamic acceptable area outside of the guardband limits, performance of a corrective action associated with the substrate processing system.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes generating, based on the trace data and a plurality of allowable types of variance, a guardband including an upper limit and a lower limit for fault detection. The method further includes causing, based on the guardband, performance of a corrective action associated with the substrate processing system.
Embodiments described herein relate to a method of using an apparatus for forming waveguides. The method includes positioning a substrate at a first rotation angle, exposing the substrate to an ion beam, forming first partial trenches defined by adjacent angled device structures with the first device angle, rotating the substrate to a second rotation angle, exposing the substrate to the ion beam, etching the first partial trenches, and repeating the method from about 1 cycle to about 100 cycles to form a plurality of trenches defined by adjacent angled device structures. The first rotation angle is selected to form one or more angled device structures with a first device angle relative to a vector parallel to the substrate. The ion beam is configured to contact the substrate at a beam angle ϑ relative to a surface normal of the substrate.
A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.
Embodiments of the present disclosure generally relate to a substrate processing chamber, and methods for cleaning the substrate processing chamber are provided herein. An electrode cleaning ring is disposed in a lower portion of a process volume (e.g., disposed below a substrate support in the process volume). The electrode cleaning ring is a capacitively coupled plasma source. The electrode cleaning ring propagates plasma into the lower portion of the process volume. RF power is provided to the electrode cleaning ring via an RF power feed-through. The RF plasma propagated by the electrode cleaning ring removes deposition residue in the lower portion of the process volume.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
42.
EPI SELF-HEATING SENSOR TUBE AS IN-SITU GROWTH RATE SENSOR
A method and apparatus for determining a growth rate on a semiconductor substrate is described herein. The apparatus is an optical sensor, such as an optical growth rate sensor. The optical sensor is positioned in an exhaust of a deposition chamber. The optical sensor is self-heated using one or more internal heating elements, such as a resistive heating element. The internal heating elements are configured to heat a sensor coupon. A film is formed on the sensor coupon by exhaust gases flowed through the exhaust and is correlated to film growth on a substrate within a process volume of the deposition chamber.
G01N 21/84 - Systems specially adapted for particular applications
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Disclosed are approaches for forming semiconductor device layers. One method may include forming a plurality of openings in a semiconductor structure, and forming a film layer atop the semiconductor structure by delivering a material at a non-zero angle relative to a normal extending perpendicular from an upper surface of the semiconductor structure. The film layer may be formed along the upper surface of the semiconductor structure without being formed along a sidewall of each opening of the plurality of openings, wherein an opening though the film layer remains above each opening of the plurality of openings.
A method of forming a structure on a substrate is provided. The method includes depositing a dipole dopant containing (DDC) layer including a dipole dopant on a first and second region of a dielectric layer (DL) of the substrate. A hardmask (HM) is deposited over the DDC deposited on the first and the second regions. A patterned photoresist layer (PR) is formed over the HM. The PR includes a first portion that is positioned over the first region and an opening that is positioned to expose a portion of the HM that is disposed over the second region of the substrate. The HM and DDC within the second region are etched and at least a portion of the DL is exposed within the second region. The PR is removed and the substrate is annealed to diffuse the dipole dopant into a portion of the DL disposed in the first region.
Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
46.
HIGH-TEMPERATURE SUBSTRATE SUPPORT ASSEMBLY WITH FAILURE PROTECTION
A substrate support assembly includes a puck, comprising a heating element, a power distribution assembly, and an insulator comprising at least one of alumina or thermoplastic disposed between the puck and the power distribution assembly, wherein an electrical connection between the heating element and the power distribution assembly comprises a terminal and a conical washer.
H05B 3/26 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor mounted on insulating base
47.
HYBRID ION SOURCE FOR ALUMINUM ION GENERATION USING A TARGET HOLDER AND ORGANOALUMINIUM COMPOUNDS
An ion source that is capable of different modes of operation is disclosed. The ion source includes an insertable target holder includes a hollow interior into which the solid dopant material is disposed. The target holder may a porous surface at a first end, through which vapors from the solid dopant material may enter the arc chamber. The porous surface inhibits the passage of liquid or molten dopant material into the arc chamber. The target holder is also constructed such that it may be refilled with dopant material when the dopant material within the hollow interior has been consumed. The ion source may have several gas inlets. When the insertable target holder is used, the ion source may supply a first gas, such as a halogen containing gas. When operating in a second mode, the ion source may utilize an organoaluminium gas.
A system and method for reducing charge on a workpiece disposed on a platen is disclosed. The system includes an ionizer to generate ionized gas from the source of backside gas. The ionizer may be used to introduce ionized gas into the backside gas channels of the platen. A controller is used to selectively allow backside gas and/or ionized gas into the backside gas channels. In certain embodiments, the platen also includes an exhaust channel in communication with an exhaust valve to ensure that the pressure within the volume between the top surface of the platen and the workpiece is maintained in a desired range. In one embodiment, the system includes a valving system in communication with the source of backside gas and also in communication with the ionizer. In another embodiment, the amount of ionization performed by the ionizer is programmable.
A method includes receiving, by a processing device, first data. The first data includes data from one or more sensors of a processing chamber and is associated with a processing operation. The first data is resolved in at least two dimensions, one of which is time. The method further includes providing the first data to a model. The method further includes receiving from the model second data. The second data includes an indication of an evolution of a processing parameter during the processing operation. The method further includes causing performance of a corrective action in view of the second data.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
50.
HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHOD
Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
A first robot arm places a calibration object into a load lock that separates a factory interface from a transfer chamber using a first taught position. A second robot arm retrieves the calibration object from the load lock using a second taught position. A controller determines, using a sensor, a first offset amount between a calibration object center of the calibration object and a pocket center of the second robot arm. The controller determines a characteristic error value that represents a misalignment between the first taught position of the first robot arm and the second taught position of the second robot arm based on the first offset amount. The first robot arm or the second robot arm uses the first characteristic error value to compensate for the misalignment for objects transferred between the first robot arm and the second robot arm via the load lock.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
B65G 47/90 - Devices for picking-up and depositing articles or materials
B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices
B25J 11/00 - Manipulators not otherwise provided for
52.
PHYSICALLY-INFORMED MULTI-SYSTEM HARDWARE OPERATING WINDOWS
Embodiments disclosed herein include a method for use with a semiconductor processing tool. In an embodiment, the method comprises configuring the semiconductor processing tool, running a benchmark test on the semiconductor processing tool, providing hardware operating window (HOW) analytics, generating a design of experiment (DoE) using the HOW analytics, implementing process optimization, and releasing an iteration of the process recipe. In an embodiment, the method further comprises margin testing the iteration of the process recipe.
Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.
A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of a surface of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source; and applying the dose map to process the substrate using the patterning energy source.
A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source. The method may include applying the dose map to process the substrate using the patterning energy source, wherein the dose map is applied by performing a plurality of exposures of the substrate to the patterning energy source, at a plurality of different twist angles.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
56.
DRUG COMPOSITIONS AND METHODS OF PREPARING THE SAME
Methods for providing an inorganic oxide coating to high aspect ratio particles containing an active pharmaceutical ingredient are described as are compositions containing such coated particles.
Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. In one or more embodiments, a process chamber comprises a first window, a second window, a substrate support disposed between the first window and the second window, and a motorized rotatable radiant spot heating source disposed over the first window and configured to provide radiant energy through the first window.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
F27B 17/00 - Furnaces of a kind not covered by any of groups
F27D 5/00 - Supports, screens, or the like for the charge within the furnace
B23K 26/00 - Working by laser beam, e.g. welding, cutting or boring
B23K 26/08 - Devices involving relative movement between laser beam and workpiece
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
B23K 26/06 - Shaping the laser beam, e.g. by masks or multi-focusing
Embodiments herein include void-free material depositions on a substrate (e.g., in a void-free trench-filled (VFTF) component) obtained using directional etching to remove predetermined portions of a seed layer covering the substrate. In several embodiments, directional etching followed by selective deposition can enable fill material (e.g., metal) patterning in tight spaces without any voids or seams. Void-free material depositions may be used in a variety of semiconductor devices, such as transistors, dual work function stacks, dynamic random-access memory (DRAM), non-volatile memory, and the like.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
Flexible display devices, such as flexible cover lens films, are discussed and provided herein. The flexible cover lens film has good strength, elasticity, optical transmission, wear resistance, and thermostability. The cover lens film includes a hard coat layer with a thickness from about 5 μm to 40 μm, an impact absorption layer with a thickness from about 20 μm to 110 μm, and a substrate layer with a thickness from about 10 μm to 175 μm and is disposed between the hard coat layer and the impact absorption layer. By combining the hard coat layer and the impact resistant layer, the cover lens film is both flexible and strong with hardness from 6H to 9H.
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a plurality of channels for delivering one or more radical beams to a workpiece, wherein each of the plurality of channels has a lengthwise axis oriented at a non-zero angle relative to a perpendicular extending from a main surface of the workpiece, wherein each channel of the plurality of channels has a channel length and a channel width, and wherein the channel width varies along the channel length.
A method for forming a nanosheet device. The method may include providing a heterostructure device stack above a semiconductor substrate. The method may include patterning the heterostructure device stack to define a dummy gate region, and before forming a source drain recess adjacent the dummy gate region, selectively removing a first set of sacrificial layers of the heterostructure device stack within the dummy gate region.
Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
METHODS, SYSTEMS, AND APPARATUS FOR CONDUCTING A CALIBRATION OPERATION FOR A PLURALITY OF MASS FLOW CONTROLLERS (MFCS) OF A SUBSTRATE PROCESSING SYSTEM
Aspects generally relate to methods, systems, and apparatus for conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system. In one aspect, a corrected flow curve is created for a range of target flow rates across a plurality of setpoints. In one implementation, a method of conducting a calibration operation for a plurality of mass flow controllers (MFCs) of a substrate processing system includes prioritizing the plurality of MFCs for the calibration operation. The prioritizing includes determining an operation time for each MFC of the plurality of MFCs, and ranking the plurality of MFCs in a rank list according to the operation time for each MFC. The method includes conducting the calibration operation for the plurality of MFCs according to the rank list and during an idle time for the substrate processing system.
G01F 15/00 - MEASURING VOLUME, VOLUME FLOW, MASS FLOW, OR LIQUID LEVEL; METERING BY VOLUME - Details of, or accessories for, apparatus of groups insofar as such details or appliances are not adapted to particular types of such apparatus
G01F 25/17 - Testing or calibration of apparatus for measuring volume, volume flow or liquid level or for metering by volume of flowmeters using calibrated reservoirs
64.
METHODS FOR CONTROLLING PULSE SHAPE IN ALD PROCESSES
Methods for controlling pulse shape in ALD processes improves local non-uniformity issues of films deposited on substrate surface. The methods include using a variable flow valve creating predetermined pulse shape when a reactant is provided on a substrate surface.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer a nitrogen trifluoride-containing gas to inhibit growth of the nucleation layer at narrow portions within the at least one opening. The method includes exposing the at least one opening to the tungsten-containing precursor gas to form a fill layer over the nucleation layer within the at least one opening. The method includes exposing the at least one opening of the substrate to the nitrogen trifluoride-containing gas or a nitrogen-containing plasma to inhibit growth of portions of the fill layer along the at least one opening.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
66.
HYBRID ION SOURCE FOR ALUMINUM ION GENERATION USING ORGANOALUMINIUM COMPOUNDS AND A SOLID TARGET
An ion source that is capable of different modes of operation is disclosed. A solid target may be disposed in the arc chamber. The ion source may have several gas inlets, in communication with different gasses. When operating in a first mode, the ion source may supply a first gas, such as a halogen containing gas. When operating in a second mode, the ion source may supply an organoaluminium gas. Ions having single charges may be created in the first mode, while ions having multiple charges may be created in the second mode. In some embodiments, the solid target may be retractable.
An ion source that is capable of different modes of operation is disclosed. The ion source includes an insertable target holder includes a hollow interior into which the solid dopant material is disposed. The target holder may a porous surface at a first end, through which vapors from the solid dopant material may enter the arc chamber. The porous surface inhibits the passage of liquid or molten dopant material into the arc chamber. The target holder is also constructed such that it may be refilled with dopant material when the dopant material within the hollow interior has been consumed. A solid target is also disposed in the arc chamber. When the insertable target holder is used, multicharged ions are created. When the insertable target holder is retracted, single charged ions are created by only etching the solid dopant-containing compound.
Exemplary fluid delivery assemblies for a semiconductor processing system may include a liquid delivery source. The assemblies may include a heater that is fluidly coupled with an outlet of the liquid delivery source. The assemblies may include a liquid flow controller that is fluidly coupled with the liquid delivery source downstream of the heater. The assemblies may include a liquid vaporizer fluidly coupled with a downstream end of the liquid flow controller. The assemblies may include a chamber delivery line coupled with an output of the liquid vaporizer.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a perpendicular extending from a main surface of the workpiece.
A microLED-quality layer of gallium nitride (GaN) may be formed above a silicon substrate for microLED devices to be formed. Typically, mismatches between the crystal lattice of the GaN and the silicon substrate cause internal stresses that bow the wafer. To relieve these stresses, a pattern of trenches may be etched into the GaN layer between the die or device footprints. These trenches may be etched through the GaN layer, down to the depth of the silicon substrate, or even down into the silicon substrate. Instead of one singular, large wafer with internal stresses, the wafer may thus be divided into multiple small sections with minimal internal stresses. A dielectric gap fill may be applied to fill the trenches, and the resulting wafer may be planarized to expose the surface of the GaN after the gap fill.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
71.
Etch Rate Modulation of FinFET Through High-Temperature Ion Implantation
A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.
Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/02 - Pretreatment of the material to be coated
Embodiments of the disclosure include a polishing pad for planarizing a surface of a substrate during a polishing process. The polishing pad includes a base layer, comprising a first material composition, and a polishing layer disposed over the base layer. The polishing layer includes a second material composition that is exposed at a polishing surface of the polishing pad, wherein the polishing surface is configured to contact the surface of the substrate during the polishing process. The second material composition includes a polishing layer material having a hardness that is greater than 50 on a Shore D scale, a yield point strength, a yield point strength strain, a break point strength, and an elongation at break point strain, wherein a magnitude of a difference between the elongation at break point strain and the yield point strength strain is greater than the magnitude of yield point strength strain when measured at room temperature.
Embodiments of the present disclosure generally relate to inductively coupled plasma sources and plasma processing apparatus. In at least one embodiment, plasma source includes a first sidewall and a gas injection insert defining a plasma source interior volume. The gas injection insert includes a peripheral gas injection port, a second sidewall disposed concentric with the first sidewall, and a center gas injection port. The plasma source includes a first induction coil disposed proximate the first sidewall and disposed around the first sidewall. The plasma source includes a first radio frequency power generator coupled with the first induction coil. The plasma source includes a second induction coil disposed proximate the second sidewall and disposed around the second sidewall. The plasma source includes a second radio frequency power generator coupled with the second induction coil.
Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first surface that faces the carrier body and a second surface opposite the first surface. The carrier heads may include at least one downforce control actuator disposed above the first surface of the inner ring at a discrete position about a circumference of the inner ring.
A mesa etch may form the geometry of microLED structures. However, the mesa etch may induce defects in the microLED structures that decreases the efficiency of the microLEDs. To correct these defects, a dry etch process may be performed that incrementally removes the surface layers of the microLED structures with the defects. The dry etch may be configured to incrementally remove a small outer layer, and thus may preserve the overall shape of the microLED structures while leaving a smooth surface for the application of a dielectric layer. The dry etch process may include two steps that are repeatedly performed. A first gas may react with the surface to form a gallium compound layer, and a second gas may then selectively remove that layer. The dry etch may include plasma-based etches or reactive thermal etches.
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Exemplary methods of semiconductor processing may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include forming a plasma of the carbon-containing precursor within the processing region. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more features along the substrate. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include treating the carbon-containing material with plasma effluents of the hydrogen-containing precursor. The plasma effluents of the hydrogen-containing precursor may cause a portion of the carbon-containing material to be removed from the substrate.
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.
Embodiments disclosed herein include a processing tool. In an embodiment, the processing tool comprises a power supply, an impedance matching network coupled to the power supply, a cathode, wherein the power supply is configured to supply power through the impedance matching network to the cathode, and a processing module, wherein the processing module is communicatively coupled to the power supply and the impedance matching network.
Embodiments disclosed herein include a processing tool. In an embodiment the processing tool comprises a transmission line sensor, and an analog to digital (A/D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC), and a frequency digital phase lock loop (dPLL). In an embodiment, the processing tool may further comprise a transmission line scaling module.
Embodiments disclosed herein include a sensor. In an embodiment, the sensor comprises a board, wherein an aperture is formed through the board, a current loop winding through the board around the aperture, and a voltage ring around the aperture and within an inner perimeter of the current loop, wherein the voltage ring comprises an interior ring, an insulator ring around the interior ring, and an exterior ring around the insulator ring.
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
G01R 15/18 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
Described herein is a method for etching a sample. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas flow comprising silicon tetrachloride (SiCl4) and a diluent towards the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first time period. Then, a source power is applied to achieve a source state for a second time period, and then no bias power and no source power is applied to achieve a recovery state for a third time period. The plasma etch pulse is repeated until a target amount of the sample is etched.
Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a metal precursor and an oxidant to form a transition metal oxide film; the transition metal oxide film is exposed to a chalcogenide precursor to form the transition metal dichalcogenide film.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 27/11556 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with floating gate characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 27/11582 - Electrically programmable read-only memories; Multistep manufacturing processes therefor with charge-trapping gate insulators, e.g. MNOS or NROM characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.
Embodiments of the present disclosure relate to methods, systems, and apparatus for inkjet printing self-assembled monolayer (SAM) structures on substrates. In one embodiment, which can be combined with other embodiments, one or more SAM layers are printed on a substrate surface of a substrate in a localized manner such that a portion of the substrate surface is left exposed to a processing region of the inkjet chamber. The printing includes spraying one or more subsections of the substrate surface with an ink, the ink having a SAM composition. The SAM composition includes an active component, and a hydrophobic tail.
Process chamber lids having a pumping liner with a showerhead and gas funnel within an open central region are described. The showerhead is spaced a distance from the gas funnel to form a gap and the gas funnel has an opening to provide a flow of gas into the gap. The gas funnel includes a plurality of apertures extending from the front surface to a common region adjacent the back surface of the gas funnel. A purge ring is in contact with the back surface of the gas funnel and aligned so that a circular channel formed in the bottom surface of the purge ring body is positioned adjacent the common area of the apertures in the gas funnel.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.
An apparatus comprises a flexible membrane for use with a carrier head of a substrate chemical mechanical polishing apparatus. The membrane comprises an outer surface providing a substrate receiving surface, wherein the outer surface has a central portion and an edge portion surrounding the central portion, wherein the central portion has a first surface roughness and the edge portion has a second surface roughness, the first surface roughness being greater than the second surface roughness.
Embodiments described herein generally relate to process chambers with coaxial lift devices. In some embodiments, the device comprises both a bottom bowl lift and a pedestal lift. The bottom bowl lift supports a bottom bowl and is configured to move the bottom bowl into a position that reduces the process volume. The bottom bowl lift is co-axial with the pedestal lift and the bottom bowl lift and the pedestal lift are attached for vacuum operation. The pedestal lift includes multiple actuators to create a dynamic lift mechanism. Both systems complete a nested system such that the bottom bowl lift is adjustable and can close the bottom bowl creating a symmetric and small process volume. The pedestal lift can move independently to its process position and tilt in a desired direction without interference with the bottom bowl lift, increasing film uniformity on a processed substrate.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Embodiments described herein generally relate to process chambers with coaxial lift devices. In some embodiments, the device comprises both a bottom bowl lift and a pedestal lift. The bottom bowl lift supports a bottom bowl and is configured to move the bottom bowl into a position that reduces the process volume. The bottom bowl lift is co-axial with the pedestal lift and the bottom bowl lift and the pedestal lift are attached for vacuum operation. The pedestal lift includes multiple actuators to create a dynamic lift mechanism. Both systems complete a nested system such that the bottom bowl lift is adjustable and can close the bottom bowl creating a symmetric and small process volume. The pedestal lift can move independently to its process position and tilt in a desired direction without interference with the bottom bowl lift, increasing film uniformity on a processed substrate.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
A chemical mechanical polishing apparatus includes a platen having a top surface to hold a polishing pad, a carrier head to hold a substrate against a polishing surface of the polishing pad during a polishing process, and a temperature monitoring system. The temperature monitoring system includes a non-contact thermal sensor positioned above the platen that has a field of view of a portion of the polishing pad on the platen. The sensor is rotatable by the motor around an axis of rotation so as to move the field of view across the polishing pad.
B24B 37/10 - Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
B24B 37/22 - Lapping pads for working plane surfaces characterised by a multi-layered structure
Embodiments described herein provide methods and apparatus used to control a processing result profile proximate to a circumferential edge of a substrate during the plasma-assisted processing thereof. In one embodiment, a substrate support assembly features a first base plate and a second base plate circumscribing the first base plate. The first and second base plates each have one or more respective first and second cooling disposed therein. The substrate support assembly further features a substrate support disposed on and thermally coupled to the first base plate, and a biasing ring disposed on and thermally coupled to the second base plate. Here, the substrate support and the biasing ring are each formed of a dielectric material. The substrate support assembly further includes an edge ring biasing electrode embedded in the dielectric material of the biasing ring and an edge ring disposed on the biasing ring.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Exemplary semiconductor substrate carrier frames may include a frame body defining a central aperture. The frames may include a plurality of fingers that are coupled with the frame body. Each of the plurality of fingers may extend into the central aperture. Each of the plurality of fingers may include a substrate receiving interface. At least one of the plurality of fingers may include an actuator that manipulates a respective one of the at least one of the plurality of fingers between a substrate holding position and an open position.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
94.
COMPLIANT INNER RING FOR A CHEMICAL MECHANICAL POLISHING SYSTEM
Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first end having a first surface that faces the carrier body and a second end having a second surface opposite the first surface. The second end of the inner ring may be radially displaceable. The carrier heads may include an outer ring having an inner surface that is disposed against an outer surface of the inner ring.
An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/52 - Controlling or regulating the coating process
96.
SILICON-AND-CARBON-CONTAINING MATERIALS WITH LOW DIELECTRIC CONSTANTS
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the oxygen-containing precursor at a temperature less than or about 700° C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.
Embodiments disclosed herein include a process power controller for a plasma processing tool. In an embodiment, the process power controller includes a process power source optimizer, a source predictor, and a process uniformity controller. In an embodiment, the source predictor is communicatively coupled to the process power source optimizer and the process uniformity controller.
Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool. In an embodiment, the method comprises measuring a voltage and a current of a transmission line, converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal, calculating a u-vector from the digital voltage signal and the digital current signal, calculating a C1 position of a first capacitor with real components of the u-vector, and calculating a C2 position of a second capacitor with imaginary components of the u-vector.
A shadow ring for a processing chamber, such as a semiconductor processing chamber, is an annular member including a body with a radially inwardly projecting lip. The shadow ring includes a feature that mitigates heat transfer between the lip and the rest of the body. In one example, the feature includes a plurality of apertures, each aperture extending from an upper opening at an upper surface of the shadow ring to a corresponding lower opening at a lower surface of the shadow ring. A neck between adjacent apertures creates a bottleneck that hinders conductive heat transfer.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for heating the substrate
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
100.
OZONE-BASED LOW TEMPERATURE SILICON OXIDE COATING FOR PHARMACEUTICAL APPLICATIONS
This disclosure pertains to coated drug compositions and methods of preparing coated drug compositions with a low temperature o-zone based silicon oxide coating. Specifically, the instant application discloses a method to coat active pharmaceutical ingredient particles using a silicon precursor and ozone at a low temperature.
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