A method and apparatus for determining a growth rate on a semiconductor substrate is described herein. The apparatus is an optical sensor, such as an optical growth rate sensor. The optical sensor is positioned in an exhaust of a deposition chamber. The optical sensor is self-heated using one or more internal heating elements, such as a resistive heating element. The internal heating elements are configured to heat a sensor coupon. A film is formed on the sensor coupon by exhaust gases flowed through the exhaust and is correlated to film growth on a substrate within a process volume of the deposition chamber.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C30B 25/14 - Feed and outlet means for the gases; Modifying the flow of the reactive gases
G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
2.
GROUNDING TECHNIQUES FOR ESD POLYMERIC FLUID LINES
A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 47/12 - Drives or gearings for grinding machines or devices; Equipment therefor for rotating or reciprocating working-spindles carrying grinding wheels or workpieces by mechanical gearing or electric power
B24B 37/30 - Work carriers for single side lapping of plane surfaces
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
3.
CONTROLLING LIGHT SOURCE WAVELENGTHS FOR SELECTABLE PHASE SHIFTS BETWEEN PIXELS IN DIGITAL LITHOGRAPHY SYSTEMS
A digital lithography system may adjust a wavelength of the light source to compensate for tilt errors in micromirrors while maintaining a perpendicular direction for the reflected light. Adjacent pixels may have a phase shift that is determined by an optical path difference between their respective light beams. This phase shift may be preselected to be any value by generating a corresponding wavelength at the light source based on the optical path difference. To generate a specific wavelength corresponding to the desired phase shift, the light source may produce multiple light components that have wavelengths that bracket the wavelength of the selected phase shift. The intensities of these components may then be controlled individually to produce an effect that approximates the selected phase shift on the substrate.
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a semiconductor processing chamber, where a substrate may be positioned. The substrate may include a trench formed between two columns and molybdenum-containing metal regions in a plurality of recesses formed in at least one of the columns. At least two of the molybdenum-containing metal regions may be connected by a molybdenum-containing first liner formed on at least a portion of a sidewall of the trench. The methods may include forming a plasma of the oxygen-containing precursor. The methods may include contacting the molybdenum-containing first liner with plasma effluents of the oxygen-containing precursor, thereby forming an oxidized portion of molybdenum. The methods may include providing a halide precursor. The methods may include contacting oxidized portion of the molybdenum with plasma effluents of the halide precursor, thereby removing the oxidized portion of molybdenum from the sidewall of the trench.
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Embodiments of the disclosure relate to methods for forming silicon based gapfill within substrate features. A flowable silicon film is formed within the feature with a greater thickness on the bottom and top surfaces than the sidewall surface. An etch plasma removes the silicon film from the sidewall surface. A conversion plasma is used to convert the silicon film to a silicon based gapfill (e.g., silicon oxide). In some embodiments, the silicon film is preferentially converted on the top and bottom surface before being etched from the sidewall surface.
Methods and systems for monitoring wafer processing results continuously and in real-time. In some embodiments, a system may comprise at least one non-active chamber with at least one feedthrough access port which is configured to interact with a metrology apparatus. The feedthrough access port has a surface exposed to an inner volume of the non-active chamber and has a fluorine-based coating covering the surface. The non-active chamber has a wafer access port to one or more other chambers. The metrology apparatus is positioned external to the non-active chamber and is oriented to detect metrology data through one of the feedthrough access ports. A data collection apparatus is connected to the metrology apparatus and configured to continuously receive data from the metrology apparatus.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
7.
SYSTEMS AND METHODS FOR OPTIMIZING FULL HORIZONTAL SCANNED BEAM DISTANCE
Provided herein are approaches for optimizing a full horizontal scanned beam distance of an accelerator beam. In one approach, a method may include positioning a first Faraday cup along a first side of an intended beam-scan area, positioning a second Faraday cup along a second side of the intended beam-scan area, scanning an ion beam along the first and second sides of the intended beam-scan area, measuring a first beam current of the ion beam at the first Faraday cup and measuring a second beam current of the ion beam at the second Faraday cup, and determining an optimal scan distance of the ion beam across the intended beam-scan area based on the first beam current and the second beam current.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.
Embodiments of the present disclosure generally relate to methods of modifying and engineering the effective thickness of an optical device substrate. The methods provide for depositing a material that is index-matched to the substrate to alter a thickness distribution of the optical device. By adjusting the thickness distribution, the optical path of light is modulated to direct the light to the output coupling grating.
A system may include a first semiconductor processing station configured to deposit a material on a first semiconductor wafer and a chemical tank that provides liquid to the processing station during a deposition process. The chemical tank may provide measurements of characteristics of the liquid to a controller. The controller may be configured to receive the measurements from the chemical tank; provide an input based on the measurements to a trained model that is configured to generate an output that adjusts an operating parameter of the first station such that the thickness uniformity of the material is closer to a target thickness uniformity; and cause the first station to deposit the material on a second wafer using the operating parameter as adjusted by the output.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A carrier head for chemical mechanical polishing includes a housing, a substrate mounting surface, and a retaining ring assembly. The retaining ring assembly includes an inner ring surrounding the substrate mounting surface and having an inner surface to retain the substrate below the substrate mounting surface, a first actuator to adjust a vertical load on the inner ring, an outer ring surrounding the inner ring, and a second actuator positioned between the inner ring and the outer ring. The inner ring has a plurality of slots that are formed in a lower surface and that extend from the inner surface to an outer surface of the inner ring to divide the inner ring into a plurality of arcuate segments suspended from an upper portion. The second actuator applies a radially inward pressure such that the plurality of arcuate segments flex inwardly relative to the upper portion.
B24B 37/005 - Control means for lapping machines or devices
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
422), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.
Methods and apparatus for processing a substrate are provided herein. For example, a processing volume for processing a substrate and a pressure system in fluid communication with the processing volume and comprising a throttle valve assembly including a housing, a sensing device disposed in an interior of the housing, and a fan open to the interior of the housing, wherein, during operation of the pressure system to control a pressure within the processing volume, the sensing device is responsive to temperature changes in the interior of the housing such that the fan remains off when a temperature of the interior of the housing is less than a predetermined temperature and automatically turns on when the temperature within interior of the housing is equal to or greater than the predetermined temperature.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/52 - Controlling or regulating the coating process
15.
DIRECT WORD LINE CONTACT AND METHODS OF MANUFACTURE FOR 3D MEMORY
Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.
A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the upper insulator structure surface. The first portion of the upper insulator structure surface forms an interior volume with the lower plate structure surface.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
A sensor device comprises a quartz crystal microbalance (QCM) and a coating on at least a portion of a surface of the QCM, wherein the coating selectively reacts with radicals of a target gas and does not react with stable molecules of the target gas. The QCM is configured such that a resonant frequency of the QCM changes in response to reaction of the radicals of the target gas with the coating, wherein the change in the resonant frequency of the QCM correlates to an amount of the radicals of the target gas that have reacted with the coating.
tt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes generating, based on the trace data and a plurality of allowable types of variance, a guardband including an upper limit and a lower limit for fault detection. The method further includes causing, based on the guardband, performance of a corrective action associated with the substrate processing system.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G05B 19/404 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
A system for nanoimprint lithography includes a master holder, a spacer, and a stamp support. The spacer supports the stamp support as a stamp material is cured to create a stamp. A method of forming an optical device using the nanoimprint lithography system with a spacer is provided. A system for the nanoimprint lithography may also include a master and a stamp support holder. The stamp support holder includes a plurality of projections defining a plurality of vacuum channels. The vacuum channels are in fluid communication with a vacuum source to support a stamp support as a stamp material is cured to create a stamp.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
22.
ANALYSIS OF MULTI-RUN CYCLIC PROCESSING PROCEDURES
A method includes receiving time trace sensor data associated with a substrate processing procedure. The substrate processing procedure includes two or more sets of processing conditions. At least a first set of processing conditions and a second set of processing conditions each include one or more operations performed repeatedly. The method further includes separating a first and second portion of the time trace sensor data corresponding to the first and second sets of processing conditions into a first and second plurality of cycle data. The method further includes processing the first plurality of cycle data and the second plurality of cycle data to generate summary data. The method further includes providing an alert to s user. The alert is based on the summary data.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
A carrier transport system (100) for transporting carriers in a vacuum processing system in a main transport direction (T) along a first transport path (T1) and along a second transport path (T2) extending next to the first transport path (T1) and for transferring carriers in a path switch direction (S) between the first transport path (T1) and the second transport path (T2) is described. The carrier transport system comprises a common movable support (119) at which a first carrier holder (110) and a second carrier holder (120) are provided spaced apart from each other in the path switch direction (S). In a first transport state (i) of the common movable support (119), the first carrier holder (110) is configured to hold a first carrier (10) in alignment with the first transport path (T1) and the second carrier holder (120) is configured to hold a second carrier (20) in alignment with the second transport path (T2) laterally spaced apart from the first carrier (10). The common movable support is movable in the path switch direction (S) for moving the first carrier holder (110) and the second carrier holder (120) synchronously in the path switch direction (S). Further described is a vacuum deposition system with such a carrier transport system as well as methods of transporting carriers in a vacuum processing system.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
24.
CARRIER FOR HOLDING A SUBSTRATE, APPARATUS FOR DEPOSITING A LAYER ON A SUBSTRATE, AND METHOD FOR SUPPORTING A SUBSTRATE
A carrier (100) for holding a substrate (10) in a curved state is provided. The carrier (100) comprises a carrier body (110) having a curved substrate support surface (111), a sealing (120) for providing a sealing between an edge of the substrate (10) and the carrier body (110), and a substrate fixation (130) for pressing the edge of the substrate (10) onto the sealing (120). The carrier body (110) comprises one or more gas supply conduits (140) to provide a gas cushion between a back side (10B) of the substrate (10) and the curved substrate support surface (111). Further, an apparatus for depositing a layer on a substrate in a curved state and a method for supporting a substrate in a curved state in a vacuum deposition chamber are provided.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 14/54 - Controlling or regulating the coating process
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
25.
PHYSICALLY-INFORMED MULTI-SYSTEM HARDWARE OPERATING WINDOWS
Embodiments disclosed herein include a method for use with a semiconductor processing tool. In an embodiment, the method comprises configuring the semiconductor processing tool, running a benchmark test on the semiconductor processing tool, providing hardware operating window (HOW) analytics, generating a design of experiment (DoE) using the HOW analytics, implementing process optimization, and releasing an iteration of the process recipe. In an embodiment, the method further comprises margin testing the iteration of the process recipe.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
A substrate processing system is provided having a processing chamber. The processing chamber includes a lid plate, one or more chamber sidewalls, and a chamber base that collectively define a processing volume. An annular plate is coupled to the lid plate, and an edge manifold is fluidly coupled to the processing chamber through the annular plate and the lid plate. The substrate processing system includes a center manifold that is coupled to the lid plate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
27.
REGENERATION ANNEAL OF METAL OXIDE THIN-FILM TRANSISTORS
A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150 °C to about 275 °C.
A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.
The present disclosure relates to thin-form-factor semiconductor device packages, and methods and systems for forming the same. Embodiments of the disclosure include methods and apparatus for forming semiconductor device packages that include frames that are coated with a layer of a coupling agent on which subsequently layers are formed. The utilization of the coupling agent between the frame and subsequently formed layers enhances the thermo-mechanical reliability of the package frames by mitigating the stress induced by any subsequently formed insulation layers and/or RDLs, and by providing improved coupling between such layers and the relatively smooth surfaces of the frames.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
30.
METHODS FOR PATTERNING SUBSTRATES TO ADJUST VOLTAGE PROPERTIES
A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.
Embodiments of the disclosure include an apparatus and method of forming a memory device with high-mobility oxide semiconductor channels. In some embodiments, the apparatus, for example, includes a plurality of alternating layers formed over a surface of a substrate; a gate coupled to each of the word line layers of the plurality of alternating layers; a multi-layer channel memory cell having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region, the multi-layer channel also having a first conductive layer and a second conductive layer, the first conductive layer being different from the second conductive layer; and an ONO layer stack disposed between the gates and the multi-layer channel, wherein the ONO layer stack extends in the first direction between the source region and the drain region.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates that have property values that meet threshold values. The method further includes determining, based on the trace data, a dynamic acceptable area outside of guardband limits. The method further includes causing, based on the dynamic acceptable area outside of the guardband limits, performance of a corrective action associated with the substrate processing system.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G05B 19/404 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes determining, based on a guardband, guardband violation data points of the plurality of data points of the trace data. The method further includes determining, based on the guardband violation data points, guardband violation shape characterization. Classification of additional guardband violation data points of additional trace data is to be based on the guardband violation shape characterization. Performance of a corrective action associated with the substrate processing system is based on the classification.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
pe1 122 2211; and detecting signal electrons emitted upon impingement of the electron beam for testing at least a first device-to-device electrical interconnect path of the packaging substrate.
G01R 31/305 - Contactless testing using electron beams
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
36.
INTEGRATED METHOD AND TOOL FOR HIGH QUALITY SELECTIVE SILICON NITRIDE DEPOSITION
Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/32 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers using masks
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method of forming a structure on a substrate includes forming a tungsten nucleation layer within at least one opening within a multi-tier portion of a substrate. The method includes exposing the nucleation layer a nitrogen trifluoride-containing gas to inhibit growth of the nucleation layer at narrow portions within the at least one opening. The method includes exposing the at least one opening to the tungsten containing precursor gas to form a fill layer over the nucleation layer within the at least one opening. The method includes exposing the at least one opening of the substrate to the nitrogen trifluoride-containing gas or a nitrogen-containing plasma to inhibit growth of portions of the fill layer along the at least one opening.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
38.
HYBRID ION SOURCE FOR ALUMINUM ION GENERATION USING A TARGET HOLDER AND ORGANOALUMINIUM COMPOUNDS
An ion source that is capable of different modes of operation is disclosed. The ion source includes an insertable target holder includes a hollow interior into which the solid dopant material is disposed. The target holder may a porous surface at a first end, through which vapors from the solid dopant material may enter the arc chamber. The porous surface inhibits the passage of liquid or molten dopant material into the arc chamber. The target holder is also constructed such that it may be refilled with dopant material when the dopant material within the hollow interior has been consumed. The ion source may have several gas inlets. When the insertable target holder is used, the ion source may supply a first gas, such as a halogen containing gas. When operating in a second mode, the ion source may utilize an organoaluminium gas.
An ion source that is capable of different modes of operation is disclosed. A solid target may be disposed in the arc chamber. The ion source may have several gas inlets, in communication with different gasses. When operating in a first mode, the ion source may supply a first gas, such as a halogen containing gas. When operating in a second mode, the ion source may supply an organoaluminium gas. Ions having single charges may be created in the first mode, while ions having multiple charges may be created in the second mode. In some embodiments, the solid target may be retractable.
Embodiments of the disclosure include a polishing pad for planarizing a surface of a substrate during a polishing process. The polishing pad includes a base layer, comprising a first material composition, and a polishing layer disposed over the base layer. The polishing layer includes a second material composition that is exposed at a polishing surface of the polishing pad, wherein the polishing surface is configured to contact the surface of the substrate during the polishing process. The second material composition includes a polishing layer material having a hardness that is greater than 50 on a Shore D scale, a yield point strength, a yield point strength strain, a break point strength, and an elongation at break point strain, wherein a magnitude of a difference between the elongation at break point strain and the yield point strength strain is greater than the magnitude of yield point strength strain when measured at room temperature.
B24B 37/22 - Lapping pads for working plane surfaces characterised by a multi-layered structure
B24B 37/24 - Lapping pads for working plane surfaces characterised by the composition or properties of the pad materials
B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
41.
DOSE MAPPING USING SUBSTRATE CURVATURE TO COMPENSATE FOR OUT-OF-PLANE DISTORTION
A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of a surface of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source; and applying the dose map to process the substrate using the patterning energy source.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
42.
DOSE MAPPING AND SUBSTRATE ROTATION FOR SUBSTRATE CURVATURE CONTROL WITH IMPROVED RESOLUTION
A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source. The method may include applying the dose map to process the substrate using the patterning energy source, wherein the dose map is applied by performing a plurality of exposures of the substrate to the patterning energy source, at a plurality of different twist angles.
H01J 37/302 - Controlling tubes by external information, e.g. programme control
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
43.
HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHOD
Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a plurality of channels for delivering one or more radical beams to a workpiece, wherein each of the plurality of channels has a lengthwise axis oriented at a non-zero angle relative to a perpendicular extending from a main surface of the workpiece, wherein each channel of the plurality of channels has a channel length and a channel width, and wherein the channel width varies along the channel length.
H01J 37/305 - Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating, or etching
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
45.
METHODS AND APPARATUSES FOR IDENTIFYING DEFECTIVE ELECTRICAL CONNECTIONS OF A SUBSTRATE
A method of identifying defective electrical connections of a substrate (10) is provided, the substrate having a first surface contact (21) and a first electrical connection (20) extending from the first surface contact through the substrate. The method includes placing the substrate on a stage in a vacuum chamber (101); charging the first surface contact (21) by directing an electron beam (111) on the first surface contact and detecting secondary electrons (113) emitted from the first surface contact (21) during the charging for determining a secondary electron signal (114) over time; and determining a state information about the first electrical connection (20) depending on an occurrence of a drop or decline in the secondary electron signal (114). Further described is an apparatus (100) for identifying defective electrical connections of a substrate according to the methods described herein.
G01R 31/305 - Contactless testing using electron beams
G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
46.
SYSTEM AND METHOD FOR DISSIPATING WORKPIECE CHARGE BUILD UP
A system and method for reducing charge on a workpiece disposed on a platen is disclosed. The system includes an ionizer to generate ionized gas from the source of backside gas. The ionizer may be used to introduce ionized gas into the backside gas channels of the platen. A controller is used to selectively allow backside gas and/or ionized gas into the backside gas channels. In certain embodiments, the platen also includes an exhaust channel in communication with an exhaust valve to ensure that the pressure within the volume between the top surface of the platen and the workpiece is maintained in a desired range. In one embodiment, the system includes a valving system in communication with the source of backside gas and also in communication with the ionizer. In another embodiment, the amount of ionization performed by the ionizer is programmable.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
An ion source that is capable of different modes of operation is disclosed. The ion source includes an insertable target holder includes a hollow interior into which the solid dopant material is disposed. The target holder may a porous surface at a first end, through which vapors from the solid dopant material may enter the arc chamber. The porous surface inhibits the passage of liquid or molten dopant material into the arc chamber. The target holder is also constructed such that it may be refilled with dopant material when the dopant material within the hollow interior has been consumed. A solid target is also disposed in the arc chamber. When the insertable target holder is used, multicharged ions are created. When the insertable target holder is retracted, single charged ions are created by only etching the solid dopant-containing compound.
Transition metal dichalcogenide films and methods for depositing transition metal dichalcogenide films on a substrate are described. Methods for converting transition metal oxide films to transition metal dichalcogenide films are also described. The substrate is exposed to a metal precursor and an oxidant to form a transition metal oxide film; the transition metal oxide film is exposed to a chalcogenide precursor to form the transition metal dichalcogenide film.
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
49.
SYSTEMS AND METHODS TO REDUCE FLOW ACCURACY ERROR FOR LIQUID & GAS MASS FLOW CONTROLLER DEVICES
Exemplary fluid delivery assemblies for a semiconductor processing system may include a liquid delivery source. The assemblies may include a heater that is fluidly coupled with an outlet of the liquid delivery source. The assemblies may include a liquid flow controller that is fluidly coupled with the liquid delivery source downstream of the heater. The assemblies may include a liquid vaporizer fluidly coupled with a downstream end of the liquid flow controller. The assemblies may include a chamber delivery line coupled with an output of the liquid vaporizer.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
50.
RECOMBINATION CHANNELS FOR ANGLE CONTROL OF NEUTRAL REACTIVE SPECIES
Provided herein are approaches for angle control of neutral reactive species ion beams. In one approach, a workpiece processing apparatus may include a plasma source operable to generate a plasma within a plasma chamber enclosed by a chamber housing, and an extraction plate coupled to the chamber housing. The extraction plate may include a recombination array having a plurality of channels operable to direct one or more radical beams to a workpiece at a non-zero angle relative to a perpendicular extending from a main surface of the workpiece.
H01J 37/305 - Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating, or etching
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
51.
APPARATUS AND METHODS TO PROMOTE WAFER EDGE TEMPERATURE UNIFORMITY
A shadow ring for a processing chamber, such as a semiconductor processing chamber, is an annular member including a body with a radially inwardly projecting lip. The shadow ring includes a feature that mitigates heat transfer between the lip and the rest of the body. In one example, the feature includes a plurality of apertures, each aperture extending from an upper opening at an upper surface of the shadow ring to a corresponding lower opening at a lower surface of the shadow ring. A neck between adjacent apertures creates a bottleneck that hinders conductive heat transfer.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
52.
CONTROL AND PREDICTION OF MULTIPLE PLASMA COUPLING SURFACES AND CORRESPONDING POWER TRANSFER
Embodiments disclosed herein include a process power controller for a plasma processing tool. In an embodiment, the process power controller includes a process power source optimizer, a source predictor, and a process uniformity controller. In an embodiment, the source predictor is communicatively coupled to the process power source optimizer and the process uniformity controller.
Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool. In an embodiment, the method comprises measuring a voltage and a current of a transmission line, converting an analog voltage signal and an analog current signal into a digital voltage signal and a digital current signal, calculating a u-vector from the digital voltage signal and the digital current signal, calculating a Cl position of a first capacitor with real components of the u-vector, and calculating a C2 position of a second capacitor with imaginary components of the u-vector.
Multilayered semiconductor particles, which may be referred to as a quantum dots, may include a zinc-containing core. The particles may include a zinc-and-selenium-containing inner shell on the zinc-containing core. The particles may include a zinc-containing outer shell on the zinc-and-selenium-containing inner shell. The particles may include a phosphorous-containing material in contact with the zinc-containing outer shell. The phosphorous-containing material may be or include triisopropyl phosphite (TIPP), bis(2,4-di-tert-butylphenyl) pentaerythritol diphosphate (B PEDP), tris(2, 4-di-tert-butylphenyl)phosphite (TDTBPP), triethylphosphite, tris(2-ethylhexylphosphite), tris(trimethylsilyl)phosphite, triphenylphosphite, triphenyl phosphine, tris(4-methoxyphenyl)phosphine, tris(1-pyrrolidinyl)phosphine, tri(2-furyl)phosphine, or tris(dimethylamino)phosphine.
Embodiments of the present disclosure relate to methods, systems, and apparatus for inkjet printing self-assembled monolayer (SAM) structures on substrates. In one embodiment, which can be combined with other embodiments, one or more SAM layers are printed on a substrate surface of a substrate in a localized manner such that a portion of the substrate surface is left exposed to a processing region of the inkjet chamber. The printing includes spraying one or more subsections of the substrate surface with an ink, the ink having a SAM composition. The SAM composition includes an active component, and a hydrophobic tail.
B41M 5/00 - Duplicating or marking methods; Sheet materials for use therein
B41M 7/00 - After-treatment of printed works, e.g. heating, irradiating
B41J 3/407 - Typewriters or selective printing or marking mechanisms characterised by the purpose for which they are constructed for marking on special material
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and a carbon-containing precursor to a processing region of a semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor, the carbon-containing precursor, and the oxygen-containing precursor at a temperature less than or about 700 °C. The methods may include forming a silicon-and-carbon-containing layer on the substrate.
Methods for providing an inorganic oxide coating to high aspect ratio particles containing an active pharmaceutical ingredient are described as are compositions containing such coated particles.
44) and a diluent towards the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first time period. Then, a source power is applied to achieve a source state for a second time period, and then no bias power and no source power is applied to achieve a recovery state for a third time period. The plasma etch pulse is repeated until a target amount of the sample is etched.
An electronic device manufacturing system capable of obtaining metrology data associated with a deposition process performed on a substrate according to a process recipe, wherein the deposition process generates a plurality of layers on a surface of the substrate. The manufacturing system can further obtain an expected profile associate with the process recipe, wherein the expected profile comprises a plurality of values indicative of a desired thickness for a plurality of layers of the process recipe. The manufacturing system can further generate a correction profile based on the metrology data and the expected profile, wherein the correction profile comprises a deposition time offset value for at least one layer of the plurality of layers. The manufacturing system can further generate an updated process recipe by applying the correction profile to the process recipe and cause a deposition step to be performed on the substrate according to the updated process recipe.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/52 - Controlling or regulating the coating process
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first end having a first surface that faces the carrier body and a second end having a second surface opposite the first surface. The second end of the inner ring may be radially displaceable. The carrier heads may include an outer ring having an inner surface that is disposed against an outer surface of the inner ring.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
61.
POLISHING HEAD WITH LOCAL INNER RING DOWNFORCE CONTROL
Exemplary carrier heads for a chemical mechanical polishing apparatus may include a carrier body. The carrier heads may include a substrate mounting surface coupled with the carrier body. The carrier heads may include an inner ring that is sized and shaped to circumferentially surround a peripheral edge of a substrate positioned against the substrate mounting surface. The inner ring may be characterized by a first surface that faces the carrier body and a second surface opposite the first surface. The carrier heads may include at least one downforce control actuator disposed above the first surface of the inner ring at a discrete position about a circumference of the inner ring.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Exemplary semiconductor substrate carrier frames may include a frame body defining a central aperture. The frames may include a plurality of fingers that are coupled with the frame body. Each of the plurality of fingers may extend into the central aperture. Each of the plurality of fingers may include a substrate receiving interface. At least one of the plurality of fingers may include an actuator that manipulates a respective one of the at least one of the plurality of fingers between a substrate holding position and an open position.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
63.
AUTONOMOUS FREQUENCY RETRIEVAL FROM PLASMA POWER SOURCES
Embodiments disclosed herein include a processing tool. In an embodiment the processing tool comprises a transmission line sensor, and an analog to digital (A/D) converter. In an embodiment, the processing tool may further comprise a digital down converter (DDC), and a frequency digital phase lock loop (dPLL). In an embodiment, the processing tool may further comprise a transmission line scaling module.
Embodiments disclosed herein include a sensor. In an embodiment, the sensor comprises a board, wherein an aperture is formed through the board, a current loop winding through the board around the aperture, and a voltage ring around the aperture and within an inner perimeter of the current loop, wherein the voltage ring comprises an interior ring, an insulator ring around the interior ring, and an exterior ring around the insulator ring.
G01R 15/18 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
Embodiments disclosed herein include a processing tool. In an embodiment, the processing tool comprises a power supply, an impedance matching network coupled to the power supply, a cathode, wherein the power supply is configured to supply power through the impedance matching network to the cathode, and a processing module, wherein the processing module is communicatively coupled to the power supply and the impedance matching network.
Exemplary methods of semiconductor processing may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include forming a plasma of the carbon-containing precursor within the processing region. The methods may include depositing a carbon-containing material on the substrate. The carbon-containing material may extend within the one or more features along the substrate. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include treating the carbon-containing material with plasma effluents of the hydrogen-containing precursor. The plasma effluents of the hydrogen-containing precursor may cause a portion of the carbon-containing material to be removed from the substrate.
Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
68.
OZONE-BASED LOW TEMPERATURE SILICON OXIDE COATING FOR PHARMACEUTICAL APPLICATIONS
This disclosure pertains to coated drug compositions and methods of preparing coated drug compositions with a low temperature o-zone based silicon oxide coating. Specifically, the instant application discloses a method to coat active pharmaceutical ingredient particles using a silicon precursor and ozone at a low temperature.
Embodiments described herein generally relate to sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes substrate, pixel-defining layer (PDL) structures disposed over the section of the substrate, inorganic or metal overhang structures disposed on an upper surface of the PDL structures, and a plurality of sub-pixels. The PDL structures include a trench disposed in the top surface of the PDL structure. Each sub-pixel includes an anode, an OLED material disposed over and in contact with the anode, and a cathode disposed over the OLED material. The inorganic or metal overhang structures have an overhang extension that extends laterally over the trench. An encapsulation layer is disposed over the cathode and extends under at least a portion of the inorganic or metal overhang structures and along a top surface of the PDL structures.
Embodiments described herein provide for a defect detection system and method suitable for detecting defects on an edge of a wafer. The method includes placing at least two wafers sequentially on a conveyor. Images of at least the edges of each wafer placed on the conveyor are captured and sent to a controller. A defect detection software combines the images to show the edges of the wafers in a virtual stack. The virtual stack allows for a pattern of defects to be identified. The pattern of defects in close proximity will allow for identification of the defects in the edges of the wafers.
Embodiments disclosed herein include a lamp module for a semiconductor processing chamber. In an embodiment, the lamp module plate comprises a back plate, a first ring that extends from the back plate, a second ring that extends from the back plate, and a third ring that extends from the back plate. In an embodiment, the lamp module further comprises a first plurality of lamps between the first ring and the second ring, a second plurality of lamps between the second ring and the third ring, and a third plurality of lamps configured to emit infrared radiation that propagates into the third ring.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
72.
GRADIENT OXIDATION AND ETCH OF PVD MOLYBDENUM FOR BOTTOM UP GAP FILL
A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on exposed top surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in the top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes the oxidized portion of the seed layer. A second etch process removes portions of the seed layer. A metal gap fill process fills or partially fills the features with a gap fill material.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method of forming a tungsten-containing layer over a substrate includes a) positioning a substrate on a substrate support in a process volume of a process chamber; b) providing a precursor gas to the process volume of the process chamber for a first duration; and c) providing a tungsten-containing gas to the process volume of the process chamber by opening a pulsing valve on a tungsten-containing gas delivery line for a second duration occurring after the first duration to form a tungsten-containing layer on the substrate. The tungsten-containing gas delivery line includes a first section connected to an inlet of the pulsing valve and a second section connected to an outlet of the pulsing valve, the first section connects the inlet of the pulsing valve to a reservoir of tungsten-containing gas, the second section connects the outlet of the pulsing valve to an inlet of the process chamber.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/08 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metal halides
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/448 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for generating reactive gas streams, e.g. by evaporation or sublimation of precursor materials
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
74.
RUN-TO-RUN CONTROL AT A MANUFACTURING SYSTEM USING MACHINE LEARNING
First data associated with a first process performed for a first layer of a substrate is identified. The first layer is to be further processed according to a second process. The first data is provided as input to a machine learning model that is trained to predict metrology measurement values for layers of substrates at the manufacturing system. An amount of drift of a first set of metrology measurement values for the first layer following completion of the first process and/or the second process from target values is determined. Modifications to a recipe for the second process is determined in view of the determined amount of drift and second data associated with a second substrate layer that was previously processed at the manufacturing system. The second process is updated based on the determined one or more modifications.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method for testing a packaging substrate with at least one electron beam column is described, wherein the packaging substrate is a panel level packaging substrate or an advanced packaging substrate. The method includes placing the packaging substrate on a stage in a vacuum chamber; directing at least one electron beam of the at least one electron beam column on at least a first portion of the packaging substrate; directing the at least one electron beam of the at least one electron beam column on at least a second portion of the packaging substrate; detecting signal electrons emitted upon impingement of the at least one electron beam for testing a first device-to-device electrical interconnect path of the packaging substrate; and illuminating at least a third portion of the packing substrate with UV radiation.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01R 31/307 - Contactless testing using electron beams of integrated circuits
H01J 37/00 - Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
A heating module for a substrate processing chamber includes heating lamps coupled to a reflector plate and a heat exchanger. The heat exchanger cools a gas within the heating module. A fan within the heating module circulates the gas through apertures in the reflector plate to cool the heating bulbs. The gas is cooled by the heat exchanger, and is recirculated. One or more shrouds directs the gas as the gas is being circulated.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C30B 25/10 - Heating of the reaction chamber or the substrate
77.
GRADIENT OXIDATION AND ETCH FOR PVD METAL AS BOTTOM LINER IN BOTTOM UP GAP FILL
A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.
C23C 16/50 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges
C23C 16/52 - Controlling or regulating the coating process
Bayesian inference and modeling techniques, along with model decomposition may be used to improve mismatch performances in semiconductor processing devices by identifying sources of intrinsic and extrinsic variations in performance. A network of causal relationships between processes and hardware in a semiconductor processing device may be accessed to generate a first Bayesian model for a first semiconductor processing device using the causal relationships in the network and performance data. A second Bayesian model may also be generated for a second semiconductor processing device using the causal relationships in the network and associated performance data. Response distributions generated by the first Bayesian model and the second Bayesian model may be compared to determine whether a performance of the first semiconductor processing device matches a performance of the second semiconductor processing device by decomposing the model transfer functions to identify the effects of intrinsic/extrinsic variables.
G06F 18/2415 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on parametric or probabilistic models, e.g. based on likelihood ratio or false acceptance rate versus a false rejection rate
G06F 18/2132 - Feature extraction, e.g. by transforming the feature space; Summarisation; Mappings, e.g. subspace methods based on discrimination criteria, e.g. discriminant analysis
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
79.
DISPLACEMENT MEASUREMENTS IN SEMICONDUCTOR WAFER PROCESSING
Wafers that begin as flat surfaces during a semiconductor manufacturing process may become warped or bowed as layers and features are added to an underlying substrate. This warpage may be detected between manufacturing processes by rotating the wafer adjacent to a displacement sensor. The displacement sensor may generate displacement data relative to a baseline measurement to identify areas of the wafer that bow up or down. The displacement data may then be mapped to locations on the wafer relative to an alignment feature. This mapping may then be used to adjust parameters in subsequent semiconductor processes, including adjusting how a carrier head on a polishing process holds or applies pressure to the wafer as it is polished. A model may be trained to provide control signals for a polishing/cleaning process, or to generate metrology data.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01S 17/08 - Systems determining position data of a target for measuring distance only
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/66 - Testing or measuring during manufacture or treatment
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
81.
REDUCED CHARGING BY LOW NEGATIVE VOLTAGE IN FIB SYSTEMS
A method of processing a region of a sample, the method comprising: positioning a sample within a vacuum chamber; generating an ion beam with a focused ion beam (FIB) column; focusing the ion beam on the sample and scanning the focused ion beam across the region of the sample thereby generating secondary electrons that are ejected from a surface of the sample within the region; and during the scanning, applying a negative bias voltage to an electrically conductive structure proximate the region to alter a trajectory of the secondary electrons and repel the secondary electrons back to the sample surface, wherein the electrically conductive structure is one of a gas injection nozzle, a voltage pin or a nano-manipulator.
Methods of selectively depositing a carbon-containing layer are described. Exemplary processing methods may include flowing a first precursor over a substrate comprising a metal surface and a non-metal surface to form a first portion of an initial carbon-containing film on the metal surface. The methods may include removing a first precursor effluent from the substrate. A second precursor may then be flowed over the substrate to react with the first portion of the initial carbon-containing layer. The methods may include removing a second precursor effluent from the substrate. The methods may include pre-treating the metal surface of the substrate to form a metal oxide surface on the metal surface.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
83.
REMOTE SURFACE WAVE PROPAGATION FOR SEMICONDUCTOR CHAMBERS
Apparatus provide plasma to a processing volume of a chamber. The Apparatus may comprise a plurality of plasma sources, each with at least a dielectric tube inlet which is at least partially surrounded by a conductive tube which is configured to be connected to RF power to generate plasma and a gas inlet positioned opposite the dielectric tube inlet for a process gas and a dielectric tube directly connected to each of the plurality of plasma sources where the dielectric tube is configured to at least partially contain plasma generated by the plurality of plasma sources and to release radicals generated in the plasma via holes in the dielectric tube.
Micro-LED structures include an LED epilayer that may be formed before the micro-LED structure is coupled to a backplane substrate. In order to prevent light leakage and maximize light output, the sidewalls and other surfaces of the LED epilayer may be coated with a reflective coating. For example, the reflective coating may include a metal layer that is electrically insulated between dielectric layers from the micro-LED electrodes. The reflective coating may also be formed using multiple layers in a distributed Bragg reflector configuration. This reflective coating may be formed during the LED fabrication process before the micro-LED structure is coupled to the backplane. The pixel isolation structures on the backplane may also include a reflective coating that is applied above the LED epilayers.
H01L 33/22 - Roughened surfaces, e.g. at the interface between epitaxial layers
H01L 33/46 - Reflective coating, e.g. dielectric Bragg reflector
H01L 33/32 - Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
H01L 33/48 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor body packages
H01L 33/36 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the electrodes
H01L 27/15 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier, specially adapted for light emission
85.
METHOD FOR ROUGHNESS REDUCTION IN MANUFACTURING OPTICAL DEVICE STRUCTURES
Embodiments described herein relate to a method of using an apparatus for forming waveguides. The method includes positioning a substrate at a first rotation angle, exposing the substrate to an ion beam, forming first partial trenches defined by adjacent angled device structures with the first device angle, rotating the substrate to a second rotation angle, exposing the substrate to the ion beam, etching the first partial trenches, and repeating the method from about 1 cycle to about 100 cycles to form a plurality of trenches defined by adjacent angled device structures. The first rotation angle is selected to form one or more angled device structures with a first device angle relative to a vector parallel to the substrate. The ion beam is configured to contact the substrate at a beam angle 0 relative to a surface normal of the substrate.
A method of reducing surface defects of a piezoelectric film layer includes depositing a first seed layer on a substrate, depositing an intermediate film layer on the first seed layer at a first temperature of approximately 350 degrees Celsius to approximately 700 degrees Celsius, depositing a second seed layer on the intermediate film layer, and depositing a piezoelectric film layer at a second temperature of less than 200 degrees Celsius. The piezoelectric film layer has a surface cone defect count of less than or equal to 2 per 100microns 2 of surface area of the piezoelectric film layer. In some embodiments, no vacuum breaks occur between depositions of the first seed layer, the intermediate film layer, the second seed layer, and the piezoelectric film layer.
H01L 41/083 - Piezo-electric or electrostrictive elements having a stacked or multilayer structure
H01L 41/27 - Manufacturing multilayered piezo-electric or electrostrictive devices or parts thereof, e.g. by stacking piezo-electric bodies and electrodes
Methods and apparatus for processing a substrate are provided herein. For example, a matching network configured for use with a plasma processing chamber comprises an input configured to receive one or more radio frequency (RF) signals, an output configured to deliver the one or more RF signals to a processing chamber, a first sensor operably connected to the input and a second sensor operably connected to the output and configured to measure impedance during operation, at least one variable capacitor connected to the first sensor and the second sensor and a controller, based on a measured impedance, configured to tune the at least one variable capacitor of the matching network to a first target position based on weighted output impedance values measured at pulse states of a voltage waveform and to tune the at least one variable capacitor to a second target position based on weighted input impedance values measured at the pulse states of the voltage waveform.
Embodiments disclosed herein include a method of developing a reduced order model (ROM) for a model based controller. In an embodiment, the method comprises obtaining a design of a plant, and building a detailed model of the thermal network of the plant from the design of the plant. In an embodiment, the method further comprises obtaining a training input recipe, and running the detailed model using the training input recipe. In an embodiment, the method further comprises generating a plurality of snapshots, wherein each snapshot includes the temperatures of a plurality of components in the detailed model, and utilizing a dynamic mode decomposition with control (DMDc) operation in order to extract the ROM from the plurality of snapshots.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Exemplary device structures may include a light emitting diode structure. The light emitting diode structure may be operable to generate light. The structures may include a photoluminescent region containing a photoluminescent material. The photoluminescent region may be positioned on the light emitting diode structure. The structures may include an ultraviolet (UV) light filter positioned above the photoluminescent region. The UV light filter may be operable to absorb light generated by the light emitting diode structure characterized by an emission wavelength of less than or about 430 nm.
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 33/12 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Embodiments of the disclosure relate to digital lithography system and related methods, the system including at least one light source configured to emit a light beam onto a substrate via a lens, at least one image sensor, configured to detect a reflected light beam from the substrate via the lens, at least one motor configured to move the lens to focus the light beam onto the substrate, and a controller in communication with the at least one light source, the at least one image sensor and the at least one motor, wherein the controller is to actuate the at least one motor to move the lens in response to at least one signal from the at least one image sensor.
A system for degassing substrates provides reduced infrared sources in a degas chamber. In some embodiments, the system includes a degas chamber with a microwave source and an infrared temperature sensor positioned in a bottom of the degas chamber, at least one hoop with an annular shape that is configured to support or lift a substrate and is formed from at least one first material that is opaque to microwaves and has an emissivity of 0.1 or less, and at least one actuator with a movable vertical shaft. Each of the at least one actuator is attached under one of the hoops at an outer perimeter of the hoop. The portion of the movable vertical shaft that is exposed to microwaves from the microwave source in the degas chamber is formed from at least one second material that is opaque to microwaves and has an emissivity of 0.1 or less.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
92.
HIGH POWER TUNGSTEN HALOGEN LAMP LIFETIME IMPROVEMENT THROUGH J-HOOK DESIGN
A lamp and epitaxial processing apparatus are described herein, In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.
H01K 1/18 - Mountings or supports for the incandescent body
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C30B 25/10 - Heating of the reaction chamber or the substrate
93.
SELF FIELD-SUPPRESSION CVD TUNGSTEN (W) FILL ON PVD W LINER
Embodiments of methods and associated apparatus for filling a feature in a substrate are provided herein. In some embodiments, a method of depositing tungsten in features of a substrate includes: depositing a seed layer consisting essentially of tungsten in the features via a physical vapor deposition (PVD) process; and depositing a bulk layer consisting essentially of tungsten in the features via a chemical vapor deposition (CVD) process to fill the features such that the deposition of the bulk layer is selective to within the features as compared to a field region of the substrate, wherein the CVD process is performed by flowing hydrogen gas (H2) at a first flow rate and a tungsten precursor at a second flow rate, and wherein the first flow rate is less than the second flow rate.
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/14 - Deposition of only one other metal element
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/52 - Controlling or regulating the coating process
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/54 - Apparatus specially adapted for continuous coating
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A method of forming patterned features on a substrate is provided. The method includes: positioning a first mask over a first portion of a substrate; directing radiation through the patterned area of the first mask at the first portion of the substrate to form a first patterned region on the substrate; positioning a second mask over a second portion of the substrate, the second mask including a first patterned area and a second patterned area, the first patterned area spaced apart from the second patterned area by an unpatterned area; directing radiation through the first patterned area of the second mask at a first part of the second portion of the substrate to form a second patterned region on the substrate; and directing radiation through the second patterned area of the second mask at a second part of the second portion of the substrate to form a third patterned region.
A method of processing a substrate is provided including flowing a deposition gas comprising a hydrocarbon compound and a dopant compound into a process volume having a substrate disposed positioned on a substrate support. The process volume is maintained at a pressure of about 0.5 mTorr to about 10 mTorr. The method includes generating a plasma at the substrate by applying a first RF bias to the substrate support to deposit a doped diamond-like carbon film on the substrate. The doped diamond-iike carbon film includes about 5 at.% to about 25 at.% of dopant and a first stress property. The method includes annealing the doped diamond-like carbon film at about 220 °C to about 450 °C to form an annealed film. The annealed film includes a second stress property. The second stress property having an absolute value less than or within 10% the first stress property.
Embodiments of the present disclosure generally relate to optical devices having barrier layers for reduced hardmask diffusion and/or hardmask residue, and related methods of forming the optical devices. In one or more embodiments, a plurality of optical device structures each include a barrier layer disposed between a device function layer and a hardmask layer prior to removal of the hardmask layer.
G02B 6/00 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/14 - Deposition of only one other metal element
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
97.
HIGH POWER TUNGSTEN HALOGEN LAMP LIFETIME IMPROVEMENT THROUGH J-HOOK DESIGN
A lamp and epitaxial processing apparatus are described herein, In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01K 1/24 - Mounts for lamps with connections at opposite ends, e.g. for tubular lamp
C30B 25/10 - Heating of the reaction chamber or the substrate
Methods and apparatus for substrate processing are described. In some embodiments a showerhead assembly includes a heated showerhead having a heater and a gas diffusion plate coupled to the heater, the gas diffusion plate having a plurality of channels extending through the gas diffusion plate; an ion filter spaced from the heated showerhead, the ion filter having a first side facing the heated showerhead and a second side opposite the first side, the ion filter having a plurality of channels extending through the ion filter; a heat transfer ring in contact between the heated showerhead and the ion filter, the heat transfer ring being thermally conductive and electrically insulative, the heat transfer ring comprised of a plurality of elements spaced from one another along an interface between the heated showerhead and the ion filter; and a remote plasma region defined between the heated showerhead and the ion filter.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.
G02B 6/00 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
C23C 16/04 - Coating on selected surface areas, e.g. using masks
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
100.
METHODS AND APPARATUSES FOR ELECTRON BEAM TESTING ELECTRICAL CONNECTIONS OF A SUBSTRATE
A method for testing electrical connections of a substrate is described, the substrate having a first surface contact (21) and a first electrical connection (20) extending from the first surface contact (21). The method includes: (a) discharging the first surface contact (21) by focusing and deflecting a first electron beam (111) having a first electron energy on the first surface contact (21); (b) charging the first surface contact (21) by focusing and deflecting a second electron beam (112) having a second electron energy different from the first electron energy on the first surface contact (21); and (c) inspecting the first electrical connection (20) by detecting signal electrons emitted from the substrate. Further described are apparatuses for testing electrical connections of a substrate using two electron beams of different electron energies in accordance with the methods described herein.
patents
