40 - Treatment of materials; recycling, air and water treatment,
Goods & Services
Treatment of materials, namely, mechanical, chemical and
physical treatment of semiconductor materials substrates and
silicon wafers for the manufacture of integrated chips.
09 - Scientific and electric apparatus and instruments
Goods & Services
Software-controlled systems used in the semiconductor
manufacturing industry, namely, recorded software for
automating and controlling machines that manufacture
semiconductors and computer memory hardware containing the
foregoing recorded software; computer software for use with
semiconductor wafer processing equipment.
Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.
A method of polishing includes bringing a substrate into contact with a polishing pad and generating relative motion between the substrate and the polishing pad, retaining the substrate on the polishing pad with a retainer, and during polishing of the substrate alternating between reducing a diameter of an inner surface of the retainer to clamp the substrate and increasing the diameter of the inner surface of the retainer to release the substrate from clamping while continuing to retain the substrate.
Embodiments of the present disclosure generally relate to apparatus and methods for reducing substrate backside damage during semiconductor device processing. In one implementation, a method of chucking a substrate in a substrate process chamber includes exposing the substrate to a plasma preheat treatment prior to applying a chucking voltage to a substrate support. In one implementation, a substrate support is provided and includes a body having an electrode and thermal control device disposed therein. A plurality of substrate supporting features are formed on an upper surface of the body, each of the substrate supporting features having a substrate supporting surface and a rounded edge.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/26 - Bombardment with wave or particle radiation
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
12.
GROUNDING TECHNIQUES FOR ESD POLYMERIC FLUID LINES
A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 53/017 - Devices or means for dressing, cleaning or otherwise conditioning lapping tools
F16L 11/127 - Hoses, i.e. flexible pipes made of rubber or flexible plastics with arrangements for particular purposes, e.g. specially profiled, with protecting layer, heated, electrically conducting electrically conducting
13.
FLUID-TIGHT ELECTRICAL CONNECTION TECHNIQUES FOR SEMICONDUCTOR PROCESSING
A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Embodiments of the disclosure relate to methods for forming silicon based gapfill within substrate features. A flowable silicon film is formed within the feature with a greater thickness on the bottom and top surfaces than the sidewall surface. An etch plasma removes the silicon film from the sidewall surface. A conversion plasma is used to convert the silicon film to a silicon based gapfill (e.g., silicon oxide). In some embodiments, the silicon film is preferentially converted on the top and bottom surface before being etched from the sidewall surface.
A method of reducing gallium particle formation in an ion implanter. The method may include performing a gallium implant process in the ion implanter, the gallium implant process comprising implanting a first dose of gallium ions from a gallium ion beam into a first set of substrates, while the first set of substrates are disposed in a process chamber of the beamline ion implanter. As such, a metallic gallium material may be deposited on one or more surfaces within a downstream portion of the ion implanter. The method may include performing a reactive gas bleed operation into at least one location of the downstream portion of the ion implanter, the reactive bleed operation comprising providing a reactive gas through a gas injection assembly, wherein the metallic gallium material is altered by reaction with the reactive gas.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
16.
SYSTEMS AND METHODS FOR OPTIMIZING FULL HORIZONTAL SCANNED BEAM DISTANCE
Provided herein are approaches for optimizing a full horizontal scanned beam distance of an accelerator beam. In one approach, a method may include positioning a first Faraday cup along a first side of an intended beam-scan area, positioning a second Faraday cup along a second side of the intended beam-scan area, scanning an ion beam along the first and second sides of the intended beam-scan area, measuring a first beam current of the ion beam at the first Faraday cup and measuring a second beam current of the ion beam at the second Faraday cup, and determining an optimal scan distance of the ion beam across the intended beam-scan area based on the first beam current and the second beam current.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
17.
EPI SELF-HEATING SENSOR TUBE AS IN-SITU GROWTH RATE SENSOR
A method and apparatus for determining a growth rate on a semiconductor substrate is described herein. The apparatus is an optical sensor, such as an optical growth rate sensor. The optical sensor is positioned in an exhaust of a deposition chamber. The optical sensor is self-heated using one or more internal heating elements, such as a resistive heating element. The internal heating elements are configured to heat a sensor coupon. A film is formed on the sensor coupon by exhaust gases flowed through the exhaust and is correlated to film growth on a substrate within a process volume of the deposition chamber.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C30B 25/14 - Feed and outlet means for the gases; Modifying the flow of the reactive gases
G01B 11/06 - Measuring arrangements characterised by the use of optical techniques for measuring length, width, or thickness for measuring thickness
18.
GROUNDING TECHNIQUES FOR ESD POLYMERIC FLUID LINES
A chemical mechanical polishing assembly includes a chemical mechanical polishing system, a fluid source, and a fluid delivery conduit to carry a fluid from the fluid source into the chemical mechanical polishing system. The polishing system has a platen to support a polishing pad, a carrier head to support a substrate and bring the substrate into contact with the polishing pad, and a motor to cause relative motion between platen and the carrier head. The fluid delivery conduit includes a conductive wire extending through an interior of the conduit to flow electrostatic discharge to a ground, and a wire extraction fitting covering and sealing a location where the conductive wire passes through a wall of the fluid delivery conduit.
B24B 57/02 - Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
B24B 47/12 - Drives or gearings for grinding machines or devices; Equipment therefor for rotating or reciprocating working-spindles carrying grinding wheels or workpieces by mechanical gearing or electric power
B24B 37/30 - Work carriers for single side lapping of plane surfaces
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
19.
CONTROLLING LIGHT SOURCE WAVELENGTHS FOR SELECTABLE PHASE SHIFTS BETWEEN PIXELS IN DIGITAL LITHOGRAPHY SYSTEMS
A digital lithography system may adjust a wavelength of the light source to compensate for tilt errors in micromirrors while maintaining a perpendicular direction for the reflected light. Adjacent pixels may have a phase shift that is determined by an optical path difference between their respective light beams. This phase shift may be preselected to be any value by generating a corresponding wavelength at the light source based on the optical path difference. To generate a specific wavelength corresponding to the desired phase shift, the light source may produce multiple light components that have wavelengths that bracket the wavelength of the selected phase shift. The intensities of these components may then be controlled individually to produce an effect that approximates the selected phase shift on the substrate.
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a semiconductor processing chamber, where a substrate may be positioned. The substrate may include a trench formed between two columns and molybdenum-containing metal regions in a plurality of recesses formed in at least one of the columns. At least two of the molybdenum-containing metal regions may be connected by a molybdenum-containing first liner formed on at least a portion of a sidewall of the trench. The methods may include forming a plasma of the oxygen-containing precursor. The methods may include contacting the molybdenum-containing first liner with plasma effluents of the oxygen-containing precursor, thereby forming an oxidized portion of molybdenum. The methods may include providing a halide precursor. The methods may include contacting oxidized portion of the molybdenum with plasma effluents of the halide precursor, thereby removing the oxidized portion of molybdenum from the sidewall of the trench.
H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Embodiments disclosed herein include a method for cleaning a bevel area of a substrate support disposed within a plasma processing chamber. In one example the method begins by placing a cover substrate on a substrate support disposed in an interior volume of a processing chamber. A cleaning gas is provided into the interior volume of the processing chamber. A plasma is struck in the interior volume of the processing chamber. A cleaning gas is provided through the substrate support to a bevel edge area defined between an outer diameter of the cover substrate and an edge ring disposed on the substrate support.
Embodiments of the present disclosure generally relate to methods of modifying and engineering the effective thickness of an optical device substrate. The methods provide for depositing a material that is index-matched to the substrate to alter a thickness distribution of the optical device. By adjusting the thickness distribution, the optical path of light is modulated to direct the light to the output coupling grating.
Exemplary methods of OLED device processing are described. The methods may include forming an anode on a substrate. Forming the anode may include forming a first metal oxide material on the substrate, forming a metal layer over the first metal oxide material, forming a protective barrier over the metal layer, and forming a second metal oxide material over the amorphous protection material. The protective barrier may be an amorphous protection material overlying the metal layer.
H01L 51/44 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation - Details of devices
H01L 51/52 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof specially adapted for light emission, e.g. organic light emitting diodes (OLED) or polymer light emitting devices (PLED) - Details of devices
H01L 51/00 - Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
24.
PROCESS KITS AND RELATED METHODS FOR PROCESSING CHAMBERS TO FACILITATE DEPOSITION PROCESS ADJUSTABILITY
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide applicable for use in semiconductor manufacturing, includes a plate having a first face and a second face opposing the first face. The flow guide includes a first fin set extending from the second face, and a second fin set extending from the second face. The second fin set is spaced from the first fin set to define a flow path between the first fin set and the second fin set. The flow path has a serpentine pattern between the first fin set and the second fin set.
C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
25.
SPIN-ORBIT TORQUE MRAM STRUCTURE AND MANUFACTURE THEREOF
Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
Exemplary semiconductor processing methods may include providing an oxygen-containing precursor to a semiconductor processing chamber, where a substrate may be positioned. The substrate may include a trench formed between two columns and molybdenum-containing metal regions in a plurality of recesses formed in at least one of the columns. At least two of the molybdenum-containing metal regions may be connected by a molybdenum-containing first liner formed on at least a portion of a sidewall of the trench. The methods may include forming a plasma of the oxygen-containing precursor. The methods may include contacting the molybdenum-containing first liner with plasma effluents of the oxygen-containing precursor, thereby forming an oxidized portion of molybdenum. The methods may include providing a halide precursor. The methods may include contacting oxidized portion of the molybdenum with plasma effluents of the halide precursor, thereby removing the oxidized portion of molybdenum from the sidewall of the trench.
A method of training a neural network includes obtaining two ground truth thickness profiles a test substrate, obtaining two thickness profiles for the test substrate as measured by an in-situ monitoring system while the test substrate is on polishing pads of different thicknesses, generating an estimated thickness profile for another thickness value that is between the two thickness values by interpolating between the two profiles, and training a neural network using the estimated thickness profile.
A carrier head for chemical mechanical polishing includes a housing, a substrate mounting surface, and a retaining ring assembly. The retaining ring assembly includes an inner ring surrounding the substrate mounting surface and having an inner surface to retain the substrate below the substrate mounting surface, a first actuator to adjust a vertical load on the inner ring, an outer ring surrounding the inner ring, and a second actuator positioned between the inner ring and the outer ring. The inner ring has a plurality of slots that are formed in a lower surface and that extend from the inner surface to an outer surface of the inner ring to divide the inner ring into a plurality of arcuate segments suspended from an upper portion. The second actuator applies a radially inward pressure such that the plurality of arcuate segments flex inwardly relative to the upper portion.
Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.
Molybdenum(0) and coordination complexes are described. Methods for depositing molybdenum-containing films on a substrate are described. The substrate is exposed to a molybdenum precursor and a reactant to form the molybdenum-containing film (e.g., elemental molybdenum, molybdenum oxide, molybdenum carbide, molybdenum silicide, molybdenum disulfide, molybdenum nitride). The exposures can be sequential or simultaneous.
C07F 11/00 - Compounds containing elements of Groups 6 or 16 of the Periodic System
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/02 - Pretreatment of the material to be coated
C23C 16/18 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material from metallo-organic compounds
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 14/56 - Apparatus specially adapted for continuous coating; Arrangements for maintaining the vacuum, e.g. vacuum locks
32.
METHODS AND MECHANISMS FOR PREVENTING FLUCTUATION IN MACHINE-LEARNING MODEL PERFORMANCE
An electronic device manufacturing system configured to receive, by a processor, input data reflecting a feature related to a manufacturing process of a substrate. The manufacturing system is further configured to generate a characteristic sequence defining a relationship between at least two manufacturing parameters, and determine a relationship between one or more variables related to the feature and the characteristic sequence. The manufacturing system is further configured to determine a weight based on the determined relationship and apply the weight to the feature. The manufacturing system is further configured to train a machine-learning model in view of the weighted feature.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
Embodiments of the disclosure relate to methods for forming silicon based gapfill within substrate features. A flowable silicon film is formed within the feature with a greater thickness on the bottom and top surfaces than the sidewall surface. An etch plasma removes the silicon film from the sidewall surface. A conversion plasma is used to convert the silicon film to a silicon based gapfill (e.g., silicon oxide). In some embodiments, the silicon film is preferentially converted on the top and bottom surface before being etched from the sidewall surface.
Methods and systems for monitoring wafer processing results continuously and in real-time. In some embodiments, a system may comprise at least one non-active chamber with at least one feedthrough access port which is configured to interact with a metrology apparatus. The feedthrough access port has a surface exposed to an inner volume of the non-active chamber and has a fluorine-based coating covering the surface. The non-active chamber has a wafer access port to one or more other chambers. The metrology apparatus is positioned external to the non-active chamber and is oriented to detect metrology data through one of the feedthrough access ports. A data collection apparatus is connected to the metrology apparatus and configured to continuously receive data from the metrology apparatus.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
35.
SYSTEMS AND METHODS FOR OPTIMIZING FULL HORIZONTAL SCANNED BEAM DISTANCE
Provided herein are approaches for optimizing a full horizontal scanned beam distance of an accelerator beam. In one approach, a method may include positioning a first Faraday cup along a first side of an intended beam-scan area, positioning a second Faraday cup along a second side of the intended beam-scan area, scanning an ion beam along the first and second sides of the intended beam-scan area, measuring a first beam current of the ion beam at the first Faraday cup and measuring a second beam current of the ion beam at the second Faraday cup, and determining an optimal scan distance of the ion beam across the intended beam-scan area based on the first beam current and the second beam current.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
Embodiments of the disclosure relate to methods for selectively removing metal material from the top surface and sidewalls of a feature. The metal material which is covered by a flowable polymer material remains unaffected. In some embodiments, the metal material is formed by physical vapor deposition resulting in a relatively thin sidewall thickness. Any metal material remaining on the sidewall after removal of the metal material from the top surface may be etched by an additional etch process. The resulting metal layer at the bottom of the feature facilitates selective metal gapfill of the feature.
The present disclosure relates to flow guides, process kits, and related methods for processing chambers to facilitate deposition process adjustability. In one implementation, a flow guide includes a middle plate having a first side and a second side opposing the first side along a first direction. The first side and the second side are arcuate. The flow guide includes a first flange extending outwardly relative to a third side of the middle plate and outwardly relative to an outer face of the middle plate, and a second flange extending outwardly relative to a fourth side of the middle plate and outwardly relative to the outer face of the middle plate. The fourth side opposes the third side along a second direction that intersects the first direction. The flow guide includes a rectangular flow opening defined between the first flange and the second flange.
Embodiments of the present disclosure generally relate to methods of modifying and engineering the effective thickness of an optical device substrate. The methods provide for depositing a material that is index-matched to the substrate to alter a thickness distribution of the optical device. By adjusting the thickness distribution, the optical path of light is modulated to direct the light to the output coupling grating.
A system may include a first semiconductor processing station configured to deposit a material on a first semiconductor wafer and a chemical tank that provides liquid to the processing station during a deposition process. The chemical tank may provide measurements of characteristics of the liquid to a controller. The controller may be configured to receive the measurements from the chemical tank; provide an input based on the measurements to a trained model that is configured to generate an output that adjusts an operating parameter of the first station such that the thickness uniformity of the material is closer to a target thickness uniformity; and cause the first station to deposit the material on a second wafer using the operating parameter as adjusted by the output.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A carrier head for chemical mechanical polishing includes a housing, a substrate mounting surface, and a retaining ring assembly. The retaining ring assembly includes an inner ring surrounding the substrate mounting surface and having an inner surface to retain the substrate below the substrate mounting surface, a first actuator to adjust a vertical load on the inner ring, an outer ring surrounding the inner ring, and a second actuator positioned between the inner ring and the outer ring. The inner ring has a plurality of slots that are formed in a lower surface and that extend from the inner surface to an outer surface of the inner ring to divide the inner ring into a plurality of arcuate segments suspended from an upper portion. The second actuator applies a radially inward pressure such that the plurality of arcuate segments flex inwardly relative to the upper portion.
B24B 37/005 - Control means for lapping machines or devices
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A sensor device comprises a quartz crystal microbalance (QCM) and a coating on at least a portion of a surface of the QCM, wherein the coating selectively reacts with radicals of a target gas and does not react with stable molecules of the target gas. The QCM is configured such that a resonant frequency of the QCM changes in response to reaction of the radicals of the target gas with the coating, wherein the change in the resonant frequency of the QCM correlates to an amount of the radicals of the target gas that have reacted with the coating.
A system for nanoimprint lithography includes a master holder, a spacer, and a stamp support. The spacer supports the stamp support as a stamp material is cured to create a stamp. A method of forming an optical device using the nanoimprint lithography system with a spacer is provided. A system for the nanoimprint lithography may also include a master and a stamp support holder. The stamp support holder includes a plurality of projections defining a plurality of vacuum channels. The vacuum channels are in fluid communication with a vacuum source to support a stamp support as a stamp material is cured to create a stamp.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
A lamp and epitaxial processing apparatus are described herein. In one example, the lamp includes a bulb, a filament, and a plurality of filament supports disposed in spaced-apart relation to the filament, each of the filament supports having a hook support and a hook. The hook includes a connector configured to fasten the hook to the hook support, a first vertical portion extending from the connector toward the filament, and a rounded portion extending from an end of the first vertical portion distal from the connector and configured to wrap around the filament. A second vertical portion extends from an end of the rounded portion distal from the first vertical portion and the second vertical portion has a length between 60% and 100% of the length of the first vertical portion.
A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the upper insulator structure surface. The first portion of the upper insulator structure surface forms an interior volume with the lower plate structure surface.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
45.
SEMICONDUCTOR DEVICE PACKAGES WITH ENHANCED THERMO-MECHANICAL RELIABILITY
The present disclosure relates to thin-form-factor semiconductor device packages, and methods and systems for forming the same. Embodiments of the disclosure include methods and apparatus for forming semiconductor device packages that include frames that are coated with a layer of a coupling agent on which subsequently layers are formed. The utilization of the coupling agent between the frame and subsequently formed layers enhances the thermo-mechanical reliability of the package frames by mitigating the stress induced by any subsequently formed insulation layers and/or RDLs, and by providing improved coupling between such layers and the relatively smooth surfaces of the frames.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The processing region may be at least partially defined between a faceplate and a substrate support on which the semiconductor substrate is seated. A bias power may be applied to the substrate support from a bias power source. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.
Methods and systems for monitoring wafer processing results continuously and in real-time. In some embodiments, a system may comprise at least one non-active chamber with at least one feedthrough access port which is configured to interact with a metrology apparatus. The feedthrough access port has a surface exposed to an inner volume of the non-active chamber and has a fluorine-based coating covering the surface. The non-active chamber has a wafer access port to one or more other chambers. The metrology apparatus is positioned external to the non-active chamber and is oriented to detect metrology data through one of the feedthrough access ports. A data collection apparatus is connected to the metrology apparatus and configured to continuously receive data from the metrology apparatus.
Methods and apparatus for processing a substrate are provided herein. For example, a method for processing a substrate comprises forming a plasma reaction between titanium tetrachloride (TlCl4), hydrogen (H2), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.
C23C 16/507 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges using external electrodes, e.g. in tunnel type reactors
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes determining, based on a guardband, guardband violation data points of the plurality of data points of the trace data. The method further includes determining, based on the guardband violation data points, guardband violation shape characterization. Classification of additional guardband violation data points of additional trace data is to be based on the guardband violation shape characterization. Performance of a corrective action associated with the substrate processing system is based on the classification.
A method for etching a hardmask layer includes forming a photoresist layer comprising an organometallic material on a hardmask layer comprising a metal-containing material, exposing the photoresist layer to ultraviolet radiation through a mask having a selected pattern, removing un-irradiated areas of the photoresist layer to pattern the photoresist layer, forming a passivation layer comprising a carbon-containing material selectively on a top surface of the patterned photoresist layer, and etching the hardmask layer exposed by the patterned photoresist layer having the passivation layer formed thereon.
Embodiments of the disclosure include an apparatus and method of forming a memory device with high-mobility oxide semiconductor channels. In some embodiments, the apparatus, for example, includes a plurality of alternating layers formed over a surface of a substrate; a gate coupled to each of the word line layers of the plurality of alternating layers; a multi-layer channel memory cell having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region, the multi-layer channel also having a first conductive layer and a second conductive layer, the first conductive layer being different from the second conductive layer; and an ONO layer stack disposed between the gates and the multi-layer channel, wherein the ONO layer stack extends in the first direction between the source region and the drain region.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
52.
HARDWARE TO UNIFORMLY DISTRIBUTE ACTIVE SPECIES FOR SEMICONDUCTOR FILM PROCESSING
A substrate processing system is provided having a processing chamber. The processing chamber includes a lid plate, one or more chamber sidewalls, and a chamber base that collectively define a processing volume. An annular plate is coupled to the lid plate, and an edge manifold is fluidly coupled to the processing chamber through the annular plate and the lid plate. The substrate processing system includes a center manifold that is coupled to the lid plate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
54.
REGENERATION ANNEAL OF METAL OXIDE THIN-FILM TRANSISTORS
A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150° C. to about 275° C.
Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-κ metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-κ metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
422), and argon (Ar) in a region between a lid heater and a showerhead of a process chamber or the showerhead and a substrate while providing RF power at a pulse frequency of about 5 kHz to about 100 kHz and at a duty cycle of about 10% to about 20% and flowing reaction products into the process chamber to selectively form a titanium material layer upon a silicon surface of the substrate.
Methods and apparatus for processing a substrate are provided herein. For example, a processing volume for processing a substrate and a pressure system in fluid communication with the processing volume and comprising a throttle valve assembly including a housing, a sensing device disposed in an interior of the housing, and a fan open to the interior of the housing, wherein, during operation of the pressure system to control a pressure within the processing volume, the sensing device is responsive to temperature changes in the interior of the housing such that the fan remains off when a temperature of the interior of the housing is less than a predetermined temperature and automatically turns on when the temperature within interior of the housing is equal to or greater than the predetermined temperature.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
C23C 16/52 - Controlling or regulating the coating process
59.
DIRECT WORD LINE CONTACT AND METHODS OF MANUFACTURE FOR 3D MEMORY
Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.
A substrate support assembly includes a plate structure and an insulator structure. The plate structure includes an upper plate and a lower plate. The lower plate includes a lower plate structure surface. The insulator structure is disposed beneath the plate structure. The insulator structure includes a lower insulator structure surface and an upper insulator structure surface. A first portion of the upper insulator structure surface is recessed with respect to a second portion of the upper insulator structure surface. The first portion of the upper insulator structure surface forms an interior volume with the lower plate structure surface.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
A sensor device comprises a quartz crystal microbalance (QCM) and a coating on at least a portion of a surface of the QCM, wherein the coating selectively reacts with radicals of a target gas and does not react with stable molecules of the target gas. The QCM is configured such that a resonant frequency of the QCM changes in response to reaction of the radicals of the target gas with the coating, wherein the change in the resonant frequency of the QCM correlates to an amount of the radicals of the target gas that have reacted with the coating.
tt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes generating, based on the trace data and a plurality of allowable types of variance, a guardband including an upper limit and a lower limit for fault detection. The method further includes causing, based on the guardband, performance of a corrective action associated with the substrate processing system.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G05B 19/404 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
A system for nanoimprint lithography includes a master holder, a spacer, and a stamp support. The spacer supports the stamp support as a stamp material is cured to create a stamp. A method of forming an optical device using the nanoimprint lithography system with a spacer is provided. A system for the nanoimprint lithography may also include a master and a stamp support holder. The stamp support holder includes a plurality of projections defining a plurality of vacuum channels. The vacuum channels are in fluid communication with a vacuum source to support a stamp support as a stamp material is cured to create a stamp.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates that have property values that meet threshold values. The method further includes determining, based on the trace data, a dynamic acceptable area outside of guardband limits. The method further includes causing, based on the dynamic acceptable area outside of the guardband limits, performance of a corrective action associated with the substrate processing system.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes generating, based on the trace data and a plurality of allowable types of variance, a guardband including an upper limit and a lower limit for fault detection. The method further includes causing, based on the guardband, performance of a corrective action associated with the substrate processing system.
Embodiments described herein relate to a method of using an apparatus for forming waveguides. The method includes positioning a substrate at a first rotation angle, exposing the substrate to an ion beam, forming first partial trenches defined by adjacent angled device structures with the first device angle, rotating the substrate to a second rotation angle, exposing the substrate to the ion beam, etching the first partial trenches, and repeating the method from about 1 cycle to about 100 cycles to form a plurality of trenches defined by adjacent angled device structures. The first rotation angle is selected to form one or more angled device structures with a first device angle relative to a vector parallel to the substrate. The ion beam is configured to contact the substrate at a beam angle ϑ relative to a surface normal of the substrate.
A method of forming a contact layer in a semiconductor structure includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.
Embodiments of the present disclosure generally relate to a substrate processing chamber, and methods for cleaning the substrate processing chamber are provided herein. An electrode cleaning ring is disposed in a lower portion of a process volume (e.g., disposed below a substrate support in the process volume). The electrode cleaning ring is a capacitively coupled plasma source. The electrode cleaning ring propagates plasma into the lower portion of the process volume. RF power is provided to the electrode cleaning ring via an RF power feed-through. The RF plasma propagated by the electrode cleaning ring removes deposition residue in the lower portion of the process volume.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
B08B 7/00 - Cleaning by methods not provided for in a single other subclass or a single group in this subclass
71.
EPI SELF-HEATING SENSOR TUBE AS IN-SITU GROWTH RATE SENSOR
A method and apparatus for determining a growth rate on a semiconductor substrate is described herein. The apparatus is an optical sensor, such as an optical growth rate sensor. The optical sensor is positioned in an exhaust of a deposition chamber. The optical sensor is self-heated using one or more internal heating elements, such as a resistive heating element. The internal heating elements are configured to heat a sensor coupon. A film is formed on the sensor coupon by exhaust gases flowed through the exhaust and is correlated to film growth on a substrate within a process volume of the deposition chamber.
G01N 21/84 - Systems specially adapted for particular applications
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
Disclosed are approaches for forming semiconductor device layers. One method may include forming a plurality of openings in a semiconductor structure, and forming a film layer atop the semiconductor structure by delivering a material at a non-zero angle relative to a normal extending perpendicular from an upper surface of the semiconductor structure. The film layer may be formed along the upper surface of the semiconductor structure without being formed along a sidewall of each opening of the plurality of openings, wherein an opening though the film layer remains above each opening of the plurality of openings.
A method of forming a structure on a substrate is provided. The method includes depositing a dipole dopant containing (DDC) layer including a dipole dopant on a first and second region of a dielectric layer (DL) of the substrate. A hardmask (HM) is deposited over the DDC deposited on the first and the second regions. A patterned photoresist layer (PR) is formed over the HM. The PR includes a first portion that is positioned over the first region and an opening that is positioned to expose a portion of the HM that is disposed over the second region of the substrate. The HM and DDC within the second region are etched and at least a portion of the DL is exposed within the second region. The PR is removed and the substrate is annealed to diffuse the dipole dopant into a portion of the DL disposed in the first region.
Methods for forming a transition metal material on a substrate and thermal processing such metal containing material in a cluster processing system are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a two-dimensional transition metal dichalcogenide layer on a substrate in a first processing chamber disposed in a cluster processing system, thermally treating the two-dimensional transition metal dichalcogenide layer to form a treated metal layer in a second processing chamber disposed in the cluster processing system, and forming a capping layer on the treated metal layer in a third processing chamber disposed in the cluster processing system.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
75.
HIGH-TEMPERATURE SUBSTRATE SUPPORT ASSEMBLY WITH FAILURE PROTECTION
A substrate support assembly includes a puck, comprising a heating element, a power distribution assembly, and an insulator comprising at least one of alumina or thermoplastic disposed between the puck and the power distribution assembly, wherein an electrical connection between the heating element and the power distribution assembly comprises a terminal and a conical washer.
H05B 3/26 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor mounted on insulating base
76.
ANALYSIS OF MULTI-RUN CYCLIC PROCESSING PROCEDURES
A method includes receiving time trace sensor data associated with a substrate processing procedure. The substrate processing procedure includes two or more sets of processing conditions. At least a first set of processing conditions and a second set of processing conditions each include one or more operations performed repeatedly. The method further includes separating a first and second portion of the time trace sensor data corresponding to the first and second sets of processing conditions into a first and second plurality of cycle data. The method further includes processing the first plurality of cycle data and the second plurality of cycle data to generate summary data. The method further includes providing an alert to s user. The alert is based on the summary data.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
A carrier transport system (100) for transporting carriers in a vacuum processing system in a main transport direction (T) along a first transport path (T1) and along a second transport path (T2) extending next to the first transport path (T1) and for transferring carriers in a path switch direction (S) between the first transport path (T1) and the second transport path (T2) is described. The carrier transport system comprises a common movable support (119) at which a first carrier holder (110) and a second carrier holder (120) are provided spaced apart from each other in the path switch direction (S). In a first transport state (i) of the common movable support (119), the first carrier holder (110) is configured to hold a first carrier (10) in alignment with the first transport path (T1) and the second carrier holder (120) is configured to hold a second carrier (20) in alignment with the second transport path (T2) laterally spaced apart from the first carrier (10). The common movable support is movable in the path switch direction (S) for moving the first carrier holder (110) and the second carrier holder (120) synchronously in the path switch direction (S). Further described is a vacuum deposition system with such a carrier transport system as well as methods of transporting carriers in a vacuum processing system.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
78.
CARRIER FOR HOLDING A SUBSTRATE, APPARATUS FOR DEPOSITING A LAYER ON A SUBSTRATE, AND METHOD FOR SUPPORTING A SUBSTRATE
A carrier (100) for holding a substrate (10) in a curved state is provided. The carrier (100) comprises a carrier body (110) having a curved substrate support surface (111), a sealing (120) for providing a sealing between an edge of the substrate (10) and the carrier body (110), and a substrate fixation (130) for pressing the edge of the substrate (10) onto the sealing (120). The carrier body (110) comprises one or more gas supply conduits (140) to provide a gas cushion between a back side (10B) of the substrate (10) and the curved substrate support surface (111). Further, an apparatus for depositing a layer on a substrate in a curved state and a method for supporting a substrate in a curved state in a vacuum deposition chamber are provided.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 14/54 - Controlling or regulating the coating process
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
79.
PHYSICALLY-INFORMED MULTI-SYSTEM HARDWARE OPERATING WINDOWS
Embodiments disclosed herein include a method for use with a semiconductor processing tool. In an embodiment, the method comprises configuring the semiconductor processing tool, running a benchmark test on the semiconductor processing tool, providing hardware operating window (HOW) analytics, generating a design of experiment (DoE) using the HOW analytics, implementing process optimization, and releasing an iteration of the process recipe. In an embodiment, the method further comprises margin testing the iteration of the process recipe.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
A substrate processing system is provided having a processing chamber. The processing chamber includes a lid plate, one or more chamber sidewalls, and a chamber base that collectively define a processing volume. An annular plate is coupled to the lid plate, and an edge manifold is fluidly coupled to the processing chamber through the annular plate and the lid plate. The substrate processing system includes a center manifold that is coupled to the lid plate.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/06 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the deposition of metallic material
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
81.
REGENERATION ANNEAL OF METAL OXIDE THIN-FILM TRANSISTORS
A method of forming a TFT is provided including forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer and the channel layer is annealed. A gate insulator layer is formed over the channel layer and an ILD is deposited over the gate insulator layer to form the TFT. The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volt or less. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition includes a temperature of about 150 °C to about 275 °C.
A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.
The present disclosure relates to thin-form-factor semiconductor device packages, and methods and systems for forming the same. Embodiments of the disclosure include methods and apparatus for forming semiconductor device packages that include frames that are coated with a layer of a coupling agent on which subsequently layers are formed. The utilization of the coupling agent between the frame and subsequently formed layers enhances the thermo-mechanical reliability of the package frames by mitigating the stress induced by any subsequently formed insulation layers and/or RDLs, and by providing improved coupling between such layers and the relatively smooth surfaces of the frames.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
84.
METHODS FOR PATTERNING SUBSTRATES TO ADJUST VOLTAGE PROPERTIES
A method of adjusting a threshold voltage in a field-effect-transistor (FET) device includes performing a deposition process to deposit a diffusion barrier layer over a gate dielectric layer in a first region, a second region, and a third region of a semiconductor structure, performing a first patterning process to remove a portion of the deposited diffusion layer in the first region, performing a second patterning process to partially remove a portion of the deposited diffusion barrier layer in the second region, performing a dipole layer deposition process to deposit a dipole layer over the gate dielectric layer in the first region, and the diffusion barrier layer in the second region and in the third region, and performing an annealing process to drive dipole dopants from the dipole layer into the gate dielectric layer.
Embodiments of the disclosure include an apparatus and method of forming a memory device with high-mobility oxide semiconductor channels. In some embodiments, the apparatus, for example, includes a plurality of alternating layers formed over a surface of a substrate; a gate coupled to each of the word line layers of the plurality of alternating layers; a multi-layer channel memory cell having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region, the multi-layer channel also having a first conductive layer and a second conductive layer, the first conductive layer being different from the second conductive layer; and an ONO layer stack disposed between the gates and the multi-layer channel, wherein the ONO layer stack extends in the first direction between the source region and the drain region.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
A three-dimensional NAND flash memory structure may include solid channel cores of epitaxial silicon that are grown directly from a silicon substrate reference. The alternating oxide-nitride material layers may be formed as a stack, and a channel hole may be etched through the material layers that extends down to the silicon substrate. A tunneling layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate up through the channel holes. In some implementations, support structures may be formed in channel holes or in slits of the memory array to provide physical support while the epitaxial silicon cores are grown through the channels.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates that have property values that meet threshold values. The method further includes determining, based on the trace data, a dynamic acceptable area outside of guardband limits. The method further includes causing, based on the dynamic acceptable area outside of the guardband limits, performance of a corrective action associated with the substrate processing system.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G05B 19/404 - Numerical control (NC), i.e. automatically operating machines, in particular machine tools, e.g. in a manufacturing environment, so as to execute positioning, movement or co-ordinated operations by means of programme data in numerical form characterised by control arrangements for compensation, e.g. for backlash, overshoot, tool offset, tool wear, temperature, machine construction errors, load, inertia
A method includes identifying trace data including a plurality of data points, the trace data being associated with production, via a substrate processing system, of substrates having property values that meet threshold values. The method further includes determining, based on a guardband, guardband violation data points of the plurality of data points of the trace data. The method further includes determining, based on the guardband violation data points, guardband violation shape characterization. Classification of additional guardband violation data points of additional trace data is to be based on the guardband violation shape characterization. Performance of a corrective action associated with the substrate processing system is based on the classification.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
09 - Scientific and electric apparatus and instruments
Goods & Services
Equipment for testing chemical delivery systems including ampoules or containers Downloadable and/or recorded software for testing chemical delivery systems including ampoules or containers; downloadable and/or recorded software for on-tool metrology measurements for semiconductor manufacturing
90.
HYBRID ION SOURCE FOR ALUMINUM ION GENERATION USING A TARGET HOLDER AND ORGANOALUMINIUM COMPOUNDS
An ion source that is capable of different modes of operation is disclosed. The ion source includes an insertable target holder includes a hollow interior into which the solid dopant material is disposed. The target holder may a porous surface at a first end, through which vapors from the solid dopant material may enter the arc chamber. The porous surface inhibits the passage of liquid or molten dopant material into the arc chamber. The target holder is also constructed such that it may be refilled with dopant material when the dopant material within the hollow interior has been consumed. The ion source may have several gas inlets. When the insertable target holder is used, the ion source may supply a first gas, such as a halogen containing gas. When operating in a second mode, the ion source may utilize an organoaluminium gas.
A system and method for reducing charge on a workpiece disposed on a platen is disclosed. The system includes an ionizer to generate ionized gas from the source of backside gas. The ionizer may be used to introduce ionized gas into the backside gas channels of the platen. A controller is used to selectively allow backside gas and/or ionized gas into the backside gas channels. In certain embodiments, the platen also includes an exhaust channel in communication with an exhaust valve to ensure that the pressure within the volume between the top surface of the platen and the workpiece is maintained in a desired range. In one embodiment, the system includes a valving system in communication with the source of backside gas and also in communication with the ionizer. In another embodiment, the amount of ionization performed by the ionizer is programmable.
A method includes receiving, by a processing device, first data. The first data includes data from one or more sensors of a processing chamber and is associated with a processing operation. The first data is resolved in at least two dimensions, one of which is time. The method further includes providing the first data to a model. The method further includes receiving from the model second data. The second data includes an indication of an evolution of a processing parameter during the processing operation. The method further includes causing performance of a corrective action in view of the second data.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control (DNC), flexible manufacturing systems (FMS), integrated manufacturing systems (IMS), computer integrated manufacturing (CIM)
93.
HIGH RESOLUTION ADVANCED OLED SUB-PIXEL CIRCUIT AND PATTERNING METHOD
Embodiments described herein relate to a sub-pixel. The sub-pixel includes an anode, overhang structures, separation structures, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by adjacent first pixel isolation structures (PIS) and adjacent second PIS. The overhang structures are disposed on the first PIS. The overhang structures include a second structure disposed over the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past an upper surface of the first structure. The first structure is disposed over the first PIS. Separation structures are disposed over the second PIS. The OLED material is disposed over the anode and an upper surface of the separation structures. The cathode disposed over the OLED material and an upper surface of the separation structures.
A first robot arm places a calibration object into a load lock that separates a factory interface from a transfer chamber using a first taught position. A second robot arm retrieves the calibration object from the load lock using a second taught position. A controller determines, using a sensor, a first offset amount between a calibration object center of the calibration object and a pocket center of the second robot arm. The controller determines a characteristic error value that represents a misalignment between the first taught position of the first robot arm and the second taught position of the second robot arm based on the first offset amount. The first robot arm or the second robot arm uses the first characteristic error value to compensate for the misalignment for objects transferred between the first robot arm and the second robot arm via the load lock.
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
B65G 47/90 - Devices for picking-up and depositing articles or materials
B25J 13/08 - Controls for manipulators by means of sensing devices, e.g. viewing or touching devices
B25J 11/00 - Manipulators not otherwise provided for
95.
PHYSICALLY-INFORMED MULTI-SYSTEM HARDWARE OPERATING WINDOWS
Embodiments disclosed herein include a method for use with a semiconductor processing tool. In an embodiment, the method comprises configuring the semiconductor processing tool, running a benchmark test on the semiconductor processing tool, providing hardware operating window (HOW) analytics, generating a design of experiment (DoE) using the HOW analytics, implementing process optimization, and releasing an iteration of the process recipe. In an embodiment, the method further comprises margin testing the iteration of the process recipe.
Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.
A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of a surface of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source; and applying the dose map to process the substrate using the patterning energy source.
A method may include generating a residual curvature map for a substrate, the residual curvature map being based upon a measurement of the substrate. The method may include generating a dose map based upon the residual curvature map, the dose map being for processing the substrate using a patterning energy source. The method may include applying the dose map to process the substrate using the patterning energy source, wherein the dose map is applied by performing a plurality of exposures of the substrate to the patterning energy source, at a plurality of different twist angles.
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
99.
DRUG COMPOSITIONS AND METHODS OF PREPARING THE SAME
Methods for providing an inorganic oxide coating to high aspect ratio particles containing an active pharmaceutical ingredient are described as are compositions containing such coated particles.
Embodiments of the present disclosure generally relate to apparatus and methods for semiconductor processing, more particularly, to a thermal process chamber. In one or more embodiments, a process chamber comprises a first window, a second window, a substrate support disposed between the first window and the second window, and a motorized rotatable radiant spot heating source disposed over the first window and configured to provide radiant energy through the first window.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
F27B 17/00 - Furnaces of a kind not covered by any of groups
F27D 5/00 - Supports, screens, or the like for the charge within the furnace
B23K 26/00 - Working by laser beam, e.g. welding, cutting or boring
B23K 26/08 - Devices involving relative movement between laser beam and workpiece
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
B23K 26/06 - Shaping the laser beam, e.g. by masks or multi-focusing
