An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
G06F 1/06 - Clock generators producing several clock signals
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G06F 1/12 - Synchronisation of different clock signals
G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.
H03K 19/17784 - Structural details for adapting physical parameters for supply voltage
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
H03K 19/1776 - Structural details of configuration resources for memories
A system for determining a power requirement for a device powered by a buck converter on a system on chip based on Time on pulses (Ton) is disclosed. A buck converter supplies output voltage to enable the device. The buck converter is driven by a Ton pulse generator generating Ton pulses to control charging of a load capacitor. A counter counts the Ton pulses during the supply of output voltage while the device is enabled. A controller is coupled to the counter and the buck converter. The controller determines the power requirement for the device based on the count of the Ton pulses. The power requirement may be used to adjust the trim value to change the width of the Ton pulses for greater energy efficiency.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
G06F 1/26 - Power supply means, e.g. regulation thereof
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
4.
On-chip system with context-based energy reduction
A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.
A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
8.
ON-DEMAND ACTIVATION OF MEMORY PATH DURING SLEEP OR ACTIVE MODES
A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.
A method of determining power data of a system on a chip is disclosed. A plug-in module is provided for installation on the chip. The plug-in module is activated to take a snapshot of the data in power related registers of components on the chip when user provided software is executed on the system on a chip. The collected data is streamed to an external computing device. A spreadsheet of the collected register data may be displayed. A graphic representation of the collected register data may be displayed.
A power evaluation tool for a system on a chip is disclosed. The tool includes a power profiling plug-in module executed by a processor on the chip to collect a snapshot of register data of components on the chip associated with power consumption by the system during a certain time. The collected register data is streamed to an external computing device. A data parser module receives the streamed collected register data on the external computing device. A spreadsheet generator module creates a spreadsheet of the collected register data. An interface module displays a graphic representation of the collected register data on a display.
A low power high bandwidth analog to digital converter system is disclosed. A first analog signal input receives an input signal. A first programmable gain amplifier receives the input signal. An analog to digital converter (ADC) is coupled to the output of the first programmable gain amplifier and samples the input signal for conversion to a digital signal. A controller is coupled to the ADC and the first programmable gain amplifier. The controller selects and enables either a reduced power mode or a power up mode for the first programmable gain amplifier and the ADC. The power up mode is selected and enabled when the input signal is to be sampled to operate the first programmable gain amplifier and the ADC to sample the input signal.
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
12.
Memory module with fine-grained voltage adjustment capabilities
Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.
H03K 19/17784 - Structural details for adapting physical parameters for supply voltage
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
H03K 19/1776 - Structural details of configuration resources for memories
A system for determining a power requirement for a device powered by a buck converter on a system on chip based on Time on pulses (Ton) is disclosed. A buck converter supplies output voltage to enable the device. The buck converter is driven by a Ton pulse generator generating Ton pulses to control charging of a load capacitor. A counter counts the Ton pulses during the supply of output voltage while the device is enabled. A controller is coupled to the counter and the buck converter. The controller determines the power requirement for the device based on the count of the Ton pulses. The power requirement may be used to adjust the trim value to change the width of the Ton pulses for greater energy efficiency.
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
G06F 1/26 - Power supply means, e.g. regulation thereof
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A low power caching architecture is disclosed. The architecture includes multiple data memory regions, each including a cache memory. The data memory regions are coupled to a peripheral device. A host processor is operable to control power to each of the plurality of data memory regions. The host processor is operable to power on any of data memory regions and power down any unused data memory regions of the data memory regions. A cache control logic is operable to receive a data request from the host processor. The cache control logic requests the data from the peripheral. The host processor powers on at least one of the data memory regions, and stores the requested data in the cache memory of the powered on data memory region.
A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
In some embodiments, a system comprises a microcontroller system comprising a CPU, an I/O module, and a microcontroller system power input, a power supply comprising a first power supply output providing power at a first power level, and a second power supply output providing power at a second power level, and a switch comprising a signal input communicatively coupled to the I/O module and configured to receive a status signal from the I/O module, a first switch power input electrically coupled to the first power supply output, a second switch power input electrically coupled to the second power supply output, and a switch power output electrically coupled to the microcontroller system power input and configured to output power to the microcontroller system.
A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.
A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.
A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.
G10L 25/09 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being zero crossing rates
G10L 15/10 - Speech classification or search using distance or distortion measures between unknown speech and reference templates
G10L 15/02 - Feature extraction for speech recognition; Selection of recognition unit
A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.
A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.
A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
G06F 1/06 - Clock generators producing several clock signals
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G06F 1/12 - Synchronisation of different clock signals
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
24.
Low power adaptive linear resonant actuator driver using accelerometer
An accelerometer and a linear resonant actuator (LRA) are mechanically coupled, such as by being mounted to the same circuit board. The output of the accelerometer is evaluated in order to select a drive frequency for the LRA. For example, the drive frequency may be varied while measuring the magnitude of acceleration induced by the LRA. The output of the accelerometer may further be used to perform a fitness tracking function, such as counting steps or detecting an activity level.
G01P 15/12 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by alteration of electrical resistance
G01P 21/00 - Testing or calibrating of apparatus or devices covered by the other groups of this subclass
H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
G01C 22/00 - Measuring distance traversed on the ground by vehicles, persons, animals or other moving solid bodies, e.g. using odometers or using pedometers
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A buck converter may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.
H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.
A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
G06F 1/06 - Clock generators producing several clock signals
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G06F 1/12 - Synchronisation of different clock signals
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
38.
Counter/timer array for generation of complex patterns independent of software control
A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.
A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.
An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
42.
Reference voltage sub-system allowing fast power up from extended periods of ultra-low power standby mode
A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
43.
Method and apparatus for controlling substrate and well biases for reduced power requirements
An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.
G06F 1/06 - Clock generators producing several clock signals
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G06F 1/12 - Synchronisation of different clock signals
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.
A method for pre-loading a SAR ADC with an initial value for a selected range of high-order bits. If the ADC resolves at either an upper or a lower limit set by the pre-loaded value, the ADC may discard the pre-loaded value and perform a full search. Alternatively, the ADC may perform one or more “bonus steps” before giving up and performing a full search.
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.
G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.
An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.
H02M 1/12 - Arrangements for reducing harmonics from ac input or output
G06F 1/06 - Clock generators producing several clock signals
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
G06F 1/12 - Synchronisation of different clock signals
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03L 7/00 - Automatic control of frequency or phase; Synchronisation
G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion
50.
Low power automatic calibration method for high frequency oscillators
A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.
G06F 1/06 - Clock generators producing several clock signals
H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
G06F 1/12 - Synchronisation of different clock signals
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A clock generator for use in an electronic system comprising an integrated circuit such as a microcontroller. A plurality of oscillators are selectively enabled to produce a respective plurality of oscillator signals. For each of a plurality of clock outputs, a mux selects a respective one of the oscillator signals in response to a respective select signal provided by a clocked facility. The selected oscillator signal is gated out as the respective clock signal in response to a respective gate signal also provided by the clocked facility.
G06F 1/06 - Clock generators producing several clock signals
G06F 1/12 - Synchronisation of different clock signals
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
G06F 13/10 - Program control for peripheral devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
An energy consumption monitor for use in an electronic system comprising an integrated circuit such as a microcontroller. The monitor comprises a counter adapted to accumulate pulses developed by a charge source, each pulse indicative of the delivery of one unit of charge to a load circuit. A monitoring facility monitors the counter to develop an energy consumption record over time.
A method and apparatus for generating an improved reference voltage for use, for example, in a system requiring accurate low power operation. In particular, our reference voltage generator is adapted to output VREF as a function of the voltage difference between V1 and V2. The reference voltage generator is further adapted to include our reference voltage tuner to compensate for predetermined sensitivities of the reference voltage VREF, and to adjust the absolute value of VREF. During manufacturing and system test, a driver may be used to drive a buffered or unbuffered version of VREF to off-chip test functionality. Also, a configuration memory may be used to store the trim settings during normal operation, and make such settings available to outside resources.
An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.
A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated.
patents
