Ambiq Micro, Inc.

United States of America

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IPC Class
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices 10
G06F 1/12 - Synchronisation of different clock signals 10
G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system 10
G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage 10
H03M 1/12 - Analogue/digital converters 10
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Status
Pending 7
Registered / In Force 33
Found results for  patents

1.

Voice Activty Detection Using Zero Crossing Detection

      
Application Number 17081378
Status Pending
Filing Date 2020-10-27
First Publication Date 2022-04-28
Owner Ambiq Micro, Inc. (USA)
Inventor Serwy, Roger David

Abstract

A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.

IPC Classes  ?

  • G10L 25/09 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being zero crossing rates
  • G10L 15/02 - Feature extraction for speech recognition; Selection of recognition unit
  • G10L 15/10 - Speech classification or search using distance or distortion measures between unknown speech and reference templates

2.

Low Complexity Voice Activity Detection Algorithm

      
Application Number 17081640
Status Pending
Filing Date 2020-10-27
First Publication Date 2022-04-28
Owner Ambiq Micro, Inc. (USA)
Inventor Serwy, Roger David

Abstract

A first VAD system outputs a pulse stream for zero crossings in an audio signal. The pulse density of the pulse stream is evaluated to identify speech. The audio signal may have noise added to it before evaluating zero crossings. A second VAD system rectifies each audio signal sample and processes each rectified sample by updating a first statistic and evaluating the rectified sample per a first threshold condition that is a function of the first statistic. Rectified samples meeting the first threshold condition may be used to update a second statistic and the rectified sample evaluated per a second threshold condition that is a function of the second statistic. Rectified samples meeting the second threshold condition may be used to update a third statistic. The audio signal sample may be selected as speech if the second statistic is less than a downscaled third statistic.

IPC Classes  ?

  • G10L 19/26 - Pre-filtering or post-filtering
  • G06F 17/18 - Complex mathematical operations for evaluating statistical data

3.

ADAPTIVE VOLTAGE CONVERTER

      
Application Number 17512346
Status Pending
Filing Date 2021-10-27
First Publication Date 2022-02-17
Owner AMBIQ MICRO, INC. (USA)
Inventor Hanson, Scott

Abstract

An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

4.

Power Efficient Context-Based Audio Processing

      
Application Number 17495661
Status Pending
Filing Date 2021-10-06
First Publication Date 2022-01-27
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Shah, Arpit
  • Hanson, Scott Mclean
  • Nease, Stephen Howard

Abstract

A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.

IPC Classes  ?

  • H04R 3/04 - Circuits for transducers for correcting frequency response
  • G06F 3/16 - Sound input; Sound output
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06F 40/205 - Parsing

5.

Buck Converter With Inductor Sensor

      
Application Number 17121593
Status Pending
Filing Date 2020-12-14
First Publication Date 2021-04-08
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Bogue, Ivan
  • Mortazavi, Yousof

Abstract

A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit

6.

Adaptive voltage converter

      
Application Number 16993231
Grant Number 11249509
Status In Force
Filing Date 2020-08-13
First Publication Date 2020-11-26
Grant Date 2022-02-15
Owner AMBIQ MICRO, INC. (USA)
Inventor Hanson, Scott

Abstract

An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

IPC Classes  ?

  • H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • G06F 1/06 - Clock generators producing several clock signals
  • H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

7.

Low power adaptive linear resonant actuator driver using accelerometer

      
Application Number 16379228
Grant Number 10868486
Status In Force
Filing Date 2019-04-09
First Publication Date 2020-10-15
Grant Date 2020-12-15
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Mortazavi, Yousof
  • Hanson, Scott Mclean

Abstract

An accelerometer and a linear resonant actuator (LRA) are mechanically coupled, such as by being mounted to the same circuit board. The output of the accelerometer is evaluated in order to select a drive frequency for the LRA. For example, the drive frequency may be varied while measuring the magnitude of acceleration induced by the LRA. The output of the accelerometer may further be used to perform a fitness tracking function, such as counting steps or detecting an activity level.

IPC Classes  ?

  • H02P 25/032 - Reciprocating, oscillating or vibrating motors
  • H02P 25/06 - Linear motors
  • G01P 15/12 - Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by alteration of electrical resistance
  • G01P 21/00 - Testing or calibrating of apparatus or devices covered by the other groups of this subclass
  • H04L 29/08 - Transmission control procedure, e.g. data link level control procedure
  • B06B 1/02 - Processes or apparatus for generating mechanical vibrations of infrasonic, sonic or ultrasonic frequency making use of electrical energy
  • H02K 41/02 - Linear motors; Sectional motors
  • G01C 22/00 - Measuring distance traversed on the ground by vehicles, persons, animals or other moving solid bodies, e.g. using odometers or using pedometers
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

8.

Buck converter with power saving mode

      
Application Number 16375345
Grant Number 10897199
Status In Force
Filing Date 2019-04-04
First Publication Date 2020-10-08
Grant Date 2021-01-19
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Bogue, Ivan
  • Lu, Yanning

Abstract

A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
  • H02M 3/157 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

9.

Buck converter with inductor sensor

      
Application Number 16375391
Grant Number 10897203
Status In Force
Filing Date 2019-04-04
First Publication Date 2020-10-08
Grant Date 2021-01-19
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Bogue, Ivan
  • Mortazavi, Yousof

Abstract

A buck converter may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

IPC Classes  ?

  • H02M 3/156 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

10.

Very Low Power Microcontroller System

      
Application Number 16864155
Status Pending
Filing Date 2020-05-01
First Publication Date 2020-08-13
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott Mclean
  • Cermak, Daniel Martin
  • Deal, Eric Jonathan
  • Sheafor, Stephen James
  • Popps, Donovan Scott
  • Baur, Mark A.

Abstract

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

IPC Classes  ?

  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • G11C 5/14 - Power supply arrangements
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
  • G06F 1/26 - Power supply means, e.g. regulation thereof
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system

11.

SRAM with error correction in retention mode

      
Application Number 16833142
Grant Number 10885972
Status In Force
Filing Date 2020-03-27
First Publication Date 2020-07-16
Grant Date 2021-01-05
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Chevallier, Christophe J.
  • Sheafor, Stephen James

Abstract

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

IPC Classes  ?

  • G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
  • G11C 11/419 - Read-write [R-W] circuits
  • G11C 29/04 - Detection or location of defective memory elements

12.

Strong arm comparator

      
Application Number 16375434
Grant Number 10601322
Status In Force
Filing Date 2019-04-04
First Publication Date 2020-03-24
Grant Date 2020-03-24
Owner AMBIQ MICRO, INC. (USA)
Inventor Bogue, Ivan

Abstract

A buck converter is disclosed that may operate in a low power mode or a high power mode based on a power requirements of a load. In the high power mode, modifications to increase frequency response include a higher polling frequency for a comparator, a lower impedance divider in a feedback circuit, a higher biasing current for a comparator, and larger switches for providing current to a reactive step-down circuit of the buck converter. In the low power mode these modifications are reversed. The buck converter may make use of an improved strong arm comparator and a circuit for sensing presence of an inductor in the reactive step-down circuit.

IPC Classes  ?

  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

13.

Power efficient context-based audio processing

      
Application Number 16508062
Grant Number 11172293
Status In Force
Filing Date 2019-07-10
First Publication Date 2020-01-16
Grant Date 2021-11-09
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Shah, Arpit
  • Hanson, Scott Mclean
  • Nease, Stephen Howard

Abstract

A low power voice processing system that includes a plurality of non-audio sensors, at least one microphone system, and a plurality of audio modules, at least some of which can be configured in selected modes. A context determination module is connected to the plurality of audio modules, and further connected to receive input from the plurality of non-audio sensors and the at least one microphone system. The context determination module acts to determine use context for the voice processing system and at least in part selects mode operation of at least some of the plurality of audio modules.

IPC Classes  ?

  • H04R 3/04 - Circuits for transducers for correcting frequency response
  • G06F 3/16 - Sound input; Sound output
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
  • G06F 40/205 - Parsing

14.

Reference voltage sub-system allowing power up from extended periods of ultra-low power standby mode

      
Application Number 16519339
Grant Number 10498347
Status In Force
Filing Date 2019-07-23
First Publication Date 2019-11-14
Grant Date 2019-12-03
Owner Ambiq Micro Inc. (USA)
Inventor Bogue, Ivan

Abstract

A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

IPC Classes  ?

  • H03M 1/00 - Analogue/digital conversion; Digital/analogue conversion
  • H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • H03M 1/20 - Increasing resolution using an n bit system to obtain n + m bits, e.g. by dithering

15.

SRAM with error correction in retention mode

      
Application Number 16399261
Grant Number 10629257
Status In Force
Filing Date 2019-04-30
First Publication Date 2019-08-22
Grant Date 2020-04-21
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Chevallier, Christophe J.
  • Sheafor, Stephen James

Abstract

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

IPC Classes  ?

  • G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
  • G11C 11/419 - Read-write [R-W] circuits
  • G11C 29/04 - Detection or location of defective memory elements

16.

Adaptive voltage converter

      
Application Number 16276931
Grant Number 10782728
Status In Force
Filing Date 2019-02-15
First Publication Date 2019-06-13
Grant Date 2020-09-22
Owner Ambiq Micro, Inc. (USA)
Inventor Hanson, Scott

Abstract

An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

17.

Very low power microcontroller system

      
Application Number 15933153
Grant Number 10754414
Status In Force
Filing Date 2018-03-22
First Publication Date 2019-03-14
Grant Date 2020-08-25
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott Mclean
  • Cermak, Daniel Martin
  • Deal, Eric Jonathan
  • Sheafor, Stephen James
  • Popps, Donovan Scott
  • Baur, Mark A

Abstract

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

IPC Classes  ?

  • G06F 1/32 - Means for saving power
  • G06F 1/26 - Power supply means, e.g. regulation thereof
  • G11C 5/14 - Power supply arrangements
  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

18.

Very low power microcontroller system

      
Application Number 16005315
Grant Number 10795425
Status In Force
Filing Date 2018-06-11
First Publication Date 2019-03-14
Grant Date 2020-10-06
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott Mclean
  • Cermak, Daniel Martin
  • Deal, Eric Jonathan
  • Sheafor, Stephen James
  • Popps, Donovan Scott
  • Baur, Mark A

Abstract

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

IPC Classes  ?

  • G06F 1/32 - Means for saving power
  • G06F 1/26 - Power supply means, e.g. regulation thereof
  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G11C 5/14 - Power supply arrangements
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

19.

Very low power microcontroller system

      
Application Number 16013767
Grant Number 10788884
Status In Force
Filing Date 2018-06-20
First Publication Date 2019-03-14
Grant Date 2020-09-29
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Hanson, Scott Mclean
  • Cermak, Daniel Martin
  • Deal, Eric Jonathan
  • Sheafor, Stephen James
  • Popps, Donovan Scott
  • Baur, Mark A

Abstract

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

IPC Classes  ?

  • G06F 1/32 - Means for saving power
  • G06F 1/26 - Power supply means, e.g. regulation thereof
  • G11C 5/14 - Power supply arrangements
  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

20.

SRAM with error correction in retention mode

      
Application Number 15982835
Grant Number 10319429
Status In Force
Filing Date 2018-05-17
First Publication Date 2019-03-07
Grant Date 2019-06-11
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Chevallier, Christophe J.
  • Sheafor, Stephen James

Abstract

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

IPC Classes  ?

  • G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency

21.

Counter/timer array for generation of complex patterns independent of software control

      
Application Number 15674242
Grant Number 10416703
Status In Force
Filing Date 2017-08-10
First Publication Date 2019-02-14
Grant Date 2019-09-17
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Sheafor, Stephen James
  • Popps, Donovan Scott

Abstract

A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F 1/12 - Synchronisation of different clock signals

22.

SRAM With Address Dependent Power Usage

      
Application Number 15648298
Status Pending
Filing Date 2017-07-12
First Publication Date 2019-01-17
Owner Ambiq Micro, Inc. (USA)
Inventor Chevallier, Christophe J.

Abstract

A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.

IPC Classes  ?

23.

SRAM with multiple power domains

      
Application Number 16049078
Grant Number 10347328
Status In Force
Filing Date 2018-07-30
First Publication Date 2018-11-22
Grant Date 2019-07-09
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Chevallier, Christophe J.
  • Hanson, Scott

Abstract

An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.

IPC Classes  ?

  • G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
  • G11C 11/419 - Read-write [R-W] circuits
  • G11C 11/418 - Address circuits
  • G11C 5/14 - Power supply arrangements

24.

SRAM with error correction in retention mode

      
Application Number 15697286
Grant Number 10096354
Status In Force
Filing Date 2017-09-06
First Publication Date 2018-10-09
Grant Date 2018-10-09
Owner AMBIQ MICRO, INC. (USA)
Inventor
  • Chevallier, Christophe J.
  • Sheafor, Stephen James

Abstract

A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

IPC Classes  ?

  • G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

25.

Reference voltage sub-system allowing fast power up from extended periods of ultra-low power standby mode

      
Application Number 15439887
Grant Number 10401942
Status In Force
Filing Date 2017-02-22
First Publication Date 2018-08-23
Grant Date 2019-09-03
Owner Ambiq Micro Inc. (USA)
Inventor
  • Bogue, Ivan
  • Lu, Yanning
  • Mandyam, Bharath

Abstract

A reference voltage sub-system that allows fast power up after spending extended periods in an ultra-low power standby mode. The reference voltage sub-system includes a reference voltage buffer, a reference voltage keeper, an active calibration facility for selectively adjusting the reference voltage keeper output to match the reference voltage buffer output, and a selection means for selecting between the reference voltage buffer output and the reference voltage keeper output.

IPC Classes  ?

  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage

26.

Method and apparatus for controlling substrate and well biases for reduced power requirements

      
Application Number 15782090
Grant Number 10332589
Status In Force
Filing Date 2017-10-12
First Publication Date 2018-07-26
Grant Date 2019-06-25
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott
  • Chevallier, Christophe J.

Abstract

An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.

IPC Classes  ?

  • G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 11/413 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
  • G11C 5/14 - Power supply arrangements

27.

Low power autonomous peripheral management

      
Application Number 15841673
Grant Number 10585448
Status In Force
Filing Date 2017-12-14
First Publication Date 2018-05-31
Grant Date 2020-03-10
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Sheafor, Stephen James
  • Hanson, Scott
  • Popps, Donovan

Abstract

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

28.

SRAM with multiple power domains

      
Application Number 15345229
Grant Number 10062431
Status In Force
Filing Date 2016-11-07
First Publication Date 2018-05-10
Grant Date 2018-08-28
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Chevallier, Christophe J.
  • Hanson, Scott

Abstract

An SRAM facility adapted to power an address path using a first developed supply voltage and to power a data path using a second developed supply voltage, the first and second developed power supplies being separate, distinct, and different. The SRAM facility includes a power supply facility or a voltage supply facility adapted to develop the first and second supply voltages.

IPC Classes  ?

  • G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store
  • G11C 11/419 - Read-write [R-W] circuits
  • G11C 11/418 - Address circuits

29.

Digital-based power reduction technique for SAR ADCs

      
Application Number 15486795
Grant Number 09912346
Status In Force
Filing Date 2017-04-13
First Publication Date 2018-03-06
Grant Date 2018-03-06
Owner Ambiq Micro, Inc. (USA)
Inventor Hamilton, Joseph

Abstract

A method for pre-loading a SAR ADC with an initial value for a selected range of high-order bits. If the ADC resolves at either an upper or a lower limit set by the pre-loaded value, the ADC may discard the pre-loaded value and perform a full search. Alternatively, the ADC may perform one or more “bonus steps” before giving up and performing a full search.

IPC Classes  ?

  • H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
  • H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
  • H03M 1/18 - Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
  • H03M 1/12 - Analogue/digital converters

30.

SRAM with active substrate bias

      
Application Number 15412039
Grant Number 09830974
Status In Force
Filing Date 2017-01-22
First Publication Date 2017-11-28
Grant Date 2017-11-28
Owner Ambiq Micro, Inch (USA)
Inventor
  • Hanson, Scott
  • Chevallier, Christophe J.

Abstract

An SRAM circuit that includes a biasing circuit adapted to selectively bias the transistors of the SRAM array to lower the threshold voltage of selected transistors. The SRAM circuit includes well voltages and positive voltages that are selectively different, and substrate voltages and ground voltages that are selectively different.

IPC Classes  ?

  • G11C 11/00 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C 11/417 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
  • G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
  • G11C 5/14 - Power supply arrangements

31.

Sub-threshold enabled flash memory system

      
Application Number 15245016
Grant Number 09779788
Status In Force
Filing Date 2016-08-23
First Publication Date 2017-10-03
Grant Date 2017-10-03
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Chevallier, Christophe J.
  • Cermak, Daniel M.
  • Hanson, Scott

Abstract

A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 7/14 - Dummy cell management; Sense reference voltage generators

32.

Adaptive voltage converter

      
Application Number 15516883
Grant Number 10338632
Status In Force
Filing Date 2015-09-15
First Publication Date 2017-08-31
Grant Date 2019-07-02
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott
  • Lu, Yanning

Abstract

An adaptive voltage converter adapted to compensate for the exponential sensitivities of sub-threshold and near-threshold circuits. The converter can change its power/performance characteristics between different energy modes. The converter may comprise two or more voltage converters/regulators. A multiplexing circuit selects between the outputs of the several converters/regulators depending on the state of a control signal generated by a control facility. The converter is specially adapted to change the output of each converter/regulator based on a number of variables, including, for example, process corner, temperature and input voltage.

IPC Classes  ?

  • H02M 1/12 - Arrangements for reducing harmonics from ac input or output
  • G06F 1/06 - Clock generators producing several clock signals
  • H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G06F 1/3237 - Power saving characterised by the action undertaken by disabling clock generation or distribution
  • G06F 1/3287 - Power saving characterised by the action undertaken by switching off individual functional units in the computer system
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
  • G06F 1/3296 - Power saving characterised by the action undertaken by lowering the supply or operating voltage
  • H02M 3/158 - Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
  • H02M 1/00 - APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF - Details of apparatus for conversion

33.

Low power automatic calibration method for high frequency oscillators

      
Application Number 14879863
Grant Number 09939839
Status In Force
Filing Date 2015-10-09
First Publication Date 2016-04-21
Grant Date 2018-04-10
Owner Ambiq Micro, Inc. (USA)
Inventor Sheafor, Stephen James

Abstract

A clock calibrator for use in an electronic system comprising an integrated circuit such as a microcontroller. The clock calibrator embodies a frequency adjustment facility adapted dynamically to adjust the frequency of one or more high-frequency clock generators as a function of a lower-frequency reference clock.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • H03L 7/06 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L 7/181 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
  • H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G06F 1/32 - Means for saving power

34.

Peripheral clock management

      
Application Number 14855105
Grant Number 09703313
Status In Force
Filing Date 2015-09-15
First Publication Date 2016-04-21
Grant Date 2017-07-11
Owner Ambiq Micro, Inc. (USA)
Inventor Sheafor, Stephen James

Abstract

A clock generator for use in an electronic system comprising an integrated circuit such as a microcontroller. A plurality of oscillators are selectively enabled to produce a respective plurality of oscillator signals. For each of a plurality of clock outputs, a mux selects a respective one of the oscillator signals in response to a respective select signal provided by a clocked facility. The selected oscillator signal is gated out as the respective clock signal in response to a respective gate signal also provided by the clocked facility.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • G06F 1/12 - Synchronisation of different clock signals
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G06F 1/32 - Means for saving power

35.

Low power autonomous peripheral management

      
Application Number 14918397
Grant Number 09880583
Status In Force
Filing Date 2015-10-20
First Publication Date 2016-04-21
Grant Date 2018-01-30
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Sheafor, Stephen James
  • Hanson, Scott
  • Popps, Donovan

Abstract

A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G06F 1/32 - Means for saving power

36.

Low power asynchronous counters in a synchronous system

      
Application Number 14918406
Grant Number 09772648
Status In Force
Filing Date 2015-10-20
First Publication Date 2016-04-21
Grant Date 2017-09-26
Owner Ambiq Micro, Inc. (USA)
Inventor Sheafor, Stephen James

Abstract

A clock synchronizer adapted to synchronize reading a Timer that is clocked asynchronously to the system clock.

IPC Classes  ?

  • G06F 1/06 - Clock generators producing several clock signals
  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 11/30 - Monitoring
  • G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
  • G06F 13/10 - Program control for peripheral devices
  • G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
  • G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
  • H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03M 1/12 - Analogue/digital converters
  • H03L 7/00 - Automatic control of frequency or phase; Synchronisation
  • G06F 1/32 - Means for saving power

37.

Method and apparatus for monitoring energy consumption

      
Application Number 14918437
Grant Number 10578656
Status In Force
Filing Date 2015-10-20
First Publication Date 2016-04-21
Grant Date 2020-03-03
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott
  • Sheafor, Stephen James
  • Baker, David Cureton

Abstract

An energy consumption monitor for use in an electronic system comprising an integrated circuit such as a microcontroller. The monitor comprises a counter adapted to accumulate pulses developed by a charge source, each pulse indicative of the delivery of one unit of charge to a load circuit. A monitoring facility monitors the counter to develop an energy consumption record over time.

IPC Classes  ?

  • G01R 21/127 - Arrangements for measuring electric power or power factor by using pulse modulation
  • G01R 21/133 - Arrangements for measuring electric power or power factor by using digital technique

38.

Low power tunable reference voltage generator

      
Application Number 14342189
Grant Number 10013006
Status In Force
Filing Date 2012-06-29
First Publication Date 2014-10-23
Grant Date 2018-07-03
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott
  • Ifesinachukwu, Kenneth Gozie
  • Kanji, Ajaykumar A.

Abstract

A method and apparatus for generating an improved reference voltage for use, for example, in a system requiring accurate low power operation. In particular, our reference voltage generator is adapted to output VREF as a function of the voltage difference between V1 and V2. The reference voltage generator is further adapted to include our reference voltage tuner to compensate for predetermined sensitivities of the reference voltage VREF, and to adjust the absolute value of VREF. During manufacturing and system test, a driver may be used to drive a buffered or unbuffered version of VREF to off-chip test functionality. Also, a configuration memory may be used to store the trim settings during normal operation, and make such settings available to outside resources.

IPC Classes  ?

  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/10 - Distribution of clock signals
  • H03K 21/02 - Input circuits
  • H03K 23/50 - Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
  • H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
  • G05F 3/08 - Regulating voltage or current wherein the variable is dc

39.

Low power tunable reference current generator

      
Application Number 14342177
Grant Number 09939826
Status In Force
Filing Date 2012-06-29
First Publication Date 2014-08-07
Grant Date 2018-04-10
Owner Ambiq Micro, Inc. (USA)
Inventor
  • Hanson, Scott
  • Ifesinachukwu, Kenneth Gozie
  • Kanji, Ajaykumar A.

Abstract

An improved reference current generator for use in an integrated circuit. A voltage difference generator generates two voltages that are separated by a relatively small electrical potential. The two closely separated voltages are applied across a resistive element with relatively large impedance value resulting in a small and stable reference current. The stable reference current is mirrored and, if desired, amplified for use on the integrated circuit. A driver selectively drives state information off chip for assisting in post-silicon correction of unwanted sensitivities. A configuration memory stores values used to adjust effective device widths and lengths for correcting unwanted sensitivities.

IPC Classes  ?

  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/10 - Distribution of clock signals
  • H03K 21/02 - Input circuits
  • H03K 23/50 - Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
  • H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
  • G05F 3/08 - Regulating voltage or current wherein the variable is dc

40.

Method and apparatus for low jitter distributed clock calibration

      
Application Number 13401268
Grant Number 08924765
Status In Force
Filing Date 2012-02-21
First Publication Date 2013-01-03
Grant Date 2014-12-30
Owner Ambiq Micro, Inc. (USA)
Inventor Sheafor, Stephen

Abstract

A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • H03K 21/00 - PULSE TECHNIQUE - Details of pulse counters or frequency dividers
  • G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc
  • G06F 1/10 - Distribution of clock signals
  • H03K 21/02 - Input circuits
  • H03K 23/50 - Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
  • H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption