Taiwan Semiconductor Manufacturing Company, Ltd.

Taiwan, Province of China

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[Owner] Taiwan Semiconductor Manufacturing Company, Ltd. 38,446
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H01L 29/66 - Types of semiconductor device 9,448
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate 6,871
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices 5,461
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device 5,458
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1.

PACKAGE STRUCTURE

      
Application Number 18766674
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lin, Tsung-Shu
  • Chen, Tsung-Yu
  • Hung, Wensen

Abstract

A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

IPC Classes  ?

  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
  • H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
  • H01L 23/498 - Leads on insulating substrates

2.

SEMICONDUCTOR PACKAGE AND FORMING METHOD OF THE SAME

      
Application Number 18307793
Status Pending
Filing Date 2023-04-26
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Yang, Su-Chun
  • Twu, Jih-Churng
  • Tsai, Jui Hsuan
  • Chang, Chiao-Chun
  • Liu, Chung-Shi
  • Yu, Chen-Hua

Abstract

A semiconductor package includes a first integrated circuit, a plurality of second integrated circuits, at least one adhesion layer and a molding compound. The second integrated circuits are bonded onto the first integrated circuit. The at least one adhesion layer extends between the second integrated circuits and on sidewalls of the second integrated circuits. The molding compound extends between the second integrated circuits and on the at least one adhesion layer, wherein a surface of the at least one adhesion layer facing away from the first integrated circuit is substantially coplanar with a surface of the molding compound facing away from the first integrated circuit.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/82 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers

3.

METHOD OF FABRICATING PACKAGE STRUCTURE

      
Application Number 18766684
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Shen, Wen-Wei
  • Huang, Sung-Hui
  • Hou, Shang-Yun

Abstract

A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

4.

SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF

      
Application Number 18765351
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Yang, Tsuching
  • Sun, Hung-Chang
  • Lai, Sheng-Chih
  • Jiang, Yu-Wei
  • Chiang, Kuo-Chang

Abstract

A semiconductor device includes a stacked structure, a first flight of steps, a second flight of steps and a third flight of steps. The stacked structure includes a memory array. The first flight of steps, the second flight of steps and the third flight of steps are disposed at a first end of the stacked structure along a first direction. The second flight of steps disposed between the first flight of steps and the third flight of steps, and a length of the second flight of steps is less than a length of the first flight of steps and a length of the third flight of steps along the first direction.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
  • H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region

5.

MINIMIZATION OF SILICON GERMANIUM FACETS IN PLANAR METAL OXIDE SEMICONDUCTOR STRUCTURES

      
Application Number 18766402
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (Taiwan, Province of China)
Inventor
  • Wang, Yi-Sin
  • Cheng, Shan-Yun
  • Kao, Ching-Hung
  • Chou, Jing-Jyu
  • Chen, Yi-Ting

Abstract

A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/762 - Dielectric regions
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions
  • H01L 29/66 - Types of semiconductor device

6.

TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME, AND MANUFACTURING METHOD THEREOF

      
Application Number 18766644
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor Manfrini, Mauricio

Abstract

A back-end-of-line transistor includes a channel strip, a source contact, a drain contact, a high-k dielectric strip, a gate pattern, and self-assembled monolayers. The channel strip includes a semiconductor oxide material. The source contact contacts a first end of the channel strip. The drain contact contacts a second end of the channel strip. The high-k dielectric strip extends on the channel strip in between the first end and the second end of the channel strip. The gate pattern extends on the high-k dielectric strip. The self-assembled monolayers are disposed in between the channel strip and the source and drain contacts. The self-assembled monolayers include a compound having a polar group. The polar group is bonded to at least one selected from the channel strip, the source contact, and the drain contact.

IPC Classes  ?

  • H10N 50/80 - Constructional details
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/01 - Manufacture or treatment

7.

FLASH MEMORY CELL WITH TUNABLE TUNNEL DIELECTRIC CAPACITANCE

      
Application Number 18306488
Status Pending
Filing Date 2023-04-25
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Doornbos, Gerben
  • Vellianitis, Georgios
  • Van Dal, Marcus Johannes Henricus
  • Lin, Yu-Ming
  • Madia, Oreste

Abstract

Some embodiments relate to an integrated device, including a control gate over a substrate, the control gate having a first length; a tunnel dielectric on the control gate; a floating gate having a second length on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; a channel on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and source/drain terminals on the channel, wherein the first length of the control gate is less than the second length of the floating gate.

IPC Classes  ?

  • H01L 29/788 - Field-effect transistors with field effect produced by an insulated gate with floating gate
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

8.

METAL LAYERS FOR INCREASING POLARIZATION OF FERROELECTRIC MEMORY DEVICE

      
Application Number 18763112
Status Pending
Filing Date 2024-07-03
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Huang, Yen-Chieh
  • Chen, Hai-Ching
  • Lin, Chung-Te

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.

IPC Classes  ?

  • H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

9.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

      
Application Number 18766863
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Hsiung, Te-Chih
  • Wu, Jyun-De
  • Wang, Peng
  • Lin, Huan-Just

Abstract

Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

10.

SEMICONDUCTOR DEVICE AND METHODS OF FORMATION

      
Application Number 18765779
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Liu, Wei-Kang
  • Shih, Chih-Tsung
  • Lu, Hau-Yan
  • Tsui, Yingkit Felix
  • Jeng, Lee-Shian

Abstract

Some implementations described herein include a photonics integrated circuit device including a photonics structure. The photonics structure includes a waveguide structure and an optical attenuator structure. In some implementation, the optical attenuator structure is formed on an end region of the waveguide structure and includes a metal material or a doped material. In some implementations, the optical attenuator structure includes a gaussian doping profile within a portion of the waveguide structure. The optical attenuator structure may absorb electromagnetic waves at the end of the waveguide structure with an efficiency that is improved relative to a spiral optical attenuator structure or metal cap optical attenuator structure.

IPC Classes  ?

  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
  • G02B 6/134 - Integrated optical circuits characterised by the manufacturing method by substitution by dopant atoms
  • G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching

11.

THREE-STATE MEMORY DEVICE

      
Application Number 18764426
Status Pending
Filing Date 2024-07-05
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor Manfrini, Mauricio

Abstract

The present disclosure relates to an integrated chip including a bottom electrode arranged within a dielectric layer. A memory element is directly over the bottom electrode and is arranged within the dielectric layer. A top electrode is directly over the memory element and is arranged within the dielectric layer. A conductive via is directly over the top electrode. A pair of lines that extend along opposing sidewalls of the top electrode are directly over, and intersect, an uppermost surface of the memory element. The pair of lines are directly under, and intersect, a lowermost surface of the via.

IPC Classes  ?

  • H10N 50/80 - Constructional details
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/01 - Manufacture or treatment
  • H10N 50/10 - Magnetoresistive devices

12.

FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING

      
Application Number 18766853
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Yu, Jeng-Wei
  • Pai, Yi-Fang
  • Jeng, Pei-Ren
  • Li, Chii-Horng
  • Yeo, Yee-Chia

Abstract

A method of forming a fin field-effect transistor device includes: forming a gate structure over a first fin and a second fin; forming, on a first side of the gate structure, a first recess and a second recess in the first fin and the second fin, respectively; and forming a source/drain region in the first and second recesses, which includes: forming a barrier layer in the first and second recesses; forming a first epitaxial material over the barrier layer, where a first portion of the first epitaxial material over the first fin is spaced apart from a second portion of the first epitaxial material over the second fin; forming a second epitaxial material over the first and second portions of the first epitaxial material, where the second epitaxial material extends continuously from the first fin to the second fin; and forming a capping layer over the second epitaxial material.

IPC Classes  ?

  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

13.

IN-LINE ELECTRICAL DETECTION OF DEFECTS AT WAFER LEVEL

      
Application Number 18766856
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, LTD. (Taiwan, Province of China)
Inventor
  • Huang, Yu-Hsuan
  • Chen, Chien-Liang
  • Lee, Pei-Hsuan

Abstract

In a semiconductor manufacturing method includes providing a plurality of patterns on a semiconductor substrate. The patterns include an NMOS structure arranged next to an N+/N well structure, and/or a PMOS structure arranged next to a P+/P well structure. The method further includes: receiving a plurality of images by applying an electron beam to the patterns; and transferring the semiconductor substrate to a next process step if there is no image conversion according to a predetermined image contrast property of the patterns.

IPC Classes  ?

  • G01R 31/307 - Contactless testing using electron beams of integrated circuits
  • H01L 21/66 - Testing or measuring during manufacture or treatment

14.

IMAGE SENSOR WITH PHOTOSENSITIVITY ENHANCEMENT REGION

      
Application Number 18765738
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Wang, Tzu-Jui
  • Yamashita, Yuichiro

Abstract

The present disclosure relates to an image sensor including a pixel along a substrate. The pixel includes a first semiconductor region having a first doping type. A second semiconductor region is directly over the first semiconductor region. The second semiconductor region has a second doping type opposite the first doping type and meets the first semiconductor region at a p-n junction. A ring-shaped third semiconductor region laterally surrounds the first and second semiconductor regions. The ring-shaped third semiconductor region has the first doping type. A ring-shaped fourth semiconductor region laterally surrounds the ring-shaped third semiconductor region. The ring-shaped fourth semiconductor region has the second doping type. A ring-shaped fifth semiconductor region is directly over the ring-shaped third semiconductor region and has the second doping type.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H01L 31/107 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode

15.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18764868
Status Pending
Filing Date 2024-07-05
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Wu, Wei-Cheng
  • Teng, Li-Feng

Abstract

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

IPC Classes  ?

  • H10B 41/42 - Simultaneous manufacture of periphery and memory cells
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/44 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
  • H10B 41/47 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a floating-gate layer also being used as part of the peripheral transistor
  • H10B 41/48 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a tunnel dielectric layer also being used as part of the peripheral transistor
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

16.

Stealth Patterning Formation for Bonding Improvement

      
Application Number 18308266
Status Pending
Filing Date 2023-04-27
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chung, Ming-Tsu
  • Lin, Yung-Chi
  • Chen, Yen-Ming

Abstract

A method includes forming a patterned treating mask over a first surface dielectric layer of a first package component, wherein portions of the first surface dielectric layer are exposed through the patterned treating mask, performing a selective plasma treatment on the portions of the first surface dielectric layer that are exposed through the patterned treating mask to form treated portions, removing the patterned treating mask, and bonding a second surface dielectric layer in a second package component to the first surface dielectric layer.

IPC Classes  ?

  • H01L 21/311 - Etching the insulating layers
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

17.

SEMICONDUCTOR DEVICE FABRICATION METHODS AND DEVICES FOR FORMING THE SAME

      
Application Number 18140444
Status Pending
Filing Date 2023-04-27
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Hou, Te-Chien
  • Chen, Chih Hung
  • Shen, Chi-Hsiang
  • Cheng, Yu-Heng
  • Suen, Shich-Chang

Abstract

A chemical mechanical polishing device is provided according to some embodiments. The chemical mechanical polishing device comprises a polishing pad. The polishing pad includes a plurality of stacks of first pad fractions and a plurality of stacks of second pad fractions. The first pad fractions and the second pad fractions have different hardness. The stacks of first pad fractions and the stacks of the second pad fractions are arranged with a pattern corresponding to a predetermined feature of a structure to be polished by the chemical mechanical polishing device. The predetermined feature may include a surface profile or a material of the structure to be polished.

IPC Classes  ?

  • B24B 37/26 - Lapping pads for working plane surfaces characterised by the shape of the lapping pad surface, e.g. grooved
  • B24B 37/04 - Lapping machines or devices; Accessories designed for working plane surfaces
  • H01L 21/3105 - After-treatment

18.

FIN FIELD-EFFECT TRANSISTOR DEVICE AND METHODS OF FORMING

      
Application Number 18449443
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Pin-Wen
  • Ko, Yu-Chen
  • Chen, Chi-Yuan
  • Cheng, Ya-Yi
  • Tsai, Chun-I
  • Lin, Wei-Jung
  • Chang, Chih-Wei
  • Tsai, Ming-Hsing
  • Jang, Syun-Ming
  • Lo, Wei-Jen

Abstract

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

19.

Millimeter-Wave Passive Circuit Designs with Wafer-Level Chip-Scale Package

      
Application Number 18309277
Status Pending
Filing Date 2023-04-28
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Hsieh, Hsieh-Hung
  • Chou, Chen Cheng
  • Yang, Hwa-Yu
  • Cheng, Ming-Da
  • Hsiao, Ru-Shang
  • Yeh, Tzu-Jin
  • Chen, Ching-Hui
  • Li, Shenggao

Abstract

A device including a substrate, a front-end module circuit situated over the substrate and configured to provide radio frequency communications, and a wafer-level chip-scale package circuit situated over the front-end module circuit and connected to the front-end module circuit and configured to provide passive components for radio frequency communications.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/66 - High-frequency adaptations
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

20.

PASSIVATION STRUCTURE WITH INCREASED THICKNESS FOR METAL PADS

      
Application Number 18766279
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Huang, Hung-Shu
  • Liu, Ming-Chyi

Abstract

A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/495 - Lead-frames
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

21.

INDUCTOR STRUCTURE, SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF

      
Application Number 18766471
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chang, Chih-Yuan
  • Wu, Jiun-Yi
  • Lee, Chien-Hsun
  • Liu, Chung-Shi
  • Yu, Chen-Hua

Abstract

A structure includes a first via and a first conductive line embedded in a first dielectric layer and spaced apart from each other by the first dielectric layer. A first metal pattern disposed on the first via and embedded in a second dielectric layer. A first conductive via disposed on the first conductive line and embedded in the second dielectric layer. The first metal pattern and the first conductive via are spaced apart from each other and are located on a first horizontal level, and the first metal pattern has an open ring shape. A second via disposed on the first metal pattern and embedded in a third dielectric layer. An inductor structure including the first via, the first metal pattern, and the second via.

IPC Classes  ?

  • H01L 23/64 - Impedance arrangements
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
  • H01L 23/498 - Leads on insulating substrates
  • H03H 7/01 - Frequency selective two-port networks

22.

PHOTOMASK INSPECTION METHOD AND APPARATUS THEREOF

      
Application Number 18765359
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Taiwan, Province of China)
Inventor
  • Wen, Chih-Wei
  • Tseng, Hsin-Fu
  • Chen, Chien-Lin

Abstract

An inspection apparatus includes: an inspection apparatus includes: a stage configured to receive a photomask; a radiation source configured to emit a first radiation beam for inspecting the photomask; and an aperture stop configured to receive a second radiation beam reflected from the photomask through an aperture of the aperture stop, wherein the aperture is tangent at a center of the aperture stop.

IPC Classes  ?

  • G03F 1/84 - Inspecting
  • G03F 1/86 - Inspecting by charged particle beam [CPB]
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor

23.

TRIM WALL PROTECTION METHOD FOR MULTI-WAFER STACKING

      
Application Number 18765696
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Li, Sheng-Chan
  • Chou, Cheng-Hsien
  • Chen, Sheng-Chau
  • Tsai, Cheng-Yuan
  • Wu, Kuo-Ming

Abstract

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a substrate and an interconnect structure on the substrate. The interconnect structure has a plurality of interconnects disposed within a dielectric structure. A dielectric material is along a sidewall of the interconnect structure. The dielectric material extends to within cracks in the sidewall of the dielectric structure.

IPC Classes  ?

  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

24.

FORMATION AND IN-SITU ETCHING PROCESSES FOR METAL LAYERS

      
Application Number 18765453
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lin, Po-Yu
  • Chou, Chi-Yu
  • Lee, Hsien-Ming
  • Yang, Huai-Tei
  • Wang, Chun-Chieh
  • Pai, Yueh-Ching
  • Yang, Chi-Jen
  • Tang, Tsung-Ta
  • Wang, Yi-Ting

Abstract

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 29/49 - Metal-insulator semiconductor electrodes

25.

MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE

      
Application Number 18763040
Status Pending
Filing Date 2024-07-03
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor Song, Ming Yuan

Abstract

Some embodiments relate to a probabilistic random number generator. The probabilistic random number generator includes a memory cell comprising a magnetic tunnel junction (MTJ), and an access transistor coupled to the MTJ of the memory cell. A variable current source is coupled to the access transistor and is configured to provide a plurality of predetermined current pulse shapes, respectively, to the MTJ to generate a bit stream that includes a plurality of probabilistic random bits, respectively, from the MTJ. The predetermined current pulse shapes have different current amplitudes and/or pulse widths corresponding to different switching probabilities for the MTJ.

IPC Classes  ?

  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/80 - Constructional details

26.

METHOD OF FABRICATING PACKAGE STRUCTURE

      
Application Number 18766556
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lin, Yu-Sheng
  • Huang, Han-Hsiang
  • Chen, Chien-Sheng
  • Yeh, Shu-Shen
  • Jeng, Shin-Puu

Abstract

A package structure includes a circuit substrate, a semiconductor package, first bump structures and second bump structures. The semiconductor package is disposed on the circuit substrate, wherein the semiconductor package includes a center region and side regions surrounding the center region. The first bump structures are disposed on the center region of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate. The second bump structures are disposed on the side regions of the semiconductor package and electrically connecting the semiconductor package to the circuit substrate, wherein the first bump structures and the second bump structures have different heights and different shapes.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

27.

METHOD FOR DETECTING CONTACT FORCE OF PROBE CARD

      
Application Number 18765676
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Hsu, Ming-Cheng
  • Lin, Te-Kun
  • Tsai, Yu-Hsien
  • Su, Wen-Tsai

Abstract

A method for detecting a contact force of a probe card is provided. The method includes contacting a pressure film sensor with a plurality of needles over a lower surface of the probe card. The method includes detecting the contact force of the probe card via the pressure film sensor. The method also includes adjusting a position of a push base over an upper surface of the probe card based on the detected contact force of the pressure film sensor.

IPC Classes  ?

  • G01R 1/073 - Multiple probes
  • G01L 5/00 - Apparatus for, or methods of, measuring force, work, mechanical power, or torque, specially adapted for specific purposes
  • G01S 17/08 - Systems determining position data of a target for measuring distance only

28.

Self-Aligned Contact Hard Mask Structure of Semiconductor Device and Method of Forming Same

      
Application Number 18766767
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Ho, Tsai-Jung
  • Lee, Tze-Liang

Abstract

A device includes a substrate including an active region, a gate stack over the active region, and a hard mask over the gate stack. The hard mask includes a capping layer, a buttress layer extending along sidewalls and a bottom of the capping layer, and a liner layer extending along sidewalls and a bottom of the buttress layer. The buttress layer includes a metal oxide material or a metal nitride material.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/8234 - MIS technology
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors

29.

ARCING PROTECTION METHOD, PROCESSING TOOL AND FABRICATION SYSTEM

      
Application Number 18765661
Status Pending
Filing Date 2024-07-08
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Tsai, Wun-Kai
  • Liang, Wen-Che
  • Li, Chao-Keng
  • Xu, Zheng-Jie
  • Chang, Chih-Kuo
  • Li, Sing-Tsung
  • Wu, Feng-Kuang
  • Liu, Hsu-Shui

Abstract

A fabrication system for fabricating IC is provided. A processing tool includes a RF sensor. The RF sensor wirelessly detects intensity of a RF signal. A computation device extracts statistical characteristics with a sampling rate. When the detected intensity of the RF signal exceeds a threshold value or a threshold range, a fault detection and classification (FDC) system notifies the processing tool to adjust the RF signal or stop tool to check parts damage.

IPC Classes  ?

  • H01J 37/32 - Gas-filled discharge tubes
  • C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating using electric discharges using radio frequency discharges
  • G05B 19/4065 - Monitoring tool breakage, life or condition
  • H01J 37/244 - Detectors; Associated components or circuits therefor
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

30.

BUMP INTEGRATION WITH REDISTRIBUTION LAYER

      
Application Number 18763481
Status Pending
Filing Date 2024-07-03
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Yang, Ting-Li
  • Tsai, Po-Hao
  • Hsiao, Ching-Wen
  • Shue, Hong-Seng
  • Cheng, Ming-Da

Abstract

A method of forming a semiconductor device includes: forming an interconnect structure over a substrate; forming a first passivation layer over the interconnect structure; forming a first conductive feature over the first passivation layer and electrically coupled to the interconnect structure; conformally forming a second passivation layer over the first conductive feature and the first passivation layer; forming a dielectric layer over the second passivation layer; and forming a first bump via and a first conductive bump over and electrically coupled to the first conductive feature, where the first bump via is between the first conductive bump and the first conductive feature, where the first bump via extends into the dielectric layer, through the second passivation layer, and contacts the first conductive feature, where the first conductive bump is over the dielectric layer and electrically coupled to the first bump via.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure

31.

MEMORY DEVICE

      
Application Number 18766701
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Young, Bo-Feng
  • Yeong, Sai-Hooi
  • Lu, Shih-Lien Linus
  • Huang, Chia-En
  • Wang, Yih
  • Lin, Yu-Ming

Abstract

Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.

IPC Classes  ?

  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

32.

SEMICONDUCTOR DEVICE WITH TWO-DIMENSIONAL MATERIALS AND FORMING METHOD THEREOF

      
Application Number 18308106
Status Pending
Filing Date 2023-04-27
First Publication Date 2024-10-31
Owner
  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
  • National Yang Ming Chiao Tung University (Taiwan, Province of China)
Inventor
  • Chang, Shu-Jui
  • Wang, Shin-Yuan
  • Huang, Yu-Che
  • Chien, Chao-Hsin
  • Hu, Chenming

Abstract

A method includes following steps. A single-crystalline two-dimensional (2D) semiconductor layer is formed over a substrate. A single-crystalline 2D material layer is epitaxially grown on the single-crystalline 2D semiconductor layer. The single-crystalline 2D material layer is lattice-matched with the single-crystalline 2D semiconductor layer. A semiconductor device is over the single-crystalline 2D semiconductor layer.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • C30B 25/18 - Epitaxial-layer growth characterised by the substrate
  • C30B 29/40 - AIIIBV compounds
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes

33.

PACKAGE PICK-UP APPARATUS AND METHODS FOR USING THE SAME

      
Application Number 18307036
Status Pending
Filing Date 2023-04-26
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company Limited (Taiwan, Province of China)
Inventor
  • Chen, Hsin Liang
  • Hsieh, Ching-Hua
  • Lin, Hsiu-Jen
  • Kuo, Hsuan-Ting
  • Chen, Wei-Yu
  • Wong, Cheng-Shiuan

Abstract

An adhesion film with a plurality of semiconductor packages thereupon may be positioned on a pedestal including an enclosure and having a perforated top surface, a first support ring located at a periphery of the perforated top surface, and a second support ring laterally surrounding the first support ring. A first semiconductor package overlaps segments of the first support ring at a plurality of overlap areas in a top-down view, and does not contact the second support ring in the top-down view. A vacuum suction may be applied to a volume within the enclosure and to a gap which is vertically bounded by a bottom surface of the adhesion film and is laterally bounded by the first support ring while holding the first semiconductor package stationary. A portion of the adhesion film underlying the first semiconductor package is peeled off a bottom surface of the first semiconductor package.

IPC Classes  ?

  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

34.

PHOTON SOURCE AND OPTICAL COMPUTING ARCHITECTURE

      
Application Number 18308794
Status Pending
Filing Date 2023-04-28
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lu, Chih-Hsin
  • Lin, Chia-Chia
  • Tsai, Chung-Hao
  • Wang, Chuei-Tang
  • Yu, Chen-Hua

Abstract

A photonic integrated circuit (PIC) with a first structure of a ordinary optical material is enhanced with a second structure of a nonlinear optical material. The second structure provides or enhances nonlinear optical effects within the PIC. The first structure and the second structure may be in distinct layers. The first structure may be directly over and in contact with the second structure. Alternatively, the first structure and the second structures may be evanescently coupled while being vertically separated by a layer of cladding material. Lateral spacing may be used in combination with vertically spacing to precisely control a degree coupling between the first structure and the second structure.

IPC Classes  ?

  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/13 - Integrated optical circuits characterised by the manufacturing method

35.

SEMICONDUCTOR DEVICE HAVING METALLIZATION LAYER WITH LOW CAPACITANCE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18764971
Status Pending
Filing Date 2024-07-05
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Lee, Cheng-Chin
  • Lo, Ting-Ya
  • Teng, Chi-Lin
  • Tsai, Cherng-Shiaw
  • Lee, Shao-Kuan
  • Yang, Kuang-Wei
  • Liu, Gary
  • Huang, Hsin-Yen
  • Chang, Hsiao-Kang
  • Shue, Shau-Lin

Abstract

A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

36.

SEMICONDUCTOR DEVICES

      
Application Number 18764973
Status Pending
Filing Date 2024-07-05
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Wu, Shih-Chieh
  • Wu, Pang-Chi
  • Chao, Kuo-Yi
  • Wang, Mei-Yun
  • Liao, Hsien-Huang
  • Hsieh, Tung-Heng
  • Young, Bao-Ru

Abstract

In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

IPC Classes  ?

  • H01L 21/8234 - MIS technology
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 29/66 - Types of semiconductor device

37.

HEATING MODULE AND PROGRAM CONTROL METHOD FOR PUMPING LINE OF SEMICONDUCTOR PROCESSING TOOL

      
Application Number 18141073
Status Pending
Filing Date 2023-04-28
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company (Taiwan, Province of China)
Inventor
  • Yang, Sheng-Chun
  • Lin, Yi-Ming
  • Chang, Chun
  • Liu, Che Kang
  • Jan, Kaijun
  • Zheng, Xuan-Yang
  • Chao, Tzu-Chuan
  • Wu, Weigang
  • Wang, Chih-Yuan
  • Wang, Ren-Jyue

Abstract

A semiconductor processing tool includes: a process chamber into which a semiconductor wafer is loaded; a support for securing the wafer loaded into the chamber tool; an inlet which introduces a first gas into the chamber for processing the wafer; and an exhaust system that exhausts gas from the chamber. The exhaust system includes: a first line coupled to the chamber to exhaust gas from the chamber; and a pump to draw gas through the first line from the chamber. The tool further includes a heating module having: a second line coupled to the first and a supply of a second gas, the second gas being flowed through the second line from the supply into the first line; and a heating element contained in the second line, the heating element heating the second gas in the second line before the second gas is flowed into the first line.

IPC Classes  ?

  • C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating
  • C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
  • C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
  • C23C 16/52 - Controlling or regulating the coating process

38.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18308912
Status Pending
Filing Date 2023-04-28
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Chun-Yuan
  • Chang, Lo-Heng
  • Su, Huan-Chieh
  • Wang, Chih-Hao
  • Wu, Szu-Chien

Abstract

A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

39.

VERTICALLY STACKED LIGHT SENSORS

      
Application Number 18363950
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Hsiang-Lin
  • Chu, Yi-Shin
  • Liao, Yin-Kai
  • Jiang, Sin-Yi
  • Chen, Sung-Wen Huang

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor structure including a first substrate comprising a first semiconductor material. A first light sensor is disposed within the first substrate. The first light sensor is configured to absorb electromagnetic radiation within a first wavelength range. A second light sensor is disposed within an absorption structure underlying the first substrate. The second light sensor is configured to absorb electromagnetic radiation within a second wavelength range different from the first wavelength range. The absorption structure underlies the first light sensor and comprises a second semiconductor material different from the first semiconductor material.

IPC Classes  ?

40.

SEMICONDUCTOR DIE HAVING EDGE WITH MULTIPLE GRADIENTS

      
Application Number 18765006
Status Pending
Filing Date 2024-07-05
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Tang, Yu-Sheng
  • Chang, Fu-Chen
  • Huang, Cheng-Lin
  • Chen, Wen-Ming
  • Lo, Chun-Yen
  • Liu, Kuo-Chio

Abstract

A semiconductor die is provided. The semiconductor die includes a substrate having a front surface, a rear surface opposite to the front surface, and a sidewall connected between the front surface and the rear surface. The sidewall includes a first primary segment immediately connected to the front surface, a second primary segment immediately connected to the rear surface, and a middle segment between the first primary segment and the second primary segment. The slope of the second primary segment is less than the slope of the first primary segment, and the slope of the middle segment is less than the slope of the second primary segment. Each of the first primary segment, the second primary segment, and the middle segment is a flat surface having a slope greater than 0 degrees relative to a line parallel to the front surface of the substrate.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices having separate containers

41.

DROPLET GENERATOR ASSEMBLY AND METHOD OF REPLACING COMPONENTS

      
Application Number 18769912
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Sun, Yu-Kuang
  • Tsai, Ming-Hsun
  • Cheng, Wei-Shin
  • Lai, Cheng-Hao
  • Chen, Hsin-Feng
  • Cheng, Chiao-Hua
  • Wu, Cheng-Hsuan
  • Lo, Yu-Fa
  • Lu, Jou-Hsuan
  • Chien, Shang-Chieh
  • Chen, Li-Jui
  • Liu, Heng-Hsin

Abstract

The present disclosure is directed to a modularized vessel droplet generator assembly (MGDVA) including a droplet generator assembly (DGA). Under a normal operation, the liquid fuel moves along an operation pathway extending through the DGA to eject or discharge the liquid fuel (e.g., liquid tin) from a nozzle of the DGA into a vacuum chamber. The liquid fuel in the vacuum chamber is then exposed to a laser generating an extreme ultra-violet (EUV) light. Under a service operation, the operation pathway is closed and a service pathway extending through the DGA is opened. A gas is introduced into the service pathway forming a gas-liquid interface between the gas and the liquid fuel. The gas-liquid interface is driven to an isolation valve directly adjacent to the DGA. In other words, the gas pushes back the liquid fuel to the isolation valve. Once the gas-liquid interface reaches the isolation valve, the isolation valve is closed isolating the DGA from the liquid fuel.

IPC Classes  ?

  • H05G 2/00 - Apparatus or processes specially adapted for producing X-rays, not involving X-ray tubes, e.g. involving generation of a plasma
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G05D 23/19 - Control of temperature characterised by the use of electric means

42.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

      
Application Number 18766899
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Young, Bo-Feng
  • Yeong, Sai-Hooi
  • Chui, Chi On
  • Lin, Yu-Ming

Abstract

3D-NOR memory array devices and methods of manufacture are disclosed herein. A method includes forming a multi-layer stack over a substrate by forming alternating layers of an isolation material and a dummy material. An array of dummy nanostructures is formed in a channel region of the multi-layer stack by performing a wire release process. Once the nanostructures have been formed, a single layer of an oxide semiconductor material is deposited over and surrounds the dummy nanostructures. A memory film is then deposited over the oxide semiconductor material and a conductive wrap-around structure is formed over the memory film. Source/bit line structures may be formed by replacing the layers of the dummy material outside of the channel region with a metal fill material. A staircase conductor structure can be formed the source/bit line structures in a region of the multi-layer stack adjacent the memory array.

IPC Classes  ?

  • H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 29/786 - Thin-film transistors
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 99/00 - Subject matter not provided for in other groups of this subclass

43.

ION IMPLANT PROCESS FOR DEFECT ELIMINATION IN METAL LAYER PLANARIZATION

      
Application Number 18767722
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Chia-Cheng
  • Chang, Tang-Kuei
  • Yeo, Yee-Chia
  • Chang, Huicheng
  • Liang, Wei-Wei
  • Cui, Ji
  • Huang, Fu-Ming
  • Chen, Kei-Wei
  • Chen, Liang-Yin

Abstract

The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/321 - After-treatment
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/45 - Ohmic electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

44.

INTEGRATED OPTICAL DEVICES AND METHODS OF FORMING THE SAME

      
Application Number 18767949
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Kuo, Feng-Wei
  • Liao, Wen-Shiang

Abstract

An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.

IPC Classes  ?

  • G02B 6/124 - Geodesic lenses or integrated gratings
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/13 - Integrated optical circuits characterised by the manufacturing method

45.

P-Type FiNFET as a Radio-Frequency Device and Method Forming Same

      
Application Number 18770088
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Hsiao, Ru-Shang
  • Su, Ching-Hwanq
  • Su, Pin Chia
  • Lu, Ying Hsin
  • Wang, Ling-Sung

Abstract

A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/8234 - MIS technology
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

46.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING

      
Application Number 18771181
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Chien-Hsun
  • Liang, Yu-Min
  • Wang, Yen-Ping
  • Wu, Jiun Yi
  • Yu, Chen-Hua
  • Wu, Kai-Chiang

Abstract

Interconnect devices, packaged semiconductor devices and methods are disclosed herein that are directed towards embedding a local silicon interconnect (LSI) device and through substrate vias (TSVs) into system on integrated substrate (SoIS) technology with a compact package structure. The LSI device may be embedded into SoIS technology with through substrate via integration to provide die-to-die FL connection arrangement for super large integrated Fan-Out (InFO) for SBT technology in a SoIS device. Furthermore, the TSV connection layer may be formed using lithographic or photoresist-defined vias to provide eLSI P/G out to a ball-grid-array (BGA) connection interface.

IPC Classes  ?

  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

47.

NMOS and PMOS Transistor Gates with Hafnium Oxide Layers and Lanthanum Oxide Layers

      
Application Number 18770052
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • More, Shahaji B.
  • Pan, Zheng-Yang
  • Chang, Shih-Chieh
  • Wang, Chun Chieh

Abstract

A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

IPC Classes  ?

  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/8234 - MIS technology
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

48.

SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED AIR SPACERS

      
Application Number 18771597
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Su, Huan-Chieh
  • You, Jia-Chuan
  • Chuang, Cheng-Chi
  • Wang, Chih-Hao

Abstract

A semiconductor device includes a multi-pattern gate (MPG) structure having a gate structure height GSH1 and a gate structure width GSW1; a first sidewall structure on a first vertical side of the MPG structure, and a second sidewall structure on a second vertical side of the MPG structure; a first air spacer adjacent the first sidewall structure, and a second air spacer adjacent the second sidewall structure, each of the first air spacer and the second air spacer having a height ASH1 and a width ASW1; and a first cap structure sealing the first air spacer, and a second cap structure sealing the second air spacer, each of the first cap structure and the second cap structure having a height CH1 and a width CW1. A first expression ASH1>GSH1, a second expression CW1>ASW1, and a third expression GSW1>CW1 are each satisfied.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/8234 - MIS technology
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

49.

Reinforcing Package Using Reinforcing Patches

      
Application Number 18770022
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Hsu, Chia-Kuei
  • Yew, Ming-Chih
  • Lin, Po-Yao
  • Chen, Shuo-Mao
  • Hsu, Feng-Cheng
  • Jeng, Shin-Puu

Abstract

A method includes forming a redistribution structure, which formation process includes forming a plurality of dielectric layers over a carrier, forming a plurality of redistribution lines extending into the plurality of dielectric layers, and forming a reinforcing patch over the carrier. The method further includes bonding a package component to the redistribution structure, with the package component having a peripheral region overlapping a portion of the reinforcing patch. And de-bonding the redistribution structure and the first package component from the carrier.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

50.

APPARATUSES AND SYSTEMS FOR ELECTROPLATING

      
Application Number 18771368
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Hou, Kuo-Lung
  • Lin, Ming-Hsien
  • Kuo, Che-I
  • Lu, Yung Hsin

Abstract

An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • C25D 3/38 - Electroplating; Baths therefor from solutions of copper
  • C25D 5/02 - Electroplating of selected surface areas

51.

SOURCE/DRAIN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES

      
Application Number 18770367
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor More, Shahaji B.

Abstract

The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

IPC Classes  ?

  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

52.

SEMICONDUCTOR STRUCTURE HAVING DIELECTRIC-ON-DIELECTRIC STRUCTURE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE

      
Application Number 18770120
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Lee, Cheng-Chin
  • Lee, Shao-Kuan
  • Huang, Hsin-Yen
  • Chang, Hsiao-Kang
  • Shue, Shau-Lin

Abstract

A semiconductor structure includes a substrate with a conductive structure thereon, a first dielectric layer, a conductive feature and a second dielectric layer. The first dielectric layer is disposed on the substrate. The conductive feature is formed in the first dielectric layer and is electrically connected to the conductive structure. The second dielectric layer is formed on the first dielectric layer and is disposed adjacent to the conductive feature. The first dielectric layer and the second dielectric layer are made of different materials.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

53.

SEMICONDUCTOR DEVICE WITH FUNNEL SHAPE SPACER AND METHODS OF FORMING THE SAME

      
Application Number 18770349
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Yang, Cheng-Yu
  • Chen, Yen-Ting
  • Lee, Wei-Yang
  • Yang, Fu-Kai
  • Chen, Yen-Ming

Abstract

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

IPC Classes  ?

  • H01L 21/8234 - MIS technology
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

54.

SEMICONDUCTOR STRUCTURE

      
Application Number 18771434
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chang, Jung-Hung
  • Chang, Lo Heng
  • Lin, Zhi-Chang
  • Chen, Shih-Cheng
  • Yao, Chien-Ning
  • Chiang, Kuo-Cheng
  • Wang, Chih-Hao

Abstract

A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures, a gate stack surrounding the nanostructures, a first source/drain feature and a second source/drain feature adjoining a first side and a second side of the plurality of nanostructures, respectively, a first contact plug under and electrically connected to the first source/drain feature, a second contact plug over and electrically connected to the second source/drain feature, and an insulating layer surrounding the second contact plug and covering a top surface of the first source/drain feature.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 21/8234 - MIS technology
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

55.

SEMICONDUCTOR DEVICE GATE STRUCTURES

      
Application Number 18771674
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • More, Shahaji B.
  • Savant, Chandrashekhar Prakash

Abstract

In an embodiment, a device includes: a gate dielectric over a substrate; a gate electrode over the gate dielectric, the gate electrode including: a work function tuning layer over the gate dielectric; a glue layer over the work function tuning layer; a fill layer over the glue layer; and a void defined by inner surfaces of at least one of the fill layer, the glue layer, and the work function tuning layer, a material of the gate electrode at the inner surfaces including a work function tuning element.

IPC Classes  ?

  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/66 - Types of semiconductor device

56.

SEMICONDUCTOR STRUCTURE

      
Application Number 18767188
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Cheng, Kuan-Hao
  • Lee, Wei-Yang
  • Chiu, Tzu-Hua
  • Fan, Wei-Han
  • Lin, Po-Yu
  • Lin, Chia-Pin

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first nanostructure stacked over and spaced apart from a second nanostructure, a gate stack wrapping around the first nanostructure and the second nanostructure, a source/drain feature adjoining the first nanostructure and the second nanostructure, and a first inner spacer layer interposing the gate stack and the source/drain feature and interposing the first nanostructure and the second nanostructure. A dopant in the source/drain feature has a first concentration at an interface between the first inner spacer layer and the source/drain feature and a second concentration at a first distance away from the interface. The first concentration is higher than the second concentration.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors

57.

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Test and Diagnosis

      
Application Number 18767186
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chandra, Anshuman
  • Goel, Sandeep Kumar

Abstract

Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

IPC Classes  ?

58.

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

      
Application Number 18769121
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lin, Meng-Han
  • Huang, Chia-En

Abstract

A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

59.

PARTICLE IMAGE VELOCIMETRY OF EXTREME ULTRAVIOLET LITHOGRAPHY SYSTEMS

      
Application Number 18770357
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lai, En Hao
  • Yang, Chi
  • Chien, Shang-Chieh
  • Chen, Li-Jui
  • Cheng, Po-Chung

Abstract

A method includes irradiating a target droplet in an extreme ultraviolet (EUV) light source of an extreme ultraviolet lithography tool with non-ionizing light from a droplet illumination module. The method further includes detecting light reflected and/or scattered by the target droplet, and performing particle image velocimetry, based on the detected light, to determine a velocity of the target droplet. The method also includes adjusting a time delay between a generation of the target droplet and a generation of an excitation laser beam based on the velocity of the target droplet.

IPC Classes  ?

  • G01P 5/20 - Measuring speed of fluids, e.g. of air stream; Measuring speed of bodies relative to fluids, e.g. of ship, of aircraft by measuring the time taken by the fluid to traverse a fixed distance using particles entrained by a fluid stream
  • G02B 27/00 - Optical systems or apparatus not provided for by any of the groups ,
  • G03F 1/42 - Alignment or registration features, e.g. alignment marks on the mask substrates
  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G03F 7/20 - Exposure; Apparatus therefor
  • H05G 2/00 - Apparatus or processes specially adapted for producing X-rays, not involving X-ray tubes, e.g. involving generation of a plasma

60.

METHOD AND APPARATUS FOR REDUCING LIGHT LEAKAGE AT MEMORY NODES IN CMOS IMAGE SENSORS

      
Application Number 18770566
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Tseng, Chih-Yu
  • Chen, Ming-Hsien

Abstract

Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H04N 25/53 - Control of the integration time
  • H04N 25/709 - Circuitry for control of the power supply
  • H04N 25/71 - Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N 25/711 - Time delay and integration [TDI] registers; TDI shift registers
  • H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

61.

MULTIFUNCTIONAL COLLIMATOR FOR CONTACT IMAGE SENSORS

      
Application Number 18770562
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Hsin-Yu
  • Li, Chun-Peng
  • Hung, Chia-Chun
  • Hu, Ching-Hsiang
  • Wu, Wei-Ding
  • Weng, Jui-Chun
  • Chiang, Ji-Hong
  • Liu, Yen Chiang
  • Chiou, Jiun-Jie
  • Tu, Li-Yang
  • Li, Jia-Syuan
  • Jhang, You-Cheng
  • Chen, Shin-Hua
  • Sanagavarapu, Lavanya
  • Pan, Han-Zong
  • Hsu, Hsi-Cheng

Abstract

Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×1019 per cubic centimeter (cm−3) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.

IPC Classes  ?

62.

SEMICONDUCTOR DEVICE WITH FIN STRUCTURES

      
Application Number 18767168
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Keng, Wen-Chun
  • Lin, Yu-Kuan
  • Yang, Chang-Ta
  • Wang, Ping-Wei

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure, a second fin structure, and a third fin structure over the substrate. Tops of the second fin structure and the third fin structure are at different height levels. The semiconductor device structure also includes a first epitaxial structure extending across sidewalls of the first fin structure and the second fin structure and a second epitaxial structure on the third fin structure. The first epitaxial structure is closer to the substrate than the second epitaxial structure.

IPC Classes  ?

  • H01L 21/8234 - MIS technology
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/311 - Etching the insulating layers
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

63.

INTERCONNECT SYSTEM WITH IMPROVED LOW-K DIELECTRICS

      
Application Number 18771426
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Liou, Joung-Wei
  • Ke, Yu Lun
  • Chiu, Yi-Wei

Abstract

Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si—O—Si bonds, such as (CH3O)3—Si—O—Si—(CH3O)3) and (CH3)3—Si—O—Si—(CH3)3 may be used.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

64.

SYSTEM AND METHOD FOR MONITORING VACUUM VALVE CLOSING CONDITION IN VACUUM PROCESSING SYSTEM

      
Application Number 18770570
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor Chiu, Pei Cheng

Abstract

A system and method for cleaning and inspecting ring frames is disclosed here. In one embodiment, a vacuum valve comprising at least one sealing O-ring; and a pressure monitoring tape on a mating surface on a vacuum processing chamber, wherein the pressure monitoring tape is configured to perform a pressure profile mapping between the mating surface on the vacuum processing chamber and a surface of the at least one sealing O-ring on the vacuum valve to determine a closing condition of the vacuum valve.

IPC Classes  ?

  • G01M 3/28 - Investigating fluid tightness of structures by using fluid or vacuum by measuring rate of loss or gain of fluid, e.g. by pressure-responsive devices, by flow detectors for valves
  • G01M 3/02 - Investigating fluid tightness of structures by using fluid or vacuum
  • G01M 13/00 - Testing of machine parts
  • G01M 13/003 - Machine valves
  • G01M 13/005 - Sealing rings
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

65.

COMPOSITE WORK FUNCTION LAYER FORMATION USING SAME WORK FUNCTION MATERIAL

      
Application Number 18767174
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Lee, Hsin-Yi
  • Hung, Cheng-Lung
  • Chui, Chi On

Abstract

A method includes forming a gate dielectric layer on a semiconductor region, and depositing a first aluminum-containing work function layer using a first aluminum-containing precursor. The first aluminum-containing work function layer is over the gate dielectric layer. A second aluminum-containing work function layer is deposited using a second aluminum-containing precursor, which is different from the first aluminum-containing precursor. The second aluminum-containing work function layer is deposited over the first aluminum-containing work function layer. A conductive region is formed over the second aluminum-containing work function layer.

IPC Classes  ?

  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/8234 - MIS technology
  • H01L 29/40 - Electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

66.

Cell Manufacturing

      
Application Number 18768467
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor Liaw, Jhon Jhy

Abstract

A semiconductor device includes a first Static Random Access Memory (SRAM) array including a first SRAM cell and a second SRAM array including a second SRAM cell. The first SRAM cell includes a first pull-down (PD) device including a single fin N-type FinFET. The single fin N-type FinFET includes a first gate dielectric having a first thickness. The second SRAM cell includes a second PD device including a multiple fin N-type FinFET. The multiple fin N-type FinFET includes a second gate dielectric having a second thickness. The first thickness is greater than the second thickness.

IPC Classes  ?

  • H10B 10/00 - Static random access memory [SRAM] devices
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

67.

Epitaxies of a Chemical Compound Semiconductor

      
Application Number 18770783
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner
  • Taiwan Semiconductor Manufacturing Company Limited (Taiwan, Province of China)
  • National Chiao-Tung University (Taiwan, Province of China)
Inventor
  • Yu, Hung-Wei
  • Chang, Yi
  • Wang, Tsun-Ming

Abstract

Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

68.

ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS

      
Application Number 18770552
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Yeh, Yu-Hung
  • Lin, Wun-Jie
  • Lee, Jam-Wem

Abstract

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

IPC Classes  ?

  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

69.

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18768002
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Taiwan, Province of China)
Inventor
  • Li, Shu-Wei
  • Chan, Yu-Chen
  • Lu, Meng-Pei
  • Yang, Shin-Yi
  • Lee, Ming-Han

Abstract

A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric structure disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure. The interconnect structure laterally contacts the 2D conductive structure.

IPC Classes  ?

  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

70.

SEMICONDUCTOR DEVICE

      
Application Number 18768003
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Taiwan, Province of China)
Inventor
  • Ting, Kuo-Chiang
  • Wu, Chi-Hsi
  • Hou, Shang-Yun
  • Yu, Tu-Hao
  • Hsu, Chia-Hao
  • Lin, Pin-Tso
  • Chen, Chia-Hsin

Abstract

A semiconductor device includes a dielectric interposer, a first RDL, a second RDL, and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first RDL is disposed over the first surface of the dielectric interposer. The second RDL is disposed over the second surface of the dielectric interposer. The conductive structures are disposed through the dielectric interposer and directly contact the dielectric interposer. The conductive structures are electrically connected to the first RDL and the second RDL. Each of the conductive structures has a tapered profile. A minimum width of each of the conductive structures is proximal to the first RDL, and a maximum width of each of the conductive structures is proximal to the second RDL.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
  • H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement

71.

SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION

      
Application Number 18768449
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Cui, Ji
  • Chen, Chih Hung
  • Chen, Liang-Guang
  • Chen, Kei-Wei

Abstract

A semiconductor processing tool includes a cleaning chamber configured to perform a post-chemical mechanical polishing/planarization (post-CMP) cleaning operation in an oxygen-free (or in a near oxygen-free) manner. An inert gas may be provided into the cleaning chamber to remove oxygen from the cleaning chamber such that the post-CMP cleaning operation may be performed in an oxygen-free (or in a near oxygen-free) environment. In this way, the post-CMP cleaning operation may be performed in an environment that may reduce oxygen-causing corrosion of metallization layers and/or metallization structures on and/or in the semiconductor wafer, which may increase semiconductor processing yield, may decrease semiconductor processing defects, and/or may increase semiconductor processing quality, among other examples.

IPC Classes  ?

  • H01L 21/321 - After-treatment
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

72.

PARASITIC CAPACITANCE REDUCTION

      
Application Number 18769781
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Wang, Jia-Heng
  • Chen, Chun-Han
  • Wu, I-Wen
  • Lee, Chen-Ming
  • Yang, Fu-Kai
  • Wang, Mei-Yun

Abstract

The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device according to one embodiment of the present disclosure includes a first fin-shaped structure extending lengthwise along a first direction over a substrate, a first epitaxial feature over a source/drain region of the first fin-shaped structure, a gate structure disposed over a channel region of the first fin-shaped structure and extending along a second direction perpendicular to the first direction, and a source/drain contact over the first epitaxial feature. The bottom surface of the gate structure is closer to the substrate than a bottom surface of the source/drain contact.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/8234 - MIS technology
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

73.

Two-Step Charge-Based Capacitor Measurement

      
Application Number 18767126
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Tai-Yi
  • Yang, Chung-Chieh
  • Chang, Chih-Chiang
  • Lu, Chung-Ting

Abstract

Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.

IPC Classes  ?

  • G01R 27/26 - Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants
  • G01R 31/26 - Testing of individual semiconductor devices
  • G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
  • H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

74.

SEMICONDUCTOR DEVICE WITH VARYING GATE DIMENSIONS AND METHODS OF FORMING THE SAME

      
Application Number 18769548
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Huang, Guan-Wei
  • Lu, Yu-Shan
  • Wu, Yu-Bey
  • Kuo, Jiun-Ming
  • Peng, Yuan-Ching

Abstract

A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

IPC Classes  ?

  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors

75.

ISOLATION STRUCTURES

      
Application Number 18767134
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Lin, Ta-Chun
  • Pan, Kuo-Hua
  • Liaw, Jhon Jhy

Abstract

A semiconductor structure includes a first well doped with a first dopant and a second well doped with a second dopant different from the first dopant. From a top view, the first well includes a first base extending lengthwise along a direction, and a first letter-shaped portion and a second letter-shaped portion connected to the first base. From the top view, the second well includes a second base extending lengthwise along the direction and a third letter-shaped portion connected to the second base. The third letter-shaped portion extends into the first well and is keyed to the first letter-shaped portion and the second letter-shaped portion.

IPC Classes  ?

  • H01L 21/762 - Dielectric regions
  • G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
  • H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

76.

ATOMIC LAYER DEPOSITION BONDING LAYER FOR JOINING TWO SEMICONDUCTOR DEVICES

      
Application Number 18768426
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Cheng, Kuang-Wei
  • Ni, Chyi-Tsong

Abstract

A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

77.

TSV STRUCTURE AND METHOD FORMING SAME

      
Application Number 18768673
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chung, Ming-Tsu
  • Yang, Ku-Feng
  • Wu, Tsang-Jiuh
  • Chiou, Wen-Chih
  • Yu, Chen-Hua

Abstract

A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

78.

SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME

      
Application Number 18770756
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Yu, Jia-Ni
  • Chu, Lung-Kun
  • Hsu, Chung-Wei
  • Wang, Chih-Hao
  • Chiang, Kuo-Cheng
  • Cheng, Kuan-Lun
  • Huang, Mao-Lin

Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first gate electrode layer, a second gate electrode layer disposed over and aligned with the first gate electrode layer, and a gate isolation structure disposed between the first gate electrode layer and the second gate electrode layer. The gate isolation structure includes a first surface and a second surface opposite the first surface. At least a portion of the first surface is in contact with the first gate electrode layer. The second surface includes a first material and a second material different from the first material, and at least a portion of the second surface is in contact with the second gate electrode layer.

IPC Classes  ?

  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 21/8234 - MIS technology
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/786 - Thin-film transistors

79.

INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT

      
Application Number 18768895
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Yang, Jung-Chan
  • Chiang, Ting-Wei
  • Huang, Cheng-I
  • Zhuang, Hui-Zhong
  • Lu, Chi-Yu
  • Rusu, Stefan

Abstract

An integrated circuit structure includes a first and second power rail on a first level, a first and second set of conductive structures on a second level and a first, second and third conductive structure on a third level. The first set of conductive structures is over the first power rail. The second set of conductive structures is over the second power rail. The first conductive structure overlaps a first conductive structure of the first set of conductive structures and a first conductive structure of the second set of conductive structures. The second conductive structure overlaps a second conductive structure of the first set of conductive structures and a second conductive structure of the second set of conductive structures. The third conductive structure overlaps a third conductive structure of the first set of conductive structures and a third conductive structure of the second set of conductive structures.

IPC Classes  ?

  • G06F 30/394 - Routing
  • H01L 21/76 - Making of isolation regions between components
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H03K 19/094 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors

80.

Work Function Layers For Transistor Gate Electrodes

      
Application Number 18767571
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Cheng, Chung-Liang
  • Fang, Ziwei
  • Wu, Chun-I
  • Chao, Huang-Lin

Abstract

The embodiments described herein are directed to a method for the fabrication of transistors with aluminum-free n-type work function layers as opposed to aluminum-based n-type work function layers. The method includes forming a channel portion disposed between spaced apart source/drain epitaxial layers and forming a gate stack on the channel portion, where forming the gate stack includes depositing a high-k dielectric layer on the channel portion and depositing a p-type work function layer on the dielectric layer. After depositing the p-type work function layer, forming without a vacuum break, an aluminum-free n-type work function layer on the p-type work function layer and depositing a metal on the aluminum-free n-type work function layer. The method further includes depositing an insulating layer to surround the spaced apart source/drain epitaxial layers and the gate stack.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/8234 - MIS technology
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

81.

INTEGRATED CIRCUIT FEATURES WITH OBTUSE ANGLES AND METHOD OF FORMING SAME

      
Application Number 18768621
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chung, Shu-Wei
  • Wang, Yen-Sen

Abstract

A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • G06F 30/394 - Routing
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

82.

FINFET PITCH SCALING

      
Application Number 18768881
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Pan, Kuan-Ting
  • Jhan, Yi-Ruei
  • Chiang, Kuo-Cheng
  • Wang, Chih-Hao

Abstract

According to one example, a semiconductor structure includes a fin-shaped structure, a gate structure disposed over a region of the fin-shaped structure and having a sidewall including a lower portion and an upper portion above the lower portion, a first dielectric sidewall structure disposed along the lower portion of the sidewall, a second dielectric sidewall structure disposed along the upper portion of the sidewall and disposed on the first dielectric sidewall structure, and a source/drain feature disposed over a source/drain region of the fin-shaped structure and adjacent to the gate structure. The source/drain feature is separated from the gate structure by the first dielectric sidewall structure and the second dielectric sidewall structure. The first dielectric sidewall structure includes a different material than the second dielectric sidewall structure.

IPC Classes  ?

  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 21/8234 - MIS technology
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

83.

SYSTEMS AND METHODS FOR SHUTTERED WAFER CLEANING

      
Application Number 18767854
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Wang, Tsui-Wei
  • Tsai, Yung-Li
  • Peng, Chui-Ya

Abstract

In an embodiment, a system includes: a wafer support configured to secure a wafer; a nozzle configured to dispense a liquid or a gas on the wafer when the nozzle is in an active state of dispensing; a shutter configured to catch the liquid from the nozzle when the shutter is in a first position below the nozzle; and a shutter actuator configured to: move the shutter to the first position in response to the nozzle not being in an inactive state; move the shutter to a second position away from the first position in response to the nozzle being in the active state.

IPC Classes  ?

  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • B08B 15/04 - Preventing escape of dirt or fumes from the area where they are produced; Collecting or removing dirt or fumes from that area from a small area, e.g. a tool
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

84.

Semiconductor Device and Manufacturing Method Thereof

      
Application Number 18767601
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Savant, Chandrashekhar Prakash
  • Yu, Tien-Wei
  • Tsai, Chia-Ming

Abstract

The present disclosure describes method to form a semiconductor device with a diffusion barrier layer. The method includes forming a gate dielectric layer on a fin structure, forming a work function stack on the gate dielectric layer, reducing a carbon concentration in the work function stack, forming a barrier layer on the work function stack, and forming a metal layer over the barrier layer. The barrier layer blocks a diffusion of impurities into the work function stack, the gate dielectric layer, and the fin structure.

IPC Classes  ?

  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

85.

STRUCTURES AND METHODS FOR REDUCING PROCESS CHARGING DAMAGES

      
Application Number 18767848
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Kuan-Jung
  • Wang, Cheng-Hung
  • Lee, Tsung-Lin
  • Lin, Shiuan-Jeng
  • Lin, Chun-Ming
  • Chiang, Wen-Chih

Abstract

Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/311 - Etching the insulating layers
  • H01L 21/762 - Dielectric regions
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

86.

SIMULTANEOUS MULTI-BANDWIDTH OPTICAL INSPECTION OF SEMICONDUCTOR DEVICES

      
Application Number 18766961
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, LTD. (Taiwan, Province of China)
Inventor
  • Wang, Shih-Chang
  • Huang, Hsiu-Hui
  • Chung, Hung-Yi
  • Chen, Chien-Huei
  • Chen, Xiaomeng

Abstract

A method of qualifying semiconductor wafer processing includes: illuminating a semiconductor wafer simultaneously with source light having wavelengths in a plurality of wavebands, including at least a first waveband and a second waveband, the second waveband being different from the first waveband; separating light reflected from the semiconductor wafer as a result of said illuminating, the separating dividing the reflected light according to waveband; generating a first image of the semiconductor wafer based on reflected light separated into the first waveband; and, generating a second image of the semiconductor wafer base on reflected light separated into the second waveband.

IPC Classes  ?

  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined

87.

ECCENTRIC VIA STRUCTURES FOR STRESS REDUCTION

      
Application Number 18766974
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Yeh, Shu-Shen
  • Yang, Che-Chia
  • Hsu, Chia-Kuei
  • Lin, Po-Yao
  • Jeng, Shin-Puu
  • Lin, Chia-Hsiang

Abstract

A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

IPC Classes  ?

  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

88.

BACKSIDE STRUCTURE FOR IMAGE SENSOR

      
Application Number 18771095
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Kao, Min-Feng
  • Yaung, Dun-Nian
  • Liu, Jen-Cheng
  • Kuo, Wen-Chang
  • Huang, Shih-Han

Abstract

The present disclosure relates to an image sensor having an image sensing element surrounded by a BDTI structure, and an associated method of formation. In some embodiments, a first image sensing element and a second image sensing element are arranged next to one another within an image sensing die. A pixel dielectric stack is disposed along a back of the image sensing die overlying the image sensing elements. The pixel dielectric stack includes a first high-k dielectric layer and a second high-k dielectric layer. The BDTI structure is disposed between the first image sensing element and the second image sensing element and extends from the back of the image sensor die to a position within the image sensor die. The BDTI structure includes a trench filling layer surrounded by an isolation dielectric stack. The pixel dielectric stack has a composition different from that of the isolation dielectric stack.

IPC Classes  ?

89.

SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

      
Application Number 18771066
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Huang, Lin-Yu
  • Yu, Li-Zhen
  • Chuang, Cheng-Chi
  • Cheng, Kuan-Lun
  • Wang, Chih-Hao

Abstract

The semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, and a second dielectric feature. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

90.

METHODS OF MANUFACTURING SPIN-ORBIT-TORQUE MAGNETIC DEVICE

      
Application Number 18771255
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Lin, Shy-Jay
  • Song, Mingyuan

Abstract

A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer, as a magnetic free layer, disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. The first magnetic layer includes a lower magnetic layer, a middle layer made of non-magnetic layer and an upper magnetic layer.

IPC Classes  ?

91.

SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR

      
Application Number 18770140
Status Pending
Filing Date 2024-07-11
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Hong-Yang
  • Lin, Tian Sheng
  • Chiu, Yi-Cheng
  • Lin, Hung-Chou
  • Chen, Yi-Min
  • Wu, Kuo-Ming
  • Chung, Chiu-Hua

Abstract

A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate

92.

Semiconductor Package Including Neighboring Die Contact Seal Ring and Methods for Forming the Same

      
Application Number 18768084
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company Limited (Taiwan, Province of China)
Inventor
  • Chang, Jen-Yuan
  • Lai, Chia-Ping

Abstract

A semiconductor package includes: a first die; a second die stacked on an upper surface of the first die, the second die including a second semiconductor substrate and a second seal ring structure that extends along a perimeter of the second semiconductor substrate; a third die stacked on the upper surface of the first die, the third die including a third semiconductor substrate and a third seal ring structure that extends along a perimeter of the third semiconductor substrate; and a connection circuit that extends through the second seal ring structure and the third seal ring structure, in a lateral direction perpendicular to the stacking direction of the first die and the second die, to electrically connect the second semiconductor substrate and the third semiconductor substrate.

IPC Classes  ?

  • H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

93.

CAPPING STRUCTURES IN SEMICONDUCTOR DEVICES

      
Application Number 18771578
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chang, Po-Chin
  • Tsai, Ming-Huan
  • Lin, Li-Te
  • Lin, Pinyen

Abstract

A semiconductor device and methods of fabricating the same are disclosed. The method can include forming a fin structure on a substrate, forming a source/drain (S/D) region on the fin structure, forming a gate structure on the fin structure adjacent to the S/D region, and forming a capping structure on the gate structure. The forming the capping structure includes forming a conductive cap on the gate structure, forming a cap liner on the conductive cap, and forming a carbon-based cap on the cap liner. The method further includes forming a first contact structure on the S/D region, forming an insulating cap on the first contact structure, and forming a second contact structure on the conductive cap.

IPC Classes  ?

  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 21/8234 - MIS technology
  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/40 - Electrodes
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

94.

THREE DIMENSIONAL METAL INSULATOR METAL CAPACITOR STRUCTURE

      
Application Number 18769261
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Yeong, Sai-Hooi
  • Yu, Chia-Ta
  • Huang, Yen-Chieh

Abstract

The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a 3D metal insulator metal (MIM) capacitor structure with an increased capacitance per unit area in a semiconductor structure. The MIM structure includes a substrate, an oxide layer formed over the substrate, and a first metal layer formed over the oxide layer. The first metal layer includes a plurality of mandrels formed on a surface of the first metal layer. The MIM structure also includes a dielectric layer formed over the first metal layer and the plurality of mandrels, a second metal layer formed over on the dielectric layer, and one or more interconnect structures electrically connected to the first and second metal layers.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

95.

DUAL METAL CAPPED VIA CONTACT STRUCTURES FOR SEMICONDUCTOR DEVICES

      
Application Number 18769271
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Cheng, Chung-Liang
  • Fang, Ziwei

Abstract

The structure of a semiconductor device with dual metal capped via contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a source/drain (S/D) region and a gate structure on a fin structure, forming S/D and gate contact structures on the S/D region and the gate structure, respectively, forming first and second via contact structures on the S/D and gate contact structures, respectively, and forming first and second interconnect structures on the first and second via contact structures, respectively. The forming of the first and second via contact structures includes forming a first via contact plug interposed between first top and bottom metal capping layers and a second via contact plug interposed between second top and bottom metal capping layers, respectively.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 21/8234 - MIS technology
  • H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

96.

MULTI-LEVEL CELL DATA ENCODING

      
Application Number 18767098
Status Pending
Filing Date 2024-07-09
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Khwa, Win-San
  • Wu, Jui-Jen
  • Liu, Jen-Chieh
  • Chang, Meng-Fan

Abstract

A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

IPC Classes  ?

  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
  • G11C 11/54 - Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
  • G11C 29/44 - Indication or identification of errors, e.g. for repair

97.

METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION

      
Application Number 18771313
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan, Province of China)
Inventor
  • Wang, Yu-Sheng
  • Hung, Chi-Cheng
  • Kao, Chen-Yuan
  • Chiu, Yi-Wei
  • Ou Yang, Liang-Yueh
  • Pai, Yueh-Ching

Abstract

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
  • H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

98.

INTERFACE PROFILE CONTROL IN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES

      
Application Number 18771551
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Winnie Victoria Wei-Ning
  • Tsai, Pang-Yen
  • Okuno, Yasutoshi

Abstract

A method for reducing stress induced defects in heterogeneous epitaxial interfaces of a semiconductor device is disclosed. The method includes forming a fin structure with a fin base, a superlattice structure on the fin base, forming a polysilicon gate structure on the fin structure, forming a source/drain (S/D) opening within a portion of the fin structure uncovered by the polysilicon gate structure, modifying the first surfaces of the first layers to curve a profile of the first surfaces, depositing first, second, and third passivation layers on the first, second, and third surfaces, respectively, forming an epitaxial S/D region within the S/D opening, and replacing the polysilicon gate structure with a metal gate structure. The superlattice structure includes first and second layers with first and second lattice constants, respectively, and the first and second lattice constants are different from each other.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device

99.

AIR SPACER FORMATION WITH A SPIN-ON DIELECTRIC MATERIAL

      
Application Number 18769246
Status Pending
Filing Date 2024-07-10
First Publication Date 2024-10-31
Owner Taiwan Semiconductor Manufacturing Company, Ltd. (Taiwan, Province of China)
Inventor
  • Chen, Ting-Ting
  • Ho, Tsai-Jung
  • Ko, Tsung-Han
  • Ueno, Tetsuji
  • Cheng, Yahru
  • Wang, Chen-Han
  • Lin, Keng-Chu
  • Liang, Shuen-Shin
  • Perng, Tsu-Hsiu

Abstract

The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

IPC Classes  ?

  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device

100.

ELECTRICAL FUSE BIT CELL IN INTEGRATED CIRCUIT HAVING BACKSIDE CONDUCTING LINES

      
Application Number 18771536
Status Pending
Filing Date 2024-07-12
First Publication Date 2024-10-31
Owner TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (Taiwan, Province of China)
Inventor
  • Chen, Chien-Ying
  • Chen, Yen-Jen
  • Yang, Yao-Jen
  • Chang, Meng-Sheng
  • Huang, Chia-En

Abstract

An integrated circuit includes a front-side horizontal conducting line and a front-side vertical conducting line at the front side of the substrate, a transistor in a semiconductor structure at the front side of the substrate, and a backside conducting line at a backside of the substrate. The front-side horizontal conducting line is directly connected to a first terminal of the transistor through a front-side terminal via-connector and directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. A word connection line directly is connected to a gate terminal of the transistor through a gate via-connector. The backside conducting line is directly connected to a second terminal of the transistor through a backside terminal via-connector. In the integrated circuit, a front-side fuse element is conductively connected to either the front-side vertical conducting line or the front-side horizontal conducting line.

IPC Classes  ?

  • H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
  • G11C 17/16 - Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H10B 20/20 - Programmable ROM [PROM] devices comprising field-effect components
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