SK Hynix Inc.

Republic of Korea

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        Patent 13,913
        Trademark 44
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        United States 13,808
        World 124
        Europe 14
        Canada 11
Owner / Subsidiary
[Owner] SK Hynix Inc. 10,980
Hynix Semiconductor Inc. 2,693
SK hynix memory solutions inc. 163
Siliconfile Technologies Inc. 92
BOE-Hydis Technology Co., Ltd. 29
Date
New (last 4 weeks) 92
2024 March (MTD) 71
2024 February 50
2024 January 105
2023 December 68
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IPC Class
G06F 3/06 - Digital input from, or digital output to, record carriers 1,534
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers 1,112
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS 1,017
G11C 7/00 - Arrangements for writing information into, or reading information out from, a digital store 880
G11C 16/10 - Programming or data input circuits 680
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NICE Class
09 - Scientific and electric apparatus and instruments 38
35 - Advertising and business services 3
42 - Scientific, technological and industrial services, research and design 2
40 - Treatment of materials; recycling, air and water treatment, 1
Status
Pending 1,348
Registered / In Force 12,609
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1.

IMAGE SENSING DEVICE

      
Application Number 18527888
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor Ha, Dong Ho

Abstract

An image sensing device includes a pixel array configured to include a plurality of pixel groups consecutively arranged in row and column directions. Each of the pixel groups includes a plurality of unit pixels and each unit pixel includes a photoelectric conversion element structured to generate photocharges through a conversion of incident light. Each pixel group outputs a first pixel signal corresponding to photocharges generated by a single unit pixel and a second pixel signal corresponding to a sum of photocharges generated by two or more unit pixels.

IPC Classes  ?

  • H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion

2.

IMAGE SENSOR

      
Application Number 18295271
Status Pending
Filing Date 2023-04-04
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Yu Jin
  • Song, Jeong Eun

Abstract

Disclosed is an image sensor including a buffer circuit suitable for generating, based on at least one first signal, at least one second signal controlled during each of settling and comparison periods, a comparison circuit suitable for using an operating current having a relatively high level during the settling period and a relatively low level during the comparison period based on the second signal, and comparing a pixel signal with a ramp signal during the comparison period to generate a comparison signal.

IPC Classes  ?

  • H04N 25/709 - Circuitry for control of the power supply
  • H04N 25/60 - Noise processing, e.g. detecting, correcting, reducing or removing noise
  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

3.

PACKAGING DEVICE INCLUDING BUMPS AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18186284
Status Pending
Filing Date 2023-03-20
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Jae Jun
  • Kim, Jong Yeon
  • Kim, Jong Hoon
  • Yang, Ju Heon
  • Lee, Mi Seon

Abstract

A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/498 - Leads on insulating substrates

4.

DATA INTERLEAVER FOR BURST ERROR CORRECTION

      
Application Number 17934910
Status Pending
Filing Date 2022-09-23
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zhang, Fan
  • Duan, Hongwei
  • Wang, Haobo

Abstract

To improve error correction when errors occur in consecutive bits of user data, the user data can be stored in an interleaved manner. Data of a data unit can be interleaved to generate a permutated data unit. A checksum of the permutated data unit can then be calculated, and an error correction code can be generated over the data unit and the checksum. The error correction code can also be interleaved to generate a permutated error correction code. The permutated data unit, the checksum, and the permutated error correction code can then be concatenated to generate a storage data unit for storage in a memory.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

5.

SEMICONDUCTOR DEVICE INCLUDING CONNECTION PORTION BETWEEN STACKED STRUCTURES AND METHOD OF FABRICATING THE SAME

      
Application Number 18192643
Status Pending
Filing Date 2023-03-30
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Im, Mir
  • Koo, Won Tae

Abstract

A semiconductor device according to an embodiment includes a first stacked structure including a first base body, a first connection pad disposed over a surface of the first base body, and a first pad buffer layer disposed adjacent to the first connection pad and the first pad buffer layer including an insulating material having a porous structure. In addition, the semiconductor device includes a second stacked structure including a second base body, a second connection pad disposed over a surface of the second base body, and a second pad buffer layer disposed adjacent to the second connection pad and the second pad buffer layer including an insulating material having a porous structure. The semiconductor device includes a connection portion of the first and second stacked structures that connects the first and second connection pads.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

6.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18097931
Status Pending
Filing Date 2023-01-17
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Dae Won
  • Kim, Sung Kyu

Abstract

A method of manufacturing a semiconductor device includes forming a first photoresist layer on a substrate and forming a second photoresist layer on the first photoresist layer. The method also includes forming a first dissolvable region having a first width in the first photoresist layer and a second dissolvable region having a second width different from the first width in the second photoresist layer by radiating exposure light to some parts of the second and first photoresist layer. The method further includes forming a second opening in the second photoresist layer and a first opening in the first photoresist layer by developing the second dissolvable region and the first dissolvable region. The method additionally includes forming a conductive bump that fills the first and second openings.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

7.

POWER DISTRIBUTION NETWORK AND SEMICONDUCTOR DEVICE

      
Application Number 18146408
Status Pending
Filing Date 2022-12-26
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kang, Ki Bum
  • Kim, Myeong Jin
  • Kim, Jin Hyun
  • Ra, Yun
  • Park, Gyu Sun
  • Jang, Sei Hyung

Abstract

Various embodiments generally relate to a power distribution network and a semiconductor device, which may include: a plurality of chip pads; a first distribution layer in which a plurality of first conductive lines having rectangular shapes of different sizes, respectively, are disposed; a second distribution layer in which a plurality of second conductive lines including a central cross-shaped conductive line and L-shaped conductive lines open toward respective corners of the second distribution layer are disposed; and a redistribution layer electrically coupling chip pads to which power is applied among the plurality of chip pads and the first conductive lines of the first distribution layer.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

8.

OUT-OF-ORDER BIT-FLIPPING DECODERS FOR NON-VOLATILE MEMORY DEVICES

      
Application Number 17950528
Status Pending
Filing Date 2022-09-22
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zhang, Fan
  • Asadi, Meysam
  • Wang, Haobo

Abstract

Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

9.

MEMORY DEVICE FOR PERFORMING TARGET REFRESH OPERATION AND OPERATING METHOD THEREOF

      
Application Number 18453321
Status Pending
Filing Date 2023-08-22
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Hwang, Jeong Jin
  • Jung, Chul Moon

Abstract

A memory device includes a memory cell region including a plurality of rows; a row-hammer control circuit including first and second queues, and configured to: read counting data from a row indicated by a row address according to an active command, store the row address in the first queue according to a comparison result of the counting data and a first set value, store the row address in the second queue according to a comparison result of the counting data and a second set value, and select, as a row-hammer address according to a refresh management command or a target refresh command, one of the row addresses stored in the first queue and the second queue; and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command.

IPC Classes  ?

  • G06F 21/56 - Computer malware detection or handling, e.g. anti-virus arrangements
  • G06F 21/55 - Detecting local intrusion or implementing counter-measures

10.

PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND OPERATING METHOD THEREOF

      
Application Number 18534037
Status Pending
Filing Date 2023-12-08
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jeon, Yong Tae
  • Yang, Ji Woon
  • Park, Dae Sik

Abstract

An SSD device comprises a first port linking up with a first host using a first link, a second port linking up with the first host or a second host using a second link, and a port mode controller controlling the first port and the second port to change an operating mode from a dual port mode, in which the first port and the second port operate independently of each other, to a single port mode, in which only the first port operates. The port mode controller controls the second port to reset the second link in a state where the first link is linked up.

IPC Classes  ?

  • G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation

11.

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18526643
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Nam Jae

Abstract

A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.

IPC Classes  ?

  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

12.

SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF MEMORY BLOCKS AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18525594
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-28
Owner SK hynix Inc. (Republic of Korea)
Inventor Jang, Jung Shik

Abstract

A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

13.

VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

      
Application Number 18303503
Status Pending
Filing Date 2023-04-19
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kwak, Jung Hyeok
  • Kim, Tae Yup
  • Jung, Ku Youl
  • Jung, Jin Won

Abstract

Variable resistance elements and semiconductor devices including the variable resistance elements are disclosed. In some implementations, a variable resistance element may include a variable resistance element may include a free layer having a variable magnetization direction that switches between different magnetization directions upon application of a magnetic field, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer and including a metal chalcogenide having a cubic crystal structure.

IPC Classes  ?

  • H10N 50/85 - Magnetic active materials
  • H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/20 - Spin-polarised current-controlled devices

14.

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

      
Application Number 18175548
Status Pending
Filing Date 2023-02-28
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Bo Kyeong

Abstract

Provided herein may be a memory controller and a memory system including the same. The memory system may include a plurality of memory devices, each including a plurality of zone blocks, a buffer memory configured to store pieces of map data that are respectively allocated to a plurality of zones corresponding to logical address groups provided by a host and that indicate correspondence relationships between the plurality of zones and physical addresses of the plurality of zone blocks, and a memory controller configured to perform a data movement operation of storing data, which is stored in a zone block allocated to one of the plurality of zones, in an additional zone block based on information related to the plurality of zone blocks, and update a physical address of the zone block corresponding to the one zone to a physical address of the additional zone block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

15.

MEMORY CONTROLLER AND STORAGE DEVICE INCLUDING SAME

      
Application Number 18186203
Status Pending
Filing Date 2023-03-20
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Han
  • Won, Jae Yeon
  • Jeong, Cheon Ok

Abstract

The present disclosure relates to a storage device including a memory device to which a namespace including a plurality of zones is applied, a cache memory caching a media encryption key corresponding to each of a plurality of key tags, an encryptor encrypting data subject to a write request in response to a command input from a host by using a media encryption key corresponding to a key tag included in the command, and outputting encrypted data, and a write operation controller controlling the memory device to store the encrypted data in the memory device, wherein the media encryption key is a second media encryption key generated based on a first media encryption key provided from the host and a Root of Trust (RoT) generated from the encryptor.

IPC Classes  ?

16.

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

      
Application Number 18115456
Status Pending
Filing Date 2023-02-28
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jeong, Woo Young
  • Koo, Ja Min
  • Kim, Tae Hyun
  • Jeon, Jae Hwan
  • Cho, Chang Hun

Abstract

An image processing device including: a decision pixel manager for setting a decision area for a defect candidate pixel, and determining a first decision pixel and a second decision pixel, based on first phase information of pixels included in the decision area with respect to a first modulation frequency of a sensing light source among the pixels; a target pixel determiner for calculating a phase difference between the first decision pixel and the second decision pixel, based on second phase information of the pixels with respect to a second modulation frequency of the sensing light source, and determining the defect candidate pixel as a target pixel, corresponding to that the phase difference exceeds a predetermined reference value; and a phase corrector for changing a phase of the target pixel, based on the phase difference.

IPC Classes  ?

  • H04N 25/683 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects by defect estimation performed on the scene signal, e.g. real time or on the fly detection
  • H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
  • H04N 25/705 - Pixels for depth measurement, e.g. RGBZ

17.

MEMORY, CONTROLLER, MEMORY SYSTEM AND OPERATION METHOD OF MEMORY SYSTEM

      
Application Number 18304345
Status Pending
Filing Date 2023-04-21
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Baek, Jin Ho
  • Joo, Young Pyo

Abstract

A memory controller includes: a data separator configured to separate host write data into upper data and lower data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing the upper data into a first storage region that is selected based on the first address in a memory, and one or more second commands for writing the lower data into a second storage region that is selected based on the second address in the memory; and a control block configured to control the address generator and the command generator to make a difference in power consumption between the first storage region and the second storage region.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

18.

METHOD AND APPARATUS FOR SETTING SEMICONDUCTOR DEVICE MANUFACTURING PARAMETER

      
Application Number 18458896
Status Pending
Filing Date 2023-08-30
First Publication Date 2024-03-21
Owner
  • SK Hynik Inc. (Republic of Korea)
  • POSTECH ACADEMY-INDUSTRY FOUNDATION (Republic of Korea)
Inventor
  • Kim, Choong Ki
  • Byun, Hong Chul
  • Yun, Hyeok
  • Baek, Rock Hyun

Abstract

Determining a semiconductor device manufacturing parameter may include determining an EPM (electrical measurement parameters) group that has a correlation in a baseline EPM dataset including EPMs of a device manufactured under a baseline condition, deriving principal components (PCs) corresponding to main correlation axes between EPMs in the EPM group, deriving a PC-based dataset including a baseline PC dataset and a conditional split PC dataset by converting the baseline EPM dataset and a conditional split EPM dataset measured from devices manufactured under conditional splits into a PC domain, determining, using the PC-based dataset, respective PCs which are effectively changed by the conditional splits, obtaining split variation information of the conditional splits, extracting an optimal point capable of optimizing a figure of merit of a semiconductor device within a range of the PC-based dataset, and deriving information for process feedback for realizing the optimal point using the split variation information.

IPC Classes  ?

  • G05B 19/4099 - Surface or curve machining, making 3D objects, e.g. desktop manufacturing

19.

MEMORY PACKAGE AND MEMORY MODULE INCLUDING THE MEMORY PACKAGE

      
Application Number 18108657
Status Pending
Filing Date 2023-02-13
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Won Ha
  • Ko, Han Suk
  • Kang, Uksong

Abstract

A single memory package includes: a substrate; and a memory chip and a buffer chip that are integrated over the substrate, wherein the memory chip includes an interface modulator embedded therein, and the interface modulator is a serializing modulator including a multi-level amplitude modulator.

IPC Classes  ?

  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

20.

STORAGE DEVICE, HOST DEVICE, AND ELECTRONIC DEVICE

      
Application Number 18118447
Status Pending
Filing Date 2023-03-07
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Do Hyeong

Abstract

An electronic device may include a storage device including a memory device configured to store data which includes map data including a plurality of map segments and a memory controller configured to be in communication with the memory device; and a host device configured to be in communication with the storage device and structured to include a host memory and configured to transmit, to the storage device, a request for one or more of the plurality of map segments from the storage device, wherein the memory controller of the storage device is configured to provide the one or more map segments to the host memory in the host device in response to the request from the host device, and wherein the host device is configured to transmit, to the storage device, a command requesting access to the memory device based on the one or more map segments.

IPC Classes  ?

  • G06F 12/1009 - Address translation using page tables, e.g. page table structures

21.

SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18183008
Status Pending
Filing Date 2023-03-13
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jae Woong

Abstract

A semiconductor memory device includes a channel layer coupled to a bit line, a cell string located along a first side portion of the channel layer, and an auxiliary string located along a second side portion of the same channel layer.

IPC Classes  ?

  • G11C 16/10 - Programming or data input circuits
  • G11C 16/08 - Address circuits; Decoders; Word-line control circuits
  • G11C 16/26 - Sensing or reading circuits; Data output circuits

22.

MEMORY DEVICE

      
Application Number 18524646
Status Pending
Filing Date 2023-11-30
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Il Do
  • Sheen, Dong Sun
  • Kim, Seung Hwan

Abstract

A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices
  • H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/76 - Unipolar devices
  • H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
  • H01L 29/786 - Thin-film transistors

23.

SEMICONDUCTOR DEVICE HAVING STACKED STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18468551
Status Pending
Filing Date 2023-09-15
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor Park, Won Je

Abstract

A semiconductor device includes a first stacked structure including a first substrate having unit pixels, and a first interconnect layer having first conductive lines connected to the unit pixels; a second stacked structure including a second substrate having first circuit elements configured to operate the unit pixels and a second interconnect layer having second conductive lines connected to the first circuit elements and an electrode pad, and a first interconnection via structure penetrating the second substrate; a third stacked structure including a third substrate having second circuit elements configured to process signals received from the second stacked structure, and a third interconnect layer having third conductive lines connected to the second circuit elements; and a pad open region disposed outside of a pixel region including the unit pixels and exposing a top surface of the electrode pad to outside.

IPC Classes  ?

24.

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

      
Application Number 18509301
Status Pending
Filing Date 2023-11-15
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Jin Woong
  • Yim, Ji Hoon

Abstract

A data storage device includes a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device such that, when a first refresh scan command is received from a host device, a first refresh scan operation for the plurality of memory blocks is performed and then a first refresh scan result for the first refresh scan operation is transmitted to the host device, and when a first refresh operation command is received from the host device, a first refresh operation for the nonvolatile memory device is performed.

IPC Classes  ?

  • G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
  • G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

25.

BUFFER CIRCUIT CAPABLE OF REDUCING NOISE

      
Application Number 18516615
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Hwang, Jin Ha
  • An, Soon Sung
  • Jang, Junseo
  • Hong, Jaehyeong

Abstract

A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.

IPC Classes  ?

  • H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only
  • H03K 19/003 - Modifications for increasing the reliability

26.

MEMORY DEVICE INCLUDING ERROR CORRECTION DEVICE

      
Application Number 18080282
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jeong, Jin Ho
  • Kim, Dae Suk
  • Jang, Mun Seon

Abstract

A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.

IPC Classes  ?

  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

27.

SYSTEM AND STORAGE DEVICE FOR EXECUTING READ COMMAND USING READ RECOVERY LEVEL AND METHODS OF OPERATION

      
Application Number 18058751
Status Pending
Filing Date 2022-11-24
First Publication Date 2024-03-21
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Shin, Young Kyun
  • Joh, Jung Hyun

Abstract

A storage device may receive, from an external device, a target read recovery level indicating information on a read command execution completion time and an error recovery amount requested by the external device, may read, from a memory, data requested by a read command transmitted by the external device, and may transmit, to the external device, a response regarding a result of executing the read command transmitted by the external device within the read command execution completion time indicated by the target read recovery level.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

28.

SSD PERFORMANCE PER POWER STATE IMPROVEMENT BY DETERMINISTIC UTILIZATION CONTROL

      
Application Number 17940324
Status Pending
Filing Date 2022-09-08
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Shin, Seong Won
  • Mallikarjunaswamy, Kailash

Abstract

A method for operating a system including a host and at least one solid state drive (SSD). The method identifies a workload associated with the SSD, recognizes a power state of the SSD, and controls allocation and/or deallocation of hardware resources for the identified workload per a budgeted target for the power state.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

29.

BIT-FLIPPING DECODER AND DECODING METHOD FOR IRREGULAR CODES

      
Application Number 17944734
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zhang, Fan
  • Asadi, Meysam
  • Wang, Haobo

Abstract

A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

30.

CONSTRAINED CLUSTERING ALGORITHM FOR EFFICIENT HARDWARE IMPLEMENTATION OF A DEEP NEURAL NETWORK ENGINE

      
Application Number 17944805
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zhang, Fan
  • Karakulak, Seyhan
  • Wang, Haobo
  • Asadi, Meysam

Abstract

A method and a system for operating a deep neural network. In the method and system, a subset of floating-point values are used to represent weights in the DNN; the floating-point values are quantized onto a flexible-power-of-two (FPoT) alphabet; values in the FPoT alphabet are listed in a plurality of regions; and an empty region among the plurality of regions is merged to neighbour regions to output dusters of the weights in merged regions, the merged regions having respective centroids and boundary lines in between.

IPC Classes  ?

  • G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow

31.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18104711
Status Pending
Filing Date 2023-02-01
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Hyun Sub
  • Kim, Sun Woo
  • Bin, Jin Ho

Abstract

A semiconductor device may include a gate structure, a channel structure extending through the gate structure, a first hydrogen supply layer disposed on the gate structure, having a first hydrogen concentration, and comprising an oxygen vacancy, and a hydrogen blocking layer disposed on the first hydrogen supply layer and having a second hydrogen concentration lower than the first hydrogen concentration.

IPC Classes  ?

32.

IMAGE SENSOR, IMAGE PROCESSING SYSTEM, AND OPERATING METHOD OF THE IMAGE PROCESSING SYSTEM

      
Application Number 18190852
Status Pending
Filing Date 2023-03-27
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor Cha, Su Ram

Abstract

Disclosed is an image sensor including a pixel array having a pixel pattern in which first to fourth 2×2 pixel groups are arranged in a clockwise direction, one infrared pixel is arranged in each of two 2×2 pixel groups that are not adjacent to each other, the same green pixels are arranged in a first diagonal direction, and red pixels and blue pixels are arranged in half in a second diagonal direction crossing the first diagonal direction, in a 4×4 unit pixel group.

IPC Classes  ?

  • H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
  • H04N 23/11 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
  • H04N 23/84 - Camera processing pipelines; Components thereof for processing colour signals
  • H04N 25/131 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
  • H04N 25/702 - SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout

33.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18508231
Status Pending
Filing Date 2023-11-14
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Beom-Yong

Abstract

A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

IPC Classes  ?

  • H01L 29/51 - Insulating materials associated therewith
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/49 - Metal-insulator semiconductor electrodes
  • H01L 29/94 - Metal-insulator-semiconductors, e.g. MOS

34.

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

      
Application Number 18510656
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Jin Woong
  • Yim, Ji Hoon

Abstract

A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

IPC Classes  ?

  • G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles
  • G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

35.

MEMORY SYSTEM

      
Application Number 18516549
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Joon-Woo
  • Hwang, Jeong-Tae

Abstract

A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.

IPC Classes  ?

  • G06F 21/55 - Detecting local intrusion or implementing counter-measures

36.

CLOCK GENERATING CIRCUIT AND CLOCK DISTRIBUTION NETWORK AND SEMICONDUCTOR APPARATUS INCLUDING THE CLOCK GENERATING CIRCUIT

      
Application Number 18094227
Status Pending
Filing Date 2023-01-06
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Yeon Ho
  • Choi, Yong Suk

Abstract

A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.

IPC Classes  ?

  • G06F 1/08 - Clock generators with changeable or programmable clock frequency
  • G06F 1/10 - Distribution of clock signals
  • G06F 1/12 - Synchronisation of different clock signals

37.

SEMICONDUCTOR MODULE AND SYSTEM INCLUDING THE SAME

      
Application Number 18104917
Status Pending
Filing Date 2023-02-02
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Nam Hyeon
  • Ryu, Seung Jin

Abstract

A semiconductor module includes a semiconductor module body and a guide. The semiconductor module body extends in a first direction and a second direction intersecting the first direction. A plurality of connection terminals is arranged at one end of the semiconductor module in the second direction. A plurality of semiconductor devices is arranged on at least one side of the semiconductor module body. The guide is arranged at the other end of the semiconductor module body opposite to the one end to induce a flow of a cooling fluid toward the one end of the semiconductor module.

IPC Classes  ?

  • H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
  • H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
  • H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

38.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18117249
Status Pending
Filing Date 2023-03-03
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jae Taek

Abstract

Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.

IPC Classes  ?

  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 99/00 - Subject matter not provided for in other groups of this subclass

39.

SEMICONDUCTOR DEVICE

      
Application Number 18187628
Status Pending
Filing Date 2023-03-21
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor Rim, Da Il

Abstract

A semiconductor device includes: a first semiconductor structure including a first semiconductor substrate, one or more first conductive patterns, a plurality of first conductive plugs, and a first bonding pad; a second semiconductor structure including a second semiconductor substrate, a plurality of second conductive patterns, one or more second conductive plugs, and a second bonding pad; and two through electrodes penetrating the second semiconductor substrate and respectively connected to two second conductive patterns positioned at opposite ends of the plurality of second conductive patterns, wherein the second bonding pad is bonded to the first bonding pad so that the plurality of second conductive patterns, the one or more second conductive plugs, the second bonding pad, the first bonding pad, the plurality of first conductive plugs, and the one or more first conductive patterns form a daisy chain.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

40.

MEMORY SYSTEM PERFORMING GARBAGE COLLECTION OPERATION BY EXCHANGING INFORMATION RELATED TO GARBAGE COLLECTION WITH HOST AND METHOD OF OPERATING THE MEMORY SYSTEM

      
Application Number 18507963
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor Kang, Hye Mi

Abstract

An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocation; Relocation
  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

41.

IMAGE SENSING DEVICE

      
Application Number 18508699
Status Pending
Filing Date 2023-11-14
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Yoon, Hyung June
  • Kim, Jong Eun
  • Kim, Jong Chae
  • Lee, Jae Won
  • Jang, Jae Hyung
  • Choi, Hoon Moo

Abstract

An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel.

IPC Classes  ?

42.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

      
Application Number 18511695
Status Pending
Filing Date 2023-11-16
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Noh, Jae Yoon
  • Kim, Tae Kyung
  • Yeom, Hyo Sub
  • Lee, Jeong Yun

Abstract

There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

43.

SYSTEM AND METHOD FOR HISTORY-BASED NON-PARAMETRIC CHANNEL INFORMATION PREDICITON USING A DEEP NEURAL NETWORK

      
Application Number 17944862
Status Pending
Filing Date 2022-09-14
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Wang, Haobo
  • Asadi, Meysam
  • Zhang, Fan

Abstract

A memory system or a method for estimating channel information to be used for error decoding. The memory system or the method a) performs one or more read operations on a page selected from among the plurality of pages using a target read threshold, b) obtains the target read threshold, a historical read threshold voltage set associated with failed read operations of the selected page, checksum values, and asymmetric ratios of ones count and zeros count which are associated with the historical read threshold voltage set, c) provides the obtained target read threshold, historical read threshold voltage set, checksum values and asymmetric ratios as input information to a neural network, and d) predicts, by the neural network, channel information at the target read threshold based on the input information and a set activation function.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

44.

METHOD FOR LANE SYNCHRONIZATION FOR AN INTERCONNECTION PROTOCOL, CONTROLLER, AND STORAGE DEVICE

      
Application Number 17972377
Status Pending
Filing Date 2022-10-24
First Publication Date 2024-03-14
Owner SK hynix Inc. (Republic of Korea)
Inventor Lin, Fu Hsiung

Abstract

A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.

IPC Classes  ?

45.

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE

      
Application Number 18106923
Status Pending
Filing Date 2023-02-07
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jin Ha

Abstract

A memory device, and a manufacturing method of the memory device, includes a stack structure including alternately stacked first and second material layers. The memory device also includes a vertical hole extending through the stack structure in a vertical direction, isolation patterns protruding from side surfaces of the first material layers formed inside the vertical hole, and a blocking layer formed along surfaces of the protruding isolation patterns and the second material layers. The memory device further includes a barrier layer formed along a surface of the blocking layer and charge trap layers formed between protrusion parts of the barrier layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

46.

MEMORY DEVICE HAVING STABLE SELF-REFRESH OPERATION AND OPERATING METHOD THEREOF

      
Application Number 18107503
Status Pending
Filing Date 2023-02-09
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Sang Hoon
  • Byeon, Sang Jin
  • Lee, Kyo Yun

Abstract

An operating method of a memory device, comprising: entering self-refresh section, updating a counting code by counting an edge of a reference cycle signal, first activating an operation control signal for the self-refresh section when a temperature application code has an initialized value in response to the counting code, updating the temperature application code after the operation control signal is first activated, second activating the operation control signal in response to the counting code based on the updated temperature application code, exiting from the self-refresh section, and initializing the counting code and the temperature application code.

IPC Classes  ?

  • G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles

47.

IMAGE SENSOR AND METHOD OF OPERATING THE IMAGE SENSOR

      
Application Number 18108473
Status Pending
Filing Date 2023-02-10
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Hak Soon

Abstract

An image sensor including a light signal generator configured to generate a plurality of light signals having different phases based on a reference light signal, a demodulated signal generator configured to generate a plurality of demodulated signals based on the reference light signal, a light source configured to sequentially output the plurality of light signals to an object, a light receiver configured to receive a plurality of reflected light signals in which the plurality of light signals are reflected from the object, and a pixel array configured to generate a plurality of pixel signals based on the plurality of demodulated signals and the plurality of reflected light signals.

IPC Classes  ?

  • H04N 25/71 - Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
  • H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array

48.

STORAGE DEVICE DETERMINING A POLICY FOR FETCHING COMMANDS FROM A PLURALITY OF COMMAND QUEUES, AND METHOD THEREOF

      
Application Number 18160040
Status Pending
Filing Date 2023-01-26
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kwon, Kang Rak
  • Lee, Seon Ju

Abstract

A storage device may fetch commands from a plurality of command queues. The storage device may determine a policy for fetching commands from the plurality of command queues as a first policy or a second policy on the basis of the state of a target command queue among the plurality of command queues. The policy may control an order in which commands are fetched from the plurality of command queues.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

49.

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18175541
Status Pending
Filing Date 2023-02-28
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Choi, Won Geun
  • Jang, Jung Shik

Abstract

A memory device and a method of manufacturing the same. The memory device may include a stacked structure including a drain selection line, word lines, and a source selection line that are sequentially stacked, a main plug extending in a vertical direction of the stacked structure, and including a sub-source layer hole in a central portion of an upper area of the main plug, a separation pattern configured to separate the main plug in a vertical direction, and a source line stacked on the stacked structure, and configured to fill the sub-source layer hole.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

50.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18506906
Status Pending
Filing Date 2023-11-10
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Heo, Min Young

Abstract

The present technology provides a method of manufacturing a semiconductor device. The method includes forming a preliminary source structure, forming a stack structure on the preliminary source structure, the stack structure including a first material layer and a second material layer, forming a preliminary memory layer that penetrates the stack structure, forming a trench passing through the stack structure, forming a first buffer pattern by performing a surface treatment on a portion of the second material layer that is exposed by the trench, and forming a protective layer covering the first buffer pattern.

IPC Classes  ?

  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

51.

INTEGRATED CIRCUIT AND MEMORY DEVICE INCLUDING SAMPLING CIRCUIT

      
Application Number 18080293
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Noh, Jun Seok

Abstract

An integrated circuit includes a sampling control circuit configured to: generate a counting signal according to a periodic signal during a sampling period, and generate a plurality of sampling enable signals by comparing counting bits of the counting signal with random bits of a random signal; and a sampling circuit configured to: store an input address as a plurality of sampling addresses according to the respective sampling enable signals, and generate a plurality of valid section signals based on the sampling enable signals to output one of the sampling addresses as a target address according to an uppermost valid section signal among activated valid section signals.

IPC Classes  ?

  • G11C 11/406 - Management or control of the refreshing or charge-regeneration cycles

52.

METHOD OF MANUFACTURING SEMICONDUCTOR CHIP INCLUDING FORMING DICING GROOVES AND SEMICONDUCTOR DEVICE

      
Application Number 18087811
Status Pending
Filing Date 2022-12-23
First Publication Date 2024-03-07
Owner SK hynix Inc (Republic of Korea)
Inventor
  • Lee, Byung Cheol
  • Kim, Jong Su

Abstract

A method of manufacturing a semiconductor chip and a semiconductor device. The method of manufacturing the semiconductor chip includes a process of dicing a substrate. The substrate includes an active layer and an organic layer on the semiconductor base. Dicing grooves that are extended to face each other along first dicing lines from points, at which the first dicing lines and second dicing lines along which the substrate is to be diced intersect, are formed by recessing some parts of the active layer. Modified patterns are formed within the semiconductor base. The substrate is diced into semiconductor chips by propagating cracks into the substrate from the modified patterns.

IPC Classes  ?

  • H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

53.

SEMICONDUCTOR DEVICES FOR CONTROLLING REFRESH OPERATIONS CONSIDERING REPAIR OPERATIONS

      
Application Number 18089261
Status Pending
Filing Date 2022-12-27
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Ku, Sang Hyun
  • Choi, Don Hyun

Abstract

A semiconductor device includes a redundancy control signal generation circuit configured to generate a redundancy control signal by determining whether a row address for an active operation has been repaired through a soft post package repair operation and determining whether a row hammer phenomenon has occurred with respect to the row address. The semiconductor device also includes a first selection address generation circuit configured to generate a first selection address for driving a sub word line or a redundancy word line from one of a repair address and a first internal address, based on the redundancy control signal. The semiconductor device further includes a second selection address generation circuit configured to generate a second selection address for driving the sub word line or the redundancy word line from one of a fixed address and a second internal address, based on the redundancy control signal.

IPC Classes  ?

  • G11C 29/44 - Indication or identification of errors, e.g. for repair
  • G11C 29/00 - Checking stores for correct operation; Testing stores during standby or offline operation

54.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A CONDUCTIVE LINE

      
Application Number 18095349
Status Pending
Filing Date 2023-01-10
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Yoon, Jae Man
  • Kim, Jun Ki
  • Kim, Tae Kyun
  • Park, Jung Woo
  • Ha, Jae Won

Abstract

A method of manufacturing a semiconductor device includes: forming a trench in an insulating interlayer by etching the insulating interlayer; forming a conductive layer on bottom, side, and upper surfaces of the insulating interlayer where the trench is formed, using a first deposition process, the conductive layer on the bottom surface of the trench being thicker than the conductive layer on the side surface of the trench; forming a sacrificial layer in the trench covering the conductive layer formed on the bottom surface of the trench using a second deposition process different from the first deposition process; selectively removing the conductive layer formed on the upper surface of the insulating interlayer and formed on the side surface of the trench left exposed through the sacrificial layer; and selectively removing the sacrificial layer, to form a conductive line using the conductive layer remaining on the bottom surface of the trench.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
  • H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

55.

IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18069795
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Kwag, Pyong Su

Abstract

An image sensing device includes a first substrate including a first surface and a second surface facing away from the first surface, the first substrate including a pixel region and a pad region located outside the pixel region, the pixel region being structured to include pixel that generate electrical signals based on light incident upon the first surface to reach to the pixels, an insulation layer disposed under the second surface and including interconnects and an electrode pad, a pad open region disposed in the pad region and structured to expose the electrode pad, and a substrate isolation layer disposed outside the pixel region in the first substrate and formed to penetrate the first substrate. The substrate isolation layer includes a lens material.

IPC Classes  ?

56.

SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR DEVICE FOR PERFORMING DEFECTIVE ANALYSIS

      
Application Number 18070606
Status Pending
Filing Date 2022-11-29
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Cho, Byung Goo

Abstract

A semiconductor system includes a controller configured to: select a plurality of fail points based on defect analysis information collected in a process stage, and provide an address designating at least one of the fail points together with a partial reset command; and a semiconductor device including a plurality of functional regions each including one or more of the fail points, the semiconductor device configured to reset, in response to the partial reset command, a sequential circuit disposed in a target functional region corresponding to the address among the functional regions.

IPC Classes  ?

  • G11C 29/44 - Indication or identification of errors, e.g. for repair
  • G11C 29/18 - Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents

57.

STACKED INTEGRATED CIRCUIT CONFIGURED TO DISTINGUISH CHIPS WITHIN STACKED CHIPS

      
Application Number 18096427
Status Pending
Filing Date 2023-01-12
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Dong Uk

Abstract

A stacked integrated circuit includes an upper chip that is rotated around a rotation axis and stacked on a lower chip in the form of a mirror symmetric structure. The lower chip and the upper chip are stacked in the form of a front and front connection structure. The upper chip is configured to generate a first internal distinguishment signal based on a distinguishment signal. The upper chip is configured to generate a first input/output control signal for the input/output of a power signal based on the first internal distinguishment signal and a chip selection signal. The lower chip is configured to generate a second internal distinguishment signal based on a reset signal. The lower chip is configured to generate a second input/output control signal for the input/output of the power signal based on the second internal distinguishment signal and the chip selection signal.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

58.

MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATION METHOD THEREOF

      
Application Number 18096561
Status Pending
Filing Date 2023-01-13
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Cho, Seung Duk
  • Chang, Woo Tae
  • Jeong, Gi Jo
  • Joh, Jung Hyun

Abstract

The present disclosure relates to a memory system capable of encrypting and storing data, and a memory controller. The memory controller may include a first interface configured to perform data Communication with a first external device, a second interface configured to generate a signal for controlling an operation of a second extern& device and transmit the signal; and a processor configured to receive, from the first external device, a data write command to write data to the second external device, encrypt the data by using one of a plurality of keys stored in a key area provided in the first external device in response to the data write command, and then control the encrypted data to be written to the second external device.

IPC Classes  ?

  • G06F 21/60 - Protecting data
  • G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data

59.

SEMICONDUCTOR DEVICE INCLUDING BARRIER DIELECTRIC LAYER INCLUDING FERROELECTRIC MATERIAL

      
Application Number 18097493
Status Pending
Filing Date 2023-01-17
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Suh, Dong Ik
  • Koo, Won Tae

Abstract

A semiconductor device according to an embodiment includes a first electrode and a second electrode that are spaced apart from each other, a capacitor dielectric structure disposed between the first electrode and the second electrode, and a barrier dielectric layer disposed between one of the first and second electrodes and the capacitor dielectric structure. The capacitor dielectric structure may include a ferroelectric layer and a dielectric layer. The barrier dielectric layer may include a ferroelectric material.

IPC Classes  ?

  • H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

60.

SEMICONDUCTOR DEVICE

      
Application Number 18104789
Status Pending
Filing Date 2023-02-02
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Park, Jin Won

Abstract

A semiconductor device may include: a first semiconductor structure including a first conductive layer and four first bonding pads connected to the first conductive layer; and a second semiconductor structure including a second conductive layer and four second bonding pads connected to the second conductive layer, wherein the four first bonding pads are configured to be disposed to have respective centers each overlapping four intersections that are formed by two virtual first straight lines extending in parallel in a first direction and two virtual second straight lines extending in parallel in a second direction intersecting the first direction, where each of the four first bonding pads has four quadrants divided by the first straight line and the second straight line, and wherein, when the first semiconductor structure and the second semiconductor structure are normally aligned, the four second bonding pads are configured to be disposed to have respective centers that are displaced in directions from the respective centers of the four first bonding pads toward different quadrants.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/528 - Layout of the interconnection structure

61.

ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE ERROR CORRECTION CODE CIRCUIT

      
Application Number 18104907
Status Pending
Filing Date 2023-02-02
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Moon, Hong Ki

Abstract

An embodiment includes: an error information processing circuit configured to generate error information according to syndrome information; and a data correction circuit configured to correct an error in data according to the syndrome information. In a test mode, only the error information processing circuit between the error information processing circuit and the data correction circuit is configured to be activated.

IPC Classes  ?

  • G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
  • G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
  • G11C 29/14 - Implementation of control logic, e.g. test mode decoders

62.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18112384
Status Pending
Filing Date 2023-02-21
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Changhan
  • Kang, In Ku
  • Kim, Dong Hyoub

Abstract

A semiconductor memory device, and a method of manufacturing the same, includes a gate stack including a plurality of gate patterns and a plurality of interlayer insulating layers alternately stacked with each other in a cell region, a source line disposed on the gate stack, and a channel plug passing through the gate stack and the source line in a vertical direction. The channel plug includes a backgate, a backgate insulating layer surrounding a sidewall of the backgate, a channel layer surrounding the sidewall of the backgate, and a memory layer surrounding a sidewall of the channel layer. The backgate insulating layer extends between the backgate and the source line.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

63.

MEMORY DEVICE AND MANUFACTURING METHOD OF THE MEMORY DEVICE

      
Application Number 18114878
Status Pending
Filing Date 2023-02-27
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Jang, Jung Shik
  • Park, Mi Seong
  • Park, In Su
  • Choi, Won Geun
  • Choi, Jung Dal

Abstract

There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first stack structure including a word line of a first group and select lines of a first group; a second stack structure including select lines of a second group; a first plug in the first stack structure; a second plug connected to the first plug, the second plug being disposed in the second stack structure; a first isolation pattern between the select lines of the first group; and a second isolation pattern between the select lines of the second group.

IPC Classes  ?

  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

64.

STORAGE DEVICE DETERMINING WHETHER TO APPLY THERMAL THROTTLING MODE TO TARGET OPERATION

      
Application Number 18146880
Status Pending
Filing Date 2022-12-27
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Chi Eun

Abstract

A storage device and a method thereof determine a candidate memory block satisfying a set condition among a plurality of memory blocks when the temperature of a memory is equal to or higher than a first temperature as a target memory block. The target memory block is used to determine whether to apply a thermal throttling mode to a target operation to be executed on the memory when the temperature of the memory is equal or higher than a second temperature in order to avoid unnecessary thermal throttling.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

65.

ATOMIC LAYER ETCHING METHOD USING LIGAND EXCHANGE REACTION

      
Application Number 18155691
Status Pending
Filing Date 2023-01-17
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Jae Chul
  • Noh, Hyun Sik
  • Lee, Dong Kyun
  • Jung, Eun Ae
  • Kim, Kyoung-Mun
  • Kim, Jooyong
  • Byun, Younghun
  • Yang, Byeong Il
  • Jin, Changhyun

Abstract

An atomic layer etching method using a ligand exchange reaction may include a substrate providing step of putting a substrate with a thin film formed thereon into a reaction chamber, a halogenated thin film forming step of forming a halogenated thin film on a surface of the thin film by infusing a halogenated gas into the reaction chamber, and an etching step of etching the halogenated thin film by infusing a ligand without a metal or metal precursor into the reaction chamber with the substrate with the halogenated thin film.

IPC Classes  ?

66.

MEMORY DEVICE FOR SUPPORTING STABLE DATA TRANSFER AND MEMORY SYSTEM INCLUDING THE SAME

      
Application Number 18159685
Status Pending
Filing Date 2023-01-26
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Hyeon Uk

Abstract

A memory device may include: a memory region, an operation control unit configured to determine a toggling reference cycle and count for a first interval, configured to determine whether an error has occurred in a toggling input cycle and count of an external control signal, in order to control a data input/output operation for the memory region based on the toggling reference cycle and count for a second interval subsequent to the first interval, and configured to determine whether an input defense mode has been entered based on a result of the error determination, and an operation execution unit configured to perform a set operation in response to the external control signal for the second interval and configured to perform, when the input defense mode has been entered, a defense operation that is predefined in the input defense mode in response to an output signal of the operation control unit.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 29/52 - Protection of memory contents; Detection of errors in memory contents

67.

SEMICONDUCTOR DEVICE

      
Application Number 18188478
Status Pending
Filing Date 2023-03-23
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Jung, Tae Kyoung

Abstract

Disclosed is a semiconductor device including a first pad, a pull-up resistor connected between the first pad and a supply terminal of a high voltage, a second pad connected to the first pad, a pull-down driver connected between the second pad and a supply terminal of a low voltage, and suitable for selectively driving the second pad with the low voltage based on a control signal corresponding to a predetermined signal, a first leakage prevention driver connected between an input terminal of the control signal and the supply terminal of the low voltage, and suitable for selectively driving the control signal with the low voltage based on a leakage prevention signal, and a controller connected to the second pad, and suitable for generating the leakage prevention signal based on a mode signal and a tie control signal.

IPC Classes  ?

  • H03K 19/00 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K 3/037 - Bistable circuits
  • H03K 19/003 - Modifications for increasing the reliability

68.

IMAGE SENSOR

      
Application Number 18296998
Status Pending
Filing Date 2023-04-07
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Dong Ju

Abstract

Disclosed is an image sensor including first to fourth, fifth to eighth, ninth to 12th and 13th to 16th unit pixel circuits, a first readout line connected to the first and ninth unit pixel circuits, a second readout line connected to the fifth and 13th unit pixel circuits, a third readout line connected to the second and 10th unit pixel circuits, a fourth readout line connected to the sixth and 14th unit pixel circuits, a fifth readout line connected to the third and 11th unit pixel circuits, a sixth readout line connected to the seventh and 15th unit pixel circuits, a seventh readout line connected to the fourth and 12th unit pixel circuits, an eighth readout line connected to the eighth and 16th unit pixel circuits, first to fourth readout circuits, and a path selector connecting the unit pixel circuits to the readout circuits via the readout lines.

IPC Classes  ?

  • H04N 25/78 - Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
  • H01L 27/146 - Imager structures
  • H04N 25/46 - Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels

69.

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18507505
Status Pending
Filing Date 2023-11-13
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor Choi, Kang Sik

Abstract

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

70.

PARALLEL SYSTEM TO CALCULATE LOW DENSITY PARITY CHECK

      
Application Number 17901126
Status Pending
Filing Date 2022-09-01
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zhang, Fan
  • Wang, Haobo
  • Duan, Hongwei

Abstract

An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.

IPC Classes  ?

  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
  • H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes

71.

HYBRID PRECISION MS DECODER TO REDUCE GATE-COUNT FOR LONG CODES

      
Application Number 17901306
Status Pending
Filing Date 2022-09-01
First Publication Date 2024-03-07
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Zhang, Fan
  • Duan, Hongwei
  • Wang, Haobo

Abstract

A method for operating an MS decoder and an associated memory system utilizing the MS decoder. The method determines an operation mode of the MS decoder. For each variable node, the method calculates a variable to check node V2C message. The method stores, in a check node unit CNU memory, check information associated with the calculated V2C message according to the operation mode. The check information includes full information when the operation mode is a high precision mode, and partial information when the operation mode is a low precision mode.

IPC Classes  ?

  • H03M 13/09 - Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

72.

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

      
Application Number 18106319
Status Pending
Filing Date 2023-02-06
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Hee Youl

Abstract

A memory device, and a method of operating the memory device, includes a memory block including memory cells. The memory device also includes a voltage generator configured to apply a read voltage and pass voltages to word lines coupled to the memory block. The voltage generator is configured to apply the read voltage to a selected word line among the word lines and apply different pass voltages to unselected word lines symmetrical to each other with respect to the selected word line depending on distances to the selected word line, during a read operation on the memory block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

73.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

      
Application Number 18108501
Status Pending
Filing Date 2023-02-10
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Dong Uk
  • Yang, Hae Chang

Abstract

A semiconductor device may include a source line, a bit line, and a gate structure located between the source line and the bit line. The gate structure may include conductive layers and insulating layers that are alternately stacked. The semiconductor device may include a topological insulator that may extend from the bit line to the source line through the gate structure. The topological insulator may include a non-conductor region and semiconductor regions coupled to the non-conductor region and located at a sidewall of the topological insulator. The semiconductor device may also include a memory layer surrounding the topological insulator.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

74.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE

      
Application Number 18112367
Status Pending
Filing Date 2023-02-21
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Hyun Sub

Abstract

Provided herein is a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a first dummy stacked body and a second dummy stacked body formed in a connection area of a substrate including a cell array area and the connection area, a cell stacked body disposed in the cell array area and the connection area and configured to enclose the first dummy stacked body and the second dummy stacked body, and a first vertical barrier disposed at a boundary between the cell stacked body and the first dummy stacked body and a second vertical barrier disposed at a boundary between the cell stacked body and the second dummy stacked body. The cell stacked body includes first and second extensions disposed to extend in substantially a linear shape in the connection area and a connector configured to connect the first and second extensions.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

75.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18194654
Status Pending
Filing Date 2023-04-03
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Dae Won
  • Kim, Yu Ri
  • Kim, Tae Kyun
  • Jeon, Jin Hwan
  • Choi, Dong Goo
  • Choi, Ri

Abstract

A semiconductor device comprises a substrate including first and second regions; a plurality of conductive line structures disposed over the substrate; a plurality of conductive contact plugs formed between the conductive line structures disposed over the first region of the substrate; and a plurality of dummy dielectric plugs disposed over the second region of the substrate.

IPC Classes  ?

  • H10B 12/00 - Dynamic random access memory [DRAM] devices

76.

IMAGE SENSING DEVICE AND METHOD FOR MANUFACTURING THE SAME

      
Application Number 18359693
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Won Jin

Abstract

An image sensing device includes a plurality of image sensing pixels configured to respond to light incident through first color filters and generate image signals corresponding to a target object to be captured, at least one phase detection pixel configured to respond to light incident through a second color filter and generate a phase signal for calculating a phase difference between images generated by the image signals, a first grid structure disposed between the adjacent first color filter and the second color filter and including a light absorption layer, and a second grid structure disposed between adjacent first color filters and structured to be free from the light absorption layer.

IPC Classes  ?

77.

SEMICONDUCTOR CHIP INCLUDING THROUGH ELECTRODE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

      
Application Number 18489557
Status Pending
Filing Date 2023-10-18
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Son, Ho Young
  • Kim, Sung Kyu
  • Lee, Mi Seon

Abstract

A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

IPC Classes  ?

  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

78.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18502084
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Yoon, Young Gwang

Abstract

Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure.

IPC Classes  ?

  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H01L 21/762 - Dielectric regions
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
  • H01L 29/66 - Types of semiconductor device

79.

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

      
Application Number 18505998
Status Pending
Filing Date 2023-11-09
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Oh, Sung Lae
  • Park, Sang Woo
  • Chae, Dong Hyuk

Abstract

A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
  • H01L 23/528 - Layout of the interconnection structure

80.

3D SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

      
Application Number 18074935
Status Pending
Filing Date 2022-12-05
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Yoon, Young Gwang

Abstract

A 3D semiconductor device includes: a word line stack over a substrate; and a channel pillar vertically penetrating the word line stack. The word line stack includes a word line and an interlayer dielectric layer. The channel pillar includes: a central dielectric layer; a channel layer surrounding a side of the central dielectric layer; a tunneling dielectric layer having a cylinder shape surrounding a side of the channel layer; an inner charge trap layer surrounding a side of the tunneling dielectric layer; a ring-shaped outer charge trap layer surrounding a side of the inner charge trap layer; and a ring-shaped blocking dielectric layer surrounding a side of the outer charge trap layer. The word line and the blocking dielectric layer have substantially the same vertical thickness. The interlayer dielectric layer is in contact with upper and lower surfaces of the outer charge trap layer and the blocking dielectric layer.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

81.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

      
Application Number 18078507
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jung Hyeong

Abstract

A semiconductor device may include a gate structure including a first conductive layer, a second conductive layer, and a third conductive layer, the third conductive layer being disposed between the first conductive layer and the second conductive layer and thicker than the first conductive layer and the second conductive layer, channel structures passing through the gate structure, and an isolation structure including a first portion passing through the second conductive layer and extended into the channel structures and a second portion protruding from the first portion into the third conductive layer and disposed between the channel structures.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

82.

IMAGE SENSING DEVICE

      
Application Number 18062969
Status Pending
Filing Date 2022-12-07
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Eun Khwang

Abstract

An image sensing device includes an image pixel region including active pixels, each active pixel configured to generate an imaging pixel signal through a photoelectric conversion of incident light received by the active pixel, and an optical black pixel region disposed separately from the image pixel region and including a plurality of black pixels and a light blocking layer that blocks incident light from entering the black pixels, each black pixel configured to generate a black pixel signal for correcting dark current. The image pixel region includes a condensing lens layer configured to condense the incident light, and the optical black pixel region includes a dispersion lens layer configured to disperse the incident light.

IPC Classes  ?

  • H01L 27/146 - Imager structures
  • H04N 25/633 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current by using optical black pixels

83.

DATA STORAGE STRUCTURE OR DATA INFRASTRUCTURE INCLDUING A PLURALITY OF STORAGE DEVICE

      
Application Number 18069292
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kang, Ho Sung

Abstract

A storage device includes a printed circuit board (PCB) with attached semiconductor chips, each including a memory, and with at least one wire coupling the plural semiconductor chips, and a breathable case surrounding a top portion and a bottom portion of the printed circuit board. The breathable case includes a first layer disposed on a second layer which is exposed to the printed circuit board. The second layer has smaller pores than the first layer.

IPC Classes  ?

  • H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
  • H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating

84.

CLOCK GENERATING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME

      
Application Number 18084956
Status Pending
Filing Date 2022-12-20
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Park, Gyu Tae
  • An, Young Jae

Abstract

A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.

IPC Classes  ?

  • H03L 7/081 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop provided with an additional controlled phase shifter
  • H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

85.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

      
Application Number 18089322
Status Pending
Filing Date 2022-12-27
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Park, Joon Hong

Abstract

A semiconductor device includes a control circuit configured to generate a buffer enable signal that is enabled when patterns of a strobe signal and an inverted strobe signal are preset patterns after the start of a write operation and configured to generate an internal strobe signal by dividing frequencies of an input strobe signal and an inverted input strobe signal, and a buffer circuit configured to generate the input strobe signal and the inverted input strobe signal from the strobe signal and the inverted strobe signal that are received when the buffer enable signal is enabled and configured to generate transfer data by receiving data for performing the write operation when the buffer enable signal is enabled.

IPC Classes  ?

  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

86.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE

      
Application Number 18092790
Status Pending
Filing Date 2023-01-03
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jae Taek

Abstract

A semiconductor device includes a gate structure including word lines and select lines, the gate structure including a first pad stepped structure for exposing each of the select lines and a common pad structure for exposing the select lines. The semiconductor device also includes first contact plugs connected to the select lines through the first pad stepped structure, respectively. The semiconductor device further includes one or more common contact plugs connected in common to the select lines through the common pad structure.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/528 - Layout of the interconnection structure
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

87.

SEMICONDUCTOR DIE INCLUDING AN ASYMMETRIC PAD ARRAYS, A SEMICONDUCTOR DIE STACK INCLUDING THE SEMICONDUCTOR DIE, AND A HIGH BANDWIDTH MEMORY INCLUDING THE SEMICONDUCTOR DIE STACK

      
Application Number 18103494
Status Pending
Filing Date 2023-01-31
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Song, Choung Ki

Abstract

A semiconductor die stack includes a lower semiconductor die and an upper semiconductor die. The upper semiconductor die includes a first upper bonding pad disposed in a first upper bonding pad region; and a second upper bonding pad disposed in a second upper bonding pad region. The lower semiconductor die includes a first lower bonding pad disposed in a first lower bonding pad region; and a second lower bonding pad disposed in a second lower bonding pad region. The second upper bonding pad and the first lower bonding pad are vertically aligned and directly bonded to each other. The second upper bonding pad and the first lower bonding pad are not electrically connected to an upper electrical circuit in the upper semiconductor die, and electrically connected to a lower electrical circuit in the lower semiconductor die.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 21/66 - Testing or measuring during manufacture or treatment
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

88.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

      
Application Number 18108953
Status Pending
Filing Date 2023-02-13
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kang, In Ku

Abstract

Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.

IPC Classes  ?

  • H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels

89.

CMOS DEVICE, METHOD OF MANUFACTURING CMOS DEVICE, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING CMOS DEVICE

      
Application Number 18113543
Status Pending
Filing Date 2023-02-23
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lee, Dong Uk
  • Yang, Hae Chang

Abstract

A CMOS device, and a method of manufacturing the same, includes a semiconductor substrate and a trench formed in the semiconductor substrate. The CMOS device also includes an oxide semiconductor layer disposed in the trench, the oxide semiconductor layer including a source region, a drain region, and a channel region between the source region and the drain region. The CMOS device further includes a buffer layer between the oxide semiconductor layer and the semiconductor substrate, a gate insulating layer on the oxide semiconductor layer, a gate electrode disposed on the gate insulating layer over the channel region of the oxide semiconductor layer, and impurities distributed in each of the source region and the drain region of the oxide semiconductor layer.

IPC Classes  ?

  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

90.

SEMICONDUCTOR DEVICE

      
Application Number 18117961
Status Pending
Filing Date 2023-03-06
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jae Taek

Abstract

A semiconductor device includes a substrate, a source structure disposed on the substrate, and cell stack structures disposed on the source structure. The semiconductor device also includes a dummy stack structure disposed between the cell stack structures on the source structure and vertical barriers disposed between the dummy stack structure and the cell stack structures. The semiconductor device further includes at least one lower protective pattern disposed at a lower portion of the dummy stack structure between the vertical barriers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

91.

MEMORY CONTROLLER INCLUDING MEMORY MANAGER FOR MAPPING BUFFER IDNENTIFIER TO SEGMENT

      
Application Number 18151429
Status Pending
Filing Date 2023-01-07
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Lim, Tae Ho
  • Park, Ie Ryung
  • Lee, Dong Sop
  • Park, Youn Won
  • Jang, Jae Min

Abstract

A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

92.

DATA STORAGE DEVICE PERFORMING DATA PROTECTION AND HOST DEVICE SUPPORTING A DATA PROTECTION FUNCTION USING A PROGRAM CONTEXT

      
Application Number 18162583
Status Pending
Filing Date 2023-01-31
First Publication Date 2024-02-29
Owner
  • SK hynix inc. (Republic of Korea)
  • Seoul National University R&DB Foundation (Republic of Korea)
Inventor
  • Lee, Sanggu
  • Kim, Jihong

Abstract

A data storage device includes a memory device including a whitelist storing one or more program contexts for identifying input/output (I/O) operation, and a control circuit including a whitelist managing circuit configured to determine whether a write request is allowable by comparing the whitelist with one or more program contexts transmitted with the write request from a host. The program contexts may be generated using program counter values corresponding to call operations performed by the I/O operation.

IPC Classes  ?

  • G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
  • G06F 21/55 - Detecting local intrusion or implementing counter-measures
  • G06F 21/56 - Computer malware detection or handling, e.g. anti-virus arrangements

93.

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

      
Application Number 18177760
Status Pending
Filing Date 2023-03-03
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Yoon, Young Gwang

Abstract

A semiconductor device includes a first gate stack and a second gate stack disposed on a substrate. The first gate stack includes a first lower gate insulating layer. The second gate stack includes a second lower gate insulating layer. The first lower gate insulating layer includes silicon oxide with a first dipole material. The second lower gate insulating layer includes silicon oxide with a second dipole material. The first dipole material and the second dipole material are different from each other.

IPC Classes  ?

  • H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
  • H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
  • H01L 29/51 - Insulating materials associated therewith
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

94.

MAC OPERATOR RELATED TO CORRECTING A COMPUTATIONAL ERROR

      
Application Number 18188145
Status Pending
Filing Date 2023-03-22
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Seong Ju

Abstract

A multiplication and accumulation (MAC) operator includes a data input circuit configured to receive first operands and second operands and configured to output the first operands and third operands, a multiplication circuit configured to generate multiplication data by performing a multiplication operation on the first operands and the third operands, an addition circuit configured to generate multiplication addition data by performing an addition operation on the multiplication data, an accumulating circuit configured to generate accumulative data by performing an accumulative addition operation on the multiplication addition data and feedback data, and an error correction circuit configured to detect a computational error in the accumulative data when a computational error occurs, and configured to output, as MAC result data, accumulative data having the computational error corrected.

IPC Classes  ?

  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
  • G06F 7/50 - Adding; Subtracting
  • G06F 7/523 - Multiplying only
  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

95.

PROCESSING-IN-MEMORY (PIM) DEVICE, CONTROLLER FOR CONTROLLING THE PIM DEVICE, AND PIM SYSTEM INCLUDING THE PIM DEVICE AND THE CONTROLLER

      
Application Number 18502796
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor Song, Choung Ki

Abstract

A processing-in-memory (PIM) device includes a plurality of multiplication/accumulation (MAC) operators and a plurality of memory banks. The MAC operators are included in each of a plurality of channels. Each of the plurality of MAC operators performs a MAC arithmetic operation using weight data of a weight matrix. The memory banks are included in each of the plurality of channels and are configured to transmit the weight data of the weight matrix to the plurality of MAC operators. The weight data arrayed in one row of the weight matrix are stored into one row of each of the plurality of memory banks.

IPC Classes  ?

  • G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06F 7/523 - Multiplying only
  • G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation

96.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

      
Application Number 18503809
Status Pending
Filing Date 2023-11-07
First Publication Date 2024-02-29
Owner SK hynix Inc. (Republic of Korea)
Inventor
  • Seo, Moon Sik
  • Yun, Dae Hwan

Abstract

A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
  • H10N 70/00 - Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching

97.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

      
Application Number 18182361
Status Pending
Filing Date 2023-03-13
First Publication Date 2024-02-22
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Jun Sik

Abstract

A semiconductor device includes: an isolation layer formed to define active regions including active fins in a substrate; gate trenches extending across the active fins and the isolation layer; and buried gates that fill the gate trenches, and include fin gates disposed on sidewalls of the active fins, active gates disposed over the active fins, and passing gates disposed over the isolation layer, wherein bottom surfaces of the passing gates are disposed at a higher level than bottom surfaces of the active gates, and bottom surfaces of the fin gates are disposed at a lower level than the bottom surfaces of the active gates.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

98.

HEAVY-DUTY PROBE CARD TRANSFER AND LOADING DEVICE

      
Application Number 18451838
Status Pending
Filing Date 2023-08-18
First Publication Date 2024-02-22
Owner
  • Gosung engineering Co., Ltd (Republic of Korea)
  • SK hynix Inc. (Republic of Korea)
Inventor
  • Kim, Ki Tae
  • Lee, Jung Shik
  • Kim, Dae Han
  • Jang, Woon Seap
  • Park, Sang Kyun
  • Oh, Dong Hyug

Abstract

Provided is a heavy-duty probe card transfer and loading device including a main body that moves along a set travel route, a loading arm assembly including an up-down unit coupled to the main body and configured to perform a lifting and lowering operation, a first arm drive unit rotatably coupled to the up-down unit, and a second arm drive unit rotatably coupled to the other end of the first arm drive unit, and a gripper unit rotatably coupled to the second arm drive part to grip a heavy-duty probe card and place the same on the main body.

IPC Classes  ?

  • H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations

99.

PIPE LATCH CIRCUIT, OPERATING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

      
Application Number 18501432
Status Pending
Filing Date 2023-11-03
First Publication Date 2024-02-22
Owner SK hynix Inc. (Republic of Korea)
Inventor Kim, Bo Kyeom

Abstract

A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.

IPC Classes  ?

  • G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C 7/22 - Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

100.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

      
Application Number 18501854
Status Pending
Filing Date 2023-11-03
First Publication Date 2024-02-22
Owner SK hynix Inc. (Republic of Korea)
Inventor Lee, Nam Jae

Abstract

A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.

IPC Classes  ?

  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
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