There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of sub-blocks; a peripheral circuit for performing first program and erase operations in a first manner in a first sub-block, among the plurality of sub-blocks, and performing second program and erase operations in a second manner in a second sub-block, among the plurality of sub-blocks; and a control circuit configured to, when a cycling number of the second program and erase operations that are performed in the second sub-block is equal to or greater than a reference number, control the peripheral circuit to perform a compensation operation that compensates for a threshold voltage of memory cells included in the first sub-block.
Provided herein may be a memory system and a host device. The memory system may include a first memory module communicating with a host through a first interface and a second memory module communicating with the host through a second interface. The second memory module may include a memory device configured to store data and a memory controller configured to update at least one of first metadata related to a space-locality and second metadata related to a time-locality based on a result of comparing the numbers of the pages respectively corresponding to a first trigger address and a second trigger address sequentially input from the host, and to prefetch, to the first memory module, the data determined based on the first metadata and the second metadata. The first and second trigger addresses are addresses corresponding to data for which access to the first memory module is missed.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
3.
MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE
Provided herein is a memory device and a method of operating the memory device. The memory device includes memory cells, a peripheral circuit configured to perform an intermediate program operation and a final program operation on the memory cells, and a program operation controller configured to control the peripheral circuit to perform an extra program operation, after the final program operation is performed, on under programmed cells having threshold voltages, lower than an extra verify voltage lower than a main verify voltage used in the final program operation among the memory cells.
A storage device includes a memory device and a controller. The memory device includes a memory region configured by a plurality of memory cells. The controller is configured to set at least one prohibited threshold voltage distribution for the memory region based on a result of an operation on the memory region.
An image sensing device includes: a control circuit coupled between an output terminal of a pixel signal and a high voltage terminal, and configured to generate a control voltage corresponding to a voltage level of the pixel signal; and a current supplying circuit coupled between the output terminal and the high voltage terminal, and configured to supply a pre-charge current, which is configured to be adaptively adjusted according to the voltage level of the pixel signal, to the output terminal based on the control voltage.
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 25/62 - Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
H04N 25/709 - Circuitry for control of the power supply
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
6.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
An error processing circuit includes: a first H matrix calculation circuit configured to calculate a first H matrix and upstream data to generate a partial first parity, during an encoding operation; a second H matrix calculation circuit configured to calculate a second H matrix and the upstream data to generate a second parity, during the encoding operation; and a parity calculation circuit configured to sum the partial first parity and the second parity to generate a first parity, during the encoding operation.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
A semiconductor system includes a controller configured to output a command address, data, and a write clock and an inverted write clock for latching the data through a channel, configured to output the write clock and the inverted write clock having a first set level and a second set level, respectively, by incorporating information with regard to characteristics of the channel during a pre-level interval, and configured to output the write clock and the inverted write clock that periodically toggle during a toggle interval, and a semiconductor device configured to latch and store the data in synchronization with the write clock and the inverted write clock.
An image processing device including: a gain value manager for generating white gain values corresponding to a plurality of positions, based on a sensing result of a predetermined white image; a target pixel manager for detecting saturated pixels, based on pixel values received from an external device, and determining target pixels as saturated white pixels of which each have a pixel value that indicates that the saturated white pixel is saturated, based on peripheral pixels of the saturated white pixels among the detected saturated pixels; and a target pixel corrector for changing pixel values of the target pixels, based on the white gain values and pixel values of the peripheral pixels.
H04N 23/86 - Camera processing pipelines; Components thereof for processing colour signals for controlling the colour saturation of colour signals, e.g. automatic chroma control circuits
G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
G06V 10/74 - Image or video pattern matching; Proximity measures in feature spaces
H04N 23/88 - Camera processing pipelines; Components thereof for processing colour signals for colour balance, e.g. white-balance circuits or colour temperature control
A storage device includes a printed circuit board (PCB) with attached semiconductor chips, each including a memory, and with at least one wire coupling the semiconductor chips. The storage device includes a case including a first case surrounding a top portion of the printed circuit board and a second case surrounding a bottom portion of the printed circuit board. A sidewall of the first case and a protrusion of the second case form a concavo-convex structure. The sidewall of the first case and the protrusion of the second case cover a side of the printed circuit board.
A method is provided in which a core processor located adjacent to a memory and processing data of the memory in a proximity data processing scheme reads and processes the data of the memory by simultaneously using a plurality of channels used by the memory. Since data processing is performed simultaneously using a total bandwidth between the memory and the core processor, the efficiency of the proximity data processing scheme by the core processor may be improved.
A method for fabricating a semiconductor device includes forming a stack body over a substrate; forming a sacrificial vertical structure including a double spacer in a first region of the stack body; forming a separation slit including a single spacer in a second region of the stack body to be spaced apart from the sacrificial vertical structure; forming a vertical opening in the first region of the stack body by removing the sacrificial vertical structure; and forming a vertical conductive line filling the vertical opening.
A memory device comprises: a plurality of memory blocks each including a plurality of word lines, a control operation circuit suitable for performing a read operation on each of the plurality of word lines, and a control logic suitable for: storing a plurality of default levels, which respectively correspond to the memory blocks, in an information storage region therein, controlling the control operation circuit to perform one of a first read operation using a selected default level corresponding to a selected block and a second read operation using an adjusted level smaller than the selected default level, resetting the adjusted level to the selected default level when a number of times that the second read operation is passed is greater than a number of times that the first read operation is passed, by a reference number of times or more, and storing the reset level in the information storage region.
A storage device may include: a plurality of memory dies; and a memory controller for receiving a first read request from a first function, controlling at least one memory die to perform a read operation according to the first read request, and controlling, when receiving a second read request from a second function in the course of the read operation according to the first read request, the at least one memory die to suspend the read operation according to the first read request and to perform a read operation according to the second read request based on a result obtained by comparing performance requirement information of the second function with residual time information of the second read request, which is determined according to a performance degree of the read operation being performed according to the first read request.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.
A memory controller includes: a request buffer storing read and write requests of a first rank, and read and write requests of a second rank; an arbiter determining a first request and second requests among the stored requests, the second requests to be issued after the first request according to a descending priority, such that a B request has a higher priority than a C request among the second requests; and a command generator generating commands to be issued to the first rank and the second rank according to the issue order of the first and second requests, wherein the B request is a command whose type and rank are different from those of the first request, and wherein the C request is a command whose type is the same as the type of the first request and whose rank is different from the rank of the first request.
In an embodiment, a semiconductor wafer includes an alignment key structure disposed over a substrate, a contact pattern layer disposed on the alignment key structure to extend upward of the alignment key structure, and an insulating layer in contact with the alignment key structure and the contact pattern layer over the substrate.
A leakage current detection circuit includes: a mirror circuit configured to copy a leakage current flowing through a node and generate a copy current in a copy node; an oscillation circuit including a charge storage unit, the oscillation circuit being connected to the copy node, charged with the copy current, and configured to generate an oscillation signal by charging and discharging the charge storage unit; and a calculation circuit configured to calculate an amount of the leakage current based on the oscillation signal.
A pooled memory device includes plural memory devices and a controller. The plural memory devices include a first memory and a second memory with at least one power supply configured to control power supplied to each of the plural memory devices. The controller is coupled to an interconnect device which is configured to provide the plural memory devices to at least one external device as a logical device. The controller is configured to track available storage capacities of the first memory and the second memory and cut off power supplied to an unused memory among the first memory and the second memory.
A training system includes a dynamic random access memory (DRAM) configured to buffer training data; a central processing unit (CPU) coupled to the DRAM and configured to downsample the training data and provide the DRAM with the downsampled training data; a computational storage consisting of a solid-state drive (SSD) and field-programmable gate array (FPGA) and configured to perform dimensionality reduction on the downsampled training data to generate training data batches; and a graphic processing unit (GPU) configured to perform training on the training data batches.
Disclosed is a memory system including a memory device including a plurality of memory blocks; and a controller suitable for performing a garbage collection operation by: moving, when a first victim block related to map data stored in an external device is included in a plurality of victim blocks selected from the plurality of memory blocks, one or more pieces of valid data from the first victim block to a temporary block, which is a free block among the plurality of memory blocks, erasing the first victim block to set the first victim block as a first target block, and moving first valid data, which correspond to the map data stored in the external device among the valid data, from the temporary block to an original location within the first target block, wherein the first valid data is originally stored in the original location before the garbage collection operation.
A storage device includes a memory device including a memory block including memory regions, and a controller configured to store read results of read operations by performing the read operations on the memory regions, to determine first reference values of the memory regions, respectively, based on the read results, to determine a second reference value of the memory block based on the first reference values, and to determine whether the memory block is a potential bad block based on the second reference value. Each of the read results is the number of error bits that are included in data that has been read from the memory region in a corresponding read operation, each of the first reference values is the smallest value among the read results of a plurality of read operations for a corresponding memory region, and the second reference value is the greatest value among the first reference values.
The present technology may include: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.
An operating method of a non-volatile memory device includes simultaneously performing a program operation on a plurality of selection transistors included in a plurality of cell strings each including a corresponding selection transistor of the selection transistors and a plurality of memory cells, each of the cell strings being coupled between a common source line and a corresponding bit line of a plurality of bit lines; sequentially performing verification operations on respective groups of the selection transistors, the groups being coupled to respective selection lines; and sequentially storing results of the verification operations into respective data latch circuits within each of a plurality of page buffers coupled to the bit lines.
A memory system may include: a memory device configured to store first training information and second training information representing different training patterns; and a memory controller configured to: perform a first training operation on the memory device based on the first training information, and perform, when a result of the first training operation is out of a predetermined range, a second training operation on the memory device plural times based on the second training information.
A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.
A decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. The decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.
A memory system includes a memory device and a controller. The memory device includes a plurality of memory cells. The controller is configured to select first map data entries associated with first data entries stored in a first region of the memory device that includes some of the plurality of memory cells, to exclude a second map data entry associated with second data entry sequentially read from among the first map data entries, and to transmit a remaining first map data entry to an external device.
A single memory package includes a package substrate; at least one of a memory chip and a buffer chip mounted on the package substrate; M×N number of interface data channel buses between the memory chip and the buffer chip; and (M×N)/2n number of outer data channel buses connected to the buffer chip. The buffer chip receives data from the memory chip through the interface data channel buses, and provides the data through the outer data channel buses. The M, N, and n are natural numbers.
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
30.
STACK PACKAGE INCLUDING INSERT DIE FOR REINFORCEMENT
A stack package includes a first die stack including first dies, a second die stack including second dies, and an insert die between the first die stack and the second die stack, wherein the insert die is thicker than each of the first and second dies.
A semiconductor device includes: a source structure comprising a cell area and an edge area; a stack located on the edge area of the source structure; a gate structure located on the cell area of the source structure; a channel structure connected to the cell area of the source structure by extending through the gate structure; and a read-only memory area.
A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.
A test device may include a test memory device, an insulation layer and a charge injection electrode. The test memory device may include a memory layer and a gate electrode layer on a semiconductor substrate. The insulation layer may be arranged on the test memory device. The charge injection electrode may be arranged on the insulation layer to inject a charge into the test memory device based on a voltage.
A decoding device may determine a candidate data unit among a plurality of data units included in one data chunk, in parallel with an operation of decoding a target data unit among the plurality of data units. The decoding device may determine whether to decode the candidate data unit, and may decode the candidate data unit according to whether to decode the candidate data unit, after executing decoding on the target data unit.
Electronic device and operation method for an electronic device are provided. In the electronic device, a specific number of protocol data units (PDUs) are received as a PDU block to be transmitted. The PDU block includes at least one PDU belonging to a control PDU category. A control block is generated according to the PDU block by reordering, wherein the control block includes a header being placed before all PDUs of the PDU block and indicating a control block category; in the control block, any PDU belonging to the control PDU category in the PDU block is placed after the header and before any PDU belonging to a data PDU category in the PDU block. The control block is transmitted through the electronic device to another electronic device according to an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding.
A method for facilitating frame error handling and an electronic device are provided. The method is for use in an electronic device capable of communicating with another electronic device. The method comprises the following. In response to an error event in an advanced line encoding mode, closing a first burst transmission and opening a second burst transmission are performed, wherein the advanced line encoding mode indicates that the electronic device is capable of data transmission by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. A lane alignment pattern is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the second burst transmission is opened. A negative acknowledgement control frame is transmitted in the advanced line encoding mode from the electronic device to the other electronic device after the lane alignment pattern is transmitted.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
37.
METHOD FOR CONTROL PROTOCOL FRAME TRANSMISSION AND ELECTRONIC DEVICE
Method for control protocol frame transmission and electronic device are provided. The method comprises following operations. By the electronic device operating in an advanced line encoding mode and having a first burst from the electronic device to the other electronic device, the first burst is closed and a second burst is opened from the electronic device to the other electronic device for request frame transmission, wherein the electronic device operating in the advanced line encoding mode is configured to transmit data by using an advanced line encoding having an effective data rate larger than an effective data rate of 8b/10b encoding. By the electronic device, a request frame is transmitted in the second burst.
A memory device includes: a first memory cell mat that includes first multi-layer level sub word lines positioned over a substrate; a second memory cell mat that is laterally spaced apart from the first memory cell mat and includes second multi-layer level sub word lines; a first sub word line driver circuit that is positioned underneath the first memory cell mat; and a second sub word line driver circuit that is positioned underneath the second memory cell mat, wherein the first sub word line driver circuit is positioned underneath ends of the first multi-layer level sub word lines, and the second sub word line driver circuit is positioned underneath ends of the second multi-layer level sub word lines.
A semiconductor device and a method of fabricating the same are provided. According to the present invention, a semiconductor device comprises an active region formed in a substrate, and including flat surfaces and hole-shaped recess portions; upper-level plugs disposed over the flat surfaces; a spacer disposed between the upper-level plugs and providing a trench exposing the hole-shaped recess portions; a lower-level plug filling the hole-shaped recess portions; and a buried conductive line disposed over the lower-level plug and partially filling the trench.
A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor device includes a self-test circuit configured to generate an internal clock having a higher frequency than a clock applied from a device external to the semiconductor device, to generate an instruction signal from a pre-instruction signal extracted through a data line, and to generate an internal control signal from the instruction signal. The semiconductor device also includes a command control circuit configured to generate a test command to perform a self-test for determining whether a defect has occurred in first memory cells and second memory cells based on the internal clock and the internal control signal. The semiconductor device further includes a data control circuit configured to output data stored in the first memory cells based on the test command, and to store data output from the first memory cells in the second memory cells.
A sensing and amplifying circuit includes a driving voltage control circuit configured to control a voltage level of a driving voltage based on a surrounding temperature of the sensing and amplifying circuit, a delay control circuit configured to generate a line connection signal and an inverted line connection signal in response to a delay start signal by being supplied with the driving voltage, and a sense amplifier configured to perform a sensing and amplifying operation in response to the line connection signal and the inverted line connection signal. An interval between enable timing of the line connection signal and enable timing of the inverted line connection signal is adjusted as the surrounding temperature changes.
H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
An image sensor includes: a unit pixel configured to output pixel data in response to a drive signal being input to the unit pixel; and a control circuit configured to provide the unit pixel with a first drive signal and a second drive signal each having a first phase, and a third drive signal having a second phase with a phase difference of 180 degrees with respect to the first phase in a first mode, the control circuit providing the unit pixel with the first drive signal having the first phase, the second drive signal having the second phase, and the third drive signal having a deactivation voltage in a second mode.
G01S 7/4914 - Detector arrays, e.g. charge-transfer gates
G01S 17/36 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
G01S 17/894 - 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
A memory device includes a memory cell array including a plurality of rows; a time table including a plurality of fields respectively corresponding to the rows; and a refresh control circuit configured to read field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, determine whether to issue a refresh request signal for the k-th row based on current clock data and the field data, and update the field data of the k-th field using the current clock data.
A shift array circuit generates output data having the number of bits greater than the number of bits of target data by shifting the target data by a bit corresponding to a value of shift data. The shift array circuit includes a plurality of shift arrays. The plurality of shift arrays is configured to receive bits of the shift data for each bit and each configured to perform a shift operation on input data that is input to each of the plurality of shift arrays by a shift bit corresponding to an input bit, among the bits of the shift data.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
46.
SUBSTRATE HAVING A DIE POSITION MARK AND A SEMICONDUCTOR DIE STACK STRUCTURE INCLUDING SEMICONDUCTOR DIES STACKED ON THE SUBSTRATE
A substrate includes: a first die alignment mark and a first die position mark defining a die stack region. The first die alignment mark has substantially a cross shape having substantially a vertical bar and substantially a horizontal bar intersecting each other substantially perpendicularly, and the first die position mark includes a first main position mark having a first area and a first branch position mark having a second area different from the first area.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
47.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a first seed layer in the opening; forming a first buffer layer by surface-treating the first seed layer; and forming a blocking layer by oxidizing the first seed layer through the first buffer layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
48.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device may include: first insulating pillars arranged in a first direction; second insulating pillars arranged alternately with the first insulating pillars and having a first width in the first direction and a second width in a second direction intersecting the first direction, the first width being greater than the second width; first memory cells located between the second insulating pillars and stacked along a first sidewall of each of the first insulating pillars; and second memory cells located between the second insulating pillars and stacked along a second sidewall of each of the first insulating pillars.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A metal wiring of a semiconductor device may include: a first metal line disposed in a first metal layer, and defined with an opening in a first region; and a contact metal passing through a dielectric layer under the first metal layer adjacent to the opening and connected to the first metal line around the opening.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
50.
SYSTEM, METHOD FOR CIRCUIT VALIDATION, AND SYSTEM AND METHOD FOR FACILITATING CIRCUIT VALIDATION
System, method for circuit validation, and system and method for facilitating circuit validation are provided. The circuit validation system comprises a prototype system and a computing device. The prototype system comprises a programming logic device circuit configured to implement a modified circuit design. The modified circuit design includes a circuit module as a design under test (DUT), an input generation circuit coupled to the circuit module for outputting input signals to the circuit module in response to a test signal, and an output acquisition circuit coupled to the circuit module for storing output data from the circuit module. The computing device is capable of being coupled to the prototype system and configured to generate the test signal to perform a test of the DUT on the prototype system.
Method for facilitating testing for an interconnection protocol, a controller, and an electronic device are provided. The method is suitable for an electronic device capable of communicating with another electronic device. The method comprises the following steps. At a controller of the electronic device, a test mode request signal is received to enter a test mode in which data transmission is to be performed by using an advanced line encoding having an improved effective data rate as compared to 8b/10b encoding. At the controller, a test data signal is generated to indicate a test pattern including an ordered set portion and a data pattern portion by using the advanced line encoding. The test data signal is transmitted according to the advanced line encoding through the electronic device to the other electronic device.
According to embodiments of the present disclosure, there may be provided a memory system and an operating method thereof, including a host accessible area accessible directly from an external device, transmitting information on the host accessible area to an external memory, receiving a direct memory access request generated based on the information for the host accessible area from the external device according to an urgent event, and providing the external device with a direct memory access to the host accessible area in response to the direct memory access request.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
53.
Semiconductor device including on-die resistor and method of calibrating on-die resistor
A semiconductor device includes an on-die resistor circuit comprising an on-die resistor, a calibration circuit configured to perform a calibration operation on the on-die resistor, and a calibration control circuit configured to control the calibration operation of the calibration circuit. The calibration circuit includes a current generating circuit configured to supply a calibration current to the on-die resistor and a comparing circuit configured to compare the magnitude of a first input signal that is generated by the calibration current and the on-die resistor with a magnitude of a second input signal that is generated by the calibration current and an external resistor.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
54.
ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION
An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.
Disclosed is an image sensor including a first tap pixel, a second tap pixel, and an overflow detection circuit suitable for detecting overflow of the first tap pixel based on a first tap pixel signal outputted from the first tap pixel and overflow of the second tap pixel based on a second tap pixel signal outputted from the second tap pixel, and forming a current path from an overflow current source to a ground voltage terminal when a voltage of the first tap pixel signal or a voltage of the second tap pixel signal drops below a predetermined voltage.
A semiconductor device includes: an inter-layer dielectric layer over a substrate including a cell region, a first peripheral region, and a second peripheral region; a capping layer over the inter-layer dielectric layer; a capacitor capped by the inter-layer dielectric layer in the cell region; a contact plug penetrating the inter-layer dielectric layer in the first peripheral region; a metal interconnection formed over the contact plug through the capping layer; and a through electrode penetrating the capping layer and the inter-layer dielectric layer and extending into the substrate in the second peripheral region.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
57.
NON-UNIFORM QUANTIZATION FOR FLEXIBLE POWER-OF-TWO COMPUTATIONS IN NEURAL NETWORKS
Devices, systems, and methods for improving operation of a memory device that uses a deep neural network (DNN), based on using non-uniform quantization for flexible power-of-two computations, are described. An example method includes receiving a plurality of initial weights of the DNN configured to determine a value of a read voltage associated with memory device, wherein the plurality of initial weights comprises at least one non-power-of-two quantized value or at least one floating point value. The method then aggregates the plurality of initial weights to generate a plurality of quantization functions, determines each of a plurality of quantized weights for a corresponding one of the plurality of quantization functions such that each of the plurality of quantized weights is a sum of powers-of-two, and configures the DNN to use the plurality of quantized weights to generate an updated value of the read voltage for retrieving information from the memory device.
To improve error correction when errors occur in consecutive bits of user data, the user data can be stored in an interleaved manner. Data of a data unit can be interleaved to generate a permutated data unit. A checksum of the permutated data unit can then be calculated, and an error correction code can be generated over the data unit and the checksum. The error correction code can also be interleaved to generate a permutated error correction code. The permutated data unit, the checksum, and the permutated error correction code can then be concatenated to generate a storage data unit for storage in a memory.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
A method of manufacturing a semiconductor device includes forming a first photoresist layer on a substrate and forming a second photoresist layer on the first photoresist layer. The method also includes forming a first dissolvable region having a first width in the first photoresist layer and a second dissolvable region having a second width different from the first width in the second photoresist layer by radiating exposure light to some parts of the second and first photoresist layer. The method further includes forming a second opening in the second photoresist layer and a first opening in the first photoresist layer by developing the second dissolvable region and the first dissolvable region. The method additionally includes forming a conductive bump that fills the first and second openings.
A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.
H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
A semiconductor device according to an embodiment includes a first stacked structure including a first base body, a first connection pad disposed over a surface of the first base body, and a first pad buffer layer disposed adjacent to the first connection pad and the first pad buffer layer including an insulating material having a porous structure. In addition, the semiconductor device includes a second stacked structure including a second base body, a second connection pad disposed over a surface of the second base body, and a second pad buffer layer disposed adjacent to the second connection pad and the second pad buffer layer including an insulating material having a porous structure. The semiconductor device includes a connection portion of the first and second stacked structures that connects the first and second connection pads.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
Disclosed is an image sensor including a buffer circuit suitable for generating, based on at least one first signal, at least one second signal controlled during each of settling and comparison periods, a comparison circuit suitable for using an operating current having a relatively high level during the settling period and a relatively low level during the comparison period based on the second signal, and comparing a pixel signal with a ramp signal during the comparison period to generate a comparison signal.
An image sensing device includes a pixel array configured to include a plurality of pixel groups consecutively arranged in row and column directions. Each of the pixel groups includes a plurality of unit pixels and each unit pixel includes a photoelectric conversion element structured to generate photocharges through a conversion of incident light. Each pixel group outputs a first pixel signal corresponding to photocharges generated by a single unit pixel and a second pixel signal corresponding to a sum of photocharges generated by two or more unit pixels.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
64.
POWER DISTRIBUTION NETWORK AND SEMICONDUCTOR DEVICE
Various embodiments generally relate to a power distribution network and a semiconductor device, which may include: a plurality of chip pads; a first distribution layer in which a plurality of first conductive lines having rectangular shapes of different sizes, respectively, are disposed; a second distribution layer in which a plurality of second conductive lines including a central cross-shaped conductive line and L-shaped conductive lines open toward respective corners of the second distribution layer are disposed; and a redistribution layer electrically coupling chip pads to which power is applied among the plurality of chip pads and the first conductive lines of the first distribution layer.
A memory device includes a memory cell region including a plurality of rows; a row-hammer control circuit including first and second queues, and configured to: read counting data from a row indicated by a row address according to an active command, store the row address in the first queue according to a comparison result of the counting data and a first set value, store the row address in the second queue according to a comparison result of the counting data and a second set value, and select, as a row-hammer address according to a refresh management command or a target refresh command, one of the row addresses stored in the first queue and the second queue; and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command.
A semiconductor memory device may include a plurality of memory blocks and at least one insulation bridge. The plurality of the memory blocks may be defined by a plurality of slits parallel to each other. The at least one insulation bridge may be formed in at least one slit located on at least one side of a memory block of the plurality of memory blocks to support the adjacent memory blocks.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
67.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
A process of forming a 3D memory device includes forming a stacked structure with a plurality of stacked layers, etching the stacked structure to form stepped trenches each comprising a plurality of steps, forming a hard mask layer with a plurality of openings over the stepped trenches, forming a photoresist layer over the hard mask layer, and etching through the plurality of openings using the hard mask layer and the photoresist layers as an etch mask to extend a bottom of the stepped trenches to a lower depth.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
68.
PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICE AND OPERATING METHOD THEREOF
An SSD device comprises a first port linking up with a first host using a first link, a second port linking up with the first host or a second host using a second link, and a port mode controller controlling the first port and the second port to change an operating mode from a dual port mode, in which the first port and the second port operate independently of each other, to a single port mode, in which only the first port operates. The port mode controller controls the second port to reset the second link in a state where the first link is linked up.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
69.
OUT-OF-ORDER BIT-FLIPPING DECODERS FOR NON-VOLATILE MEMORY DEVICES
Devices, systems, and methods for reducing a latency of a decoder in a non-volatile memory are described. An example method includes receiving a noisy codeword that is based on a transmitted codeword generated from a low-density parity-check (LDPC) code, the LDPC code having an associated parity matrix comprising a plurality of columns of circulant matrices, performing a sorting operation that sorts the plurality of columns of circulant matrices in a descending order of a first quality metric to generate a plurality of sorted columns of circulant matrices, the first quality metric indicative of a number of errors in a corresponding column of circulant matrices, and iteratively processing the plurality of sorted columns of circulant matrices to determine a candidate version of the transmitted codeword.
A single memory package includes: a substrate; and a memory chip and a buffer chip that are integrated over the substrate, wherein the memory chip includes an interface modulator embedded therein, and the interface modulator is a serializing modulator including a multi-level amplitude modulator.
An image processing device including: a decision pixel manager for setting a decision area for a defect candidate pixel, and determining a first decision pixel and a second decision pixel, based on first phase information of pixels included in the decision area with respect to a first modulation frequency of a sensing light source among the pixels; a target pixel determiner for calculating a phase difference between the first decision pixel and the second decision pixel, based on second phase information of the pixels with respect to a second modulation frequency of the sensing light source, and determining the defect candidate pixel as a target pixel, corresponding to that the phase difference exceeds a predetermined reference value; and a phase corrector for changing a phase of the target pixel, based on the phase difference.
H04N 25/683 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to defects by defect estimation performed on the scene signal, e.g. real time or on the fly detection
H04N 25/704 - Pixels specially adapted for focusing, e.g. phase difference pixel sets
H04N 25/705 - Pixels for depth measurement, e.g. RGBZ
72.
STORAGE DEVICE, HOST DEVICE, AND ELECTRONIC DEVICE
An electronic device may include a storage device including a memory device configured to store data which includes map data including a plurality of map segments and a memory controller configured to be in communication with the memory device; and a host device configured to be in communication with the storage device and structured to include a host memory and configured to transmit, to the storage device, a request for one or more of the plurality of map segments from the storage device, wherein the memory controller of the storage device is configured to provide the one or more map segments to the host memory in the host device in response to the request from the host device, and wherein the host device is configured to transmit, to the storage device, a command requesting access to the memory device based on the one or more map segments.
Provided herein may be a memory controller and a memory system including the same. The memory system may include a plurality of memory devices, each including a plurality of zone blocks, a buffer memory configured to store pieces of map data that are respectively allocated to a plurality of zones corresponding to logical address groups provided by a host and that indicate correspondence relationships between the plurality of zones and physical addresses of the plurality of zone blocks, and a memory controller configured to perform a data movement operation of storing data, which is stored in a zone block allocated to one of the plurality of zones, in an additional zone block based on information related to the plurality of zone blocks, and update a physical address of the zone block corresponding to the one zone to a physical address of the additional zone block.
A semiconductor memory device includes a channel layer coupled to a bit line, a cell string located along a first side portion of the channel layer, and an auxiliary string located along a second side portion of the same channel layer.
The present disclosure relates to a storage device including a memory device to which a namespace including a plurality of zones is applied, a cache memory caching a media encryption key corresponding to each of a plurality of key tags, an encryptor encrypting data subject to a write request in response to a command input from a host by using a media encryption key corresponding to a key tag included in the command, and outputting encrypted data, and a write operation controller controlling the memory device to store the encrypted data in the memory device, wherein the media encryption key is a second media encryption key generated based on a first media encryption key provided from the host and a Root of Trust (RoT) generated from the encryptor.
Variable resistance elements and semiconductor devices including the variable resistance elements are disclosed. In some implementations, a variable resistance element may include a variable resistance element may include a free layer having a variable magnetization direction that switches between different magnetization directions upon application of a magnetic field, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer and including a metal chalcogenide having a cubic crystal structure.
A memory controller includes: a data separator configured to separate host write data into upper data and lower data; an address generator configured to generate a first address and a second address based on a host address; a command generator configured to generate one or more first commands for writing the upper data into a first storage region that is selected based on the first address in a memory, and one or more second commands for writing the lower data into a second storage region that is selected based on the second address in the memory; and a control block configured to control the address generator and the command generator to make a difference in power consumption between the first storage region and the second storage region.
POSTECH ACADEMY-INDUSTRY FOUNDATION (Republic of Korea)
Inventor
Kim, Choong Ki
Byun, Hong Chul
Yun, Hyeok
Baek, Rock Hyun
Abstract
Determining a semiconductor device manufacturing parameter may include determining an EPM (electrical measurement parameters) group that has a correlation in a baseline EPM dataset including EPMs of a device manufactured under a baseline condition, deriving principal components (PCs) corresponding to main correlation axes between EPMs in the EPM group, deriving a PC-based dataset including a baseline PC dataset and a conditional split PC dataset by converting the baseline EPM dataset and a conditional split EPM dataset measured from devices manufactured under conditional splits into a PC domain, determining, using the PC-based dataset, respective PCs which are effectively changed by the conditional splits, obtaining split variation information of the conditional splits, extracting an optimal point capable of optimizing a figure of merit of a semiconductor device within a range of the PC-based dataset, and deriving information for process feedback for realizing the optimal point using the split variation information.
A memory device includes a substrate, an active layer spaced apart from a surface of the substrate and laterally oriented in a first direction and including an opened first side, a closed second side, and a channel layer between the first side and the second side, and a word line laterally oriented in a second direction crossing the first direction while surrounding the channel layer.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A storage device may receive, from an external device, a target read recovery level indicating information on a read command execution completion time and an error recovery amount requested by the external device, may read, from a memory, data requested by a read command transmitted by the external device, and may transmit, to the external device, a response regarding a result of executing the read command transmitted by the external device within the read command execution completion time indicated by the target read recovery level.
A memory device includes a plurality of first cell blocks configured to store first data; a second cell block configured to store second data; a third cell block configured to store third data; a repair information storage circuit configured to output, based on repair information stored therein, a repair use signal corresponding to an input address; and an error correction circuit configured to: receive the second data as a first error correction code from the second cell block while selectively receiving, according to the repair use signal, the third data as a second error correction code from the third cell block, and correct errors in the first data from the first cell blocks using the first and second error correction codes.
A semiconductor device includes a first stacked structure including a first substrate having unit pixels, and a first interconnect layer having first conductive lines connected to the unit pixels; a second stacked structure including a second substrate having first circuit elements configured to operate the unit pixels and a second interconnect layer having second conductive lines connected to the first circuit elements and an electrode pad, and a first interconnection via structure penetrating the second substrate; a third stacked structure including a third substrate having second circuit elements configured to process signals received from the second stacked structure, and a third interconnect layer having third conductive lines connected to the second circuit elements; and a pad open region disposed outside of a pixel region including the unit pixels and exposing a top surface of the electrode pad to outside.
A data storage device includes a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device such that, when a first refresh scan command is received from a host device, a first refresh scan operation for the plurality of memory blocks is performed and then a first refresh scan result for the first refresh scan operation is transmitted to the host device, and when a first refresh operation command is received from the host device, a first refresh operation for the nonvolatile memory device is performed.
A buffer circuit includes a power control circuit, an inverting circuit, and a voltage adjustment circuit. The power control circuit is configured to provide voltages based on an input signal and a mode signal, and the inverting circuit is configured to receive and invert the voltages to generate an output signal. The voltage adjustment circuit is configured to adjust voltage levels based on the mode signal and the output signal.
A method for operating a system including a host and at least one solid state drive (SSD). The method identifies a workload associated with the SSD, recognizes a power state of the SSD, and controls allocation and/or deallocation of hardware resources for the identified workload per a budgeted target for the power state.
A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
87.
CONSTRAINED CLUSTERING ALGORITHM FOR EFFICIENT HARDWARE IMPLEMENTATION OF A DEEP NEURAL NETWORK ENGINE
A method and a system for operating a deep neural network. In the method and system, a subset of floating-point values are used to represent weights in the DNN; the floating-point values are quantized onto a flexible-power-of-two (FPoT) alphabet; values in the FPoT alphabet are listed in a plurality of regions; and an empty region among the plurality of regions is merged to neighbour regions to output dusters of the weights in merged regions, the merged regions having respective centroids and boundary lines in between.
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
A semiconductor device may include a gate structure, a channel structure extending through the gate structure, a first hydrogen supply layer disposed on the gate structure, having a first hydrogen concentration, and comprising an oxygen vacancy, and a hydrogen blocking layer disposed on the first hydrogen supply layer and having a second hydrogen concentration lower than the first hydrogen concentration.
Disclosed is an image sensor including a pixel array having a pixel pattern in which first to fourth 2×2 pixel groups are arranged in a clockwise direction, one infrared pixel is arranged in each of two 2×2 pixel groups that are not adjacent to each other, the same green pixels are arranged in a first diagonal direction, and red pixels and blue pixels are arranged in half in a second diagonal direction crossing the first diagonal direction, in a 4×4 unit pixel group.
H04N 23/667 - Camera operation mode switching, e.g. between still and video, sport and normal or high and low resolution modes
H04N 23/11 - Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths for generating image signals from visible and infrared light wavelengths
H04N 23/84 - Camera processing pipelines; Components thereof for processing colour signals
H04N 25/131 - Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements including elements passing infrared wavelengths
H04N 25/702 - SSIS architectures characterised by non-identical, non-equidistant or non-planar pixel layout
91.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.
A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.
A method for lane synchronization for an interconnection protocol, a controller, and a storage device. The method is suitable for a first device capable of linking to a second device according to the interconnection protocol, and includes providing data representing a de-skew interval which indicates a time interval between two consecutive periodic de-skew patterns. Then performing, by a hardware protocol engine for implementing a link layer of the interconnection protocol, a periodic de-skew pattern transmission adaptively over lanes from the first device to the second device according to the de-skew interval and in response to communication status information between the first device and the second device. The hardware protocol engine is configured to send a de-skew pattern periodically according to the de-skew interval when the communication status information satisfies a criterion, and to postpone sending of the de-skew pattern when the communication status information does not satisfy the criterion.
A semiconductor module includes a semiconductor module body and a guide. The semiconductor module body extends in a first direction and a second direction intersecting the first direction. A plurality of connection terminals is arranged at one end of the semiconductor module in the second direction. A plurality of semiconductor devices is arranged on at least one side of the semiconductor module body. The guide is arranged at the other end of the semiconductor module body opposite to the one end to induce a flow of a cooling fluid toward the one end of the semiconductor module.
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
H01R 12/73 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures connecting to other rigid printed circuits or like structures
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
96.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
A semiconductor device includes: a first semiconductor structure including a first semiconductor substrate, one or more first conductive patterns, a plurality of first conductive plugs, and a first bonding pad; a second semiconductor structure including a second semiconductor substrate, a plurality of second conductive patterns, one or more second conductive plugs, and a second bonding pad; and two through electrodes penetrating the second semiconductor substrate and respectively connected to two second conductive patterns positioned at opposite ends of the plurality of second conductive patterns, wherein the second bonding pad is bonded to the first bonding pad so that the plurality of second conductive patterns, the one or more second conductive plugs, the second bonding pad, the first bonding pad, the plurality of first conductive plugs, and the one or more first conductive patterns form a daisy chain.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
98.
MEMORY SYSTEM PERFORMING GARBAGE COLLECTION OPERATION BY EXCHANGING INFORMATION RELATED TO GARBAGE COLLECTION WITH HOST AND METHOD OF OPERATING THE MEMORY SYSTEM
An electronic device includes a memory system having improved performance. The memory system includes a memory device including memory blocks allocated to zones, a memory controller configured to send, to a host, a request for information on whether to perform a garbage collection operation on a target zone according to a trigger signal for performing a first internal operation, the target zone corresponding to a target memory block on which the first internal operation is to be performed, the target zone being included in the zones, and the host configured to provide the information on whether to perform the garbage collection operation to the memory controller based on information related to the zones, in response to the request. The memory controller determines whether to perform the first internal operation on the target memory block, based on the information on whether to perform the garbage collection operation.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
An image sensing device is provided to include a pixel array having a plurality of pixels arranged in a matrix shape. Each of the pixels includes: a control node configured to generate a hole current in a substrate; a detection node configured to capture photocharge migrated by the hole current, formed in a shape whose at least part is partially open, and disposed to surround the control node, and a low resistance region including a dielectric layer formed in the substrate, and disposed in the opening on of the detection node. The low resistance region includes an inner low resistance region disposed between the control node and the center of the pixel.
There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
patents
