MACOM Technology Solutions Holdings, Inc.

United States of America

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H01L 23/66 - High-frequency adaptations 101
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds 97
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT 95
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation 80
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits 71
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1.

PIN DIODES WITH MULTI-THICKNESS INTRINSIC REGIONS

      
Application Number 18790394
Status Pending
Filing Date 2024-07-31
First Publication Date 2024-11-28
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Boles, Timothy Edward
  • Brogle, James Joseph
  • Bukowski, Joseph Gerard
  • Barter, Margaret Mary

Abstract

A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes a P-type silicon substrate, an intrinsic layer formed on the P-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first N-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second N-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional N-type regions can be formed to other depths.

IPC Classes  ?

  • H01L 29/868 - PIN diodes
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/66 - Types of semiconductor device

2.

HYBRID POWER AMPLIFIER WITH GAN-ON-SI AND GAN-ON-SIC CIRCUITS

      
Application Number 18675839
Status Pending
Filing Date 2024-05-28
First Publication Date 2024-11-28
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Patel, Prity Kirit

Abstract

A power amplifier, such as a radio-frequency (RF) Doherty power amplifier, for amplifying an input signal to an output signal is disclosed. The power amplifier includes a peaking amplifier circuit, where the peaking amplifier circuit is formed in gallium nitride materials on a silicon substrate. The power amplifier further includes a main amplifier circuit, where the main amplifier circuit is formed in gallium nitride materials on a silicon carbide substrate.

IPC Classes  ?

  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H01L 23/66 - High-frequency adaptations
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

3.

COMPONENT CONFIGURED WITH INTRINSIC SHIELDING AND PROCESS OF IMPLEMENTING THE SAME

      
Application Number 18317541
Status Pending
Filing Date 2023-05-15
First Publication Date 2024-11-21
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Bouisse, Gérard

Abstract

A shielded capacitor includes a first terminal; one or more first capacitor metals electrically connected to the first terminal; a second terminal; one or more second capacitor metals electrically connected to the second terminal. The shielded capacitor further includes a shielding structure. The shielding structure being configured to limit a variation of an RF characteristic due to a presence of a metallic structure.

IPC Classes  ?

  • H01G 4/012 - Form of non-self-supporting electrodes

4.

LEVEL SHIFTER WITH EXPANDED VOLTAGE RANGE

      
Application Number 18198275
Status Pending
Filing Date 2023-05-16
First Publication Date 2024-11-21
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Lacombe, David Kenneth
  • Kwan, Kai
  • Ikram, Quazi
  • Bazzani, Cristiano

Abstract

A level shifter, configured to shift an input voltage swing from a first voltage range to a second voltage range, comprising a first stage and a switching stage, with circuitry configured in isolation wells. The first stage includes a first stage input receiving an input signal that swings between a first voltage value and a second voltage, a buffer configured to shift the input signal to vary between a third value and a fourth value, and a first stage output configured to present a first stage output signal. The switching stage comprises switching stage inputs, configured to receive the first stage output signal, switch drivers, and switching devices configured to, responsive to the driver output, generate a switching stage output signal that is a shifted version of the input signal. The switching stage output signal ranges between a fifth voltage value and a sixth voltage value.

IPC Classes  ?

  • H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only

5.

DEVICE HAVING A COUPLED INTERSTAGE TRANSFORMER AND PROCESS IMPLEMENTING THE SAME

      
Application Number 18775169
Status Pending
Filing Date 2024-07-17
First Publication Date 2024-11-07
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Marbell, Marvin

Abstract

A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/495 - Lead-frames
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

6.

TRANSISTOR FEEDBACK CAPACITANCE REDUCTION

      
Application Number 18309320
Status Pending
Filing Date 2023-04-28
First Publication Date 2024-10-31
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Pal, Debdas
  • Kumar, Parshant
  • Bilotta, Stephen
  • Boles, Timothy E.

Abstract

The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.

IPC Classes  ?

  • H01L 29/737 - Hetero-junction transistors
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions

7.

SEMICONDUCTOR MATERIAL WAFERS OPTIMIZED FOR LINEAR AMPLIFIERS

      
Application Number 18685616
Status Pending
Filing Date 2022-08-23
First Publication Date 2024-10-24
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Linthicum, Kevin James
  • Patel, Prity Kirit
  • Roberts, John Claassen
  • Runton, David Walter

Abstract

A number of different types of semiconductor material structures and wafers, including epiwafers, are described herein. The semiconductor material wafers are optimized in certain aspects to form transistor amplifiers for use with new modulation communications systems. A semiconductor material wafer includes a silicon carbide substrate and at least one III-nitride material layer over the silicon carbide substrate. The semiconductor material wafers can include layers consisting of semiconductor materials without dopants such as iron or carbon, formed over the silicon carbide substrate.

IPC Classes  ?

  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation

8.

SOLDERABLE AND WIRE BONDABLE PART MARKING

      
Application Number 18672877
Status Pending
Filing Date 2024-05-23
First Publication Date 2024-09-19
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Barter, Margaret
  • Boles, Timothy

Abstract

A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.

IPC Classes  ?

  • H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions

9.

BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY

      
Application Number US2024019002
Publication Number 2024/191770
Status In Force
Filing Date 2024-03-08
Publication Date 2024-09-19
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Fisher, Jeremy
  • Sheppard, Scott
  • Fayed, Khaled
  • Wood, Simon

Abstract

A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

IPC Classes  ?

  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

10.

METHODS OF FORMING PACKAGED SEMICONDUCTOR DEVICES AND LEADFRAMES FOR SEMICONDUCTOR DEVICE PACKAGES

      
Application Number 18654125
Status Pending
Filing Date 2024-05-03
First Publication Date 2024-08-22
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Liew, Soon Lee
  • Woo, Eng Wah
  • Komposch, Alexander

Abstract

A leadframe blank includes a first package blank, a second package blank and a tie bar between the first package blank and the second package blank. The tie bar includes a recessed cavity therein.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

11.

COAXIAL TO MICROSTRIP TRANSITIONAL HOUSING

      
Application Number 18649368
Status Pending
Filing Date 2024-04-29
First Publication Date 2024-08-22
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Rozbicki, Andrzej
  • Hogan, Paul
  • Pepelis, Gary
  • Donahue, Scott

Abstract

Aspects of coaxial to microstrip transitional housings are described. A method of forming a transitional housing includes forming a channel to a first depth into a housing block from a top surface of the housing block, forming a first annular opening to a second depth into the housing block from the top surface of the housing block at a first end of the channel, forming a second annular opening to the second depth into the housing block from the top surface of the housing block at a second end of the channel, inserting a first cylindrical plug into the first annular opening, and inserting a second cylindrical plug into the second annular opening. The second depth can be greater than the first depth in some cases.

IPC Classes  ?

  • H01P 5/08 - Coupling devices of the waveguide type for linking lines or devices of different kinds
  • H01P 5/02 - Coupling devices of the waveguide type with invariable factor of coupling

12.

III-NITRIDE MATERIAL SEMICONDUCTOR STRUCTURES ON CONDUCTIVE SILICON SUBSTRATES

      
Application Number 18591875
Status Pending
Filing Date 2024-02-29
First Publication Date 2024-08-08
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Boles, Timothy E.
  • Struble, Wayne Mack

Abstract

Semiconductor structures including III-nitride materials are described herein, including semiconductor structures comprising III-nitride material regions (e.g., gallium nitride material regions). An example semiconductor structure includes a substrate, a III-nitride material region located over the substrate, a first-type electrode over the III-nitride material region, and a second-type electrode over the III-nitride material region. The first-type electrode defines a first electrode interfacial area with the III-nitride material region. The second-type electrode defines a second electrode interfacial area with the III-nitride material region. The first electrode interfacial area is less than 20 times the second electrode interfacial area in at least one example.

IPC Classes  ?

  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 23/66 - High-frequency adaptations
  • H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/872 - Schottky diodes

13.

WIDE BAND PASSIVE BALUN

      
Application Number 18104315
Status Pending
Filing Date 2023-02-01
First Publication Date 2024-08-01
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Mourant, Jean-Marc

Abstract

A balun is enhanced with design features that extend the operational bandwidth of the balun allowing the balun to operate at lower frequencies. The design enhancements also suppress resonances that otherwise cause sudden power drops at a resonance frequency while a load is connected between the balun's differential outputs.

IPC Classes  ?

  • H01P 5/10 - Coupling devices of the waveguide type for linking lines or devices of different kinds for coupling balanced with unbalanced lines or devices
  • H03H 7/42 - Balance/unbalance networks

14.

GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE

      
Application Number 18632801
Status Pending
Filing Date 2024-04-11
First Publication Date 2024-08-01
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Struble, Wayne Mack
  • Boles, Timothy Edward
  • Barrett, Jason Matthew
  • Atherton, John Stephen

Abstract

Electrode structures and methods of manufacturing electrode structures for devices are described. An example electrode structure includes a gate metal formation including a nitride layer with an opening that exposes a surface region of a substrate, a gate metal layer on the surface region of the substrate, a barrier metal layer on the gate metal layer and on at least a portion of a step around the opening in the nitride layer, and a conductive metal layer on the barrier metal layer. The gate metal layer is on the surface region of the substrate and on at least another portion of the step around the opening in the nitride layer in one example. The gate metal layer includes first and second gate metal layers in one example, such as nickel and tungsten.

IPC Classes  ?

  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/40 - Electrodes

15.

ADAPTIVE TEMPERATURE PEAKING CONTROL FOR WIDEBAND AMPLIFIERS

      
Application Number 18048225
Status Pending
Filing Date 2022-10-20
First Publication Date 2024-07-11
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Duy P.
  • Nguyen, Nguyen L.K.
  • Pham, Thanh T.
  • Phan, Trong
  • D'Agostino, Stefano
  • Kennan, Wayne

Abstract

Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.

IPC Classes  ?

  • H03F 3/45 - Differential amplifiers
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices

16.

EXTRINSIC FIELD TERMINATION STRUCTURES FOR IMPROVING RELIABILITY OF HIGH-VOLTAGE, HIGH-POWER ACTIVE DEVICES

      
Application Number 18606765
Status Pending
Filing Date 2024-03-15
First Publication Date 2024-07-04
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Hanson, Allen W.
  • Lian, Chuanxin
  • Struble, Wayne Mack

Abstract

Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 21/76 - Making of isolation regions between components
  • H01L 21/765 - Making of isolation regions between components by field-effect
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/872 - Schottky diodes

17.

VARIABLE GAIN OPTICAL MODULATOR WITH OPEN COLLECTOR DRIVER AMPLIFIER AND METHOD OF OPERATION

      
Application Number 18089448
Status Pending
Filing Date 2022-12-27
First Publication Date 2024-06-27
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Nguyen
  • Nguyen, Duy
  • Phan, Trong
  • Pham, Thanh
  • Kennan, Wayne
  • D'Agostino, Stefano

Abstract

A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.

IPC Classes  ?

  • H03F 1/42 - Modifications of amplifiers to extend the bandwidth
  • H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices

18.

VARIABLE GAIN OPTICAL MODULATOR WITH OPEN COLLECTOR DRIVER AMPLIFIER AND METHOD OF OPERATION

      
Application Number 18089510
Status Pending
Filing Date 2022-12-27
First Publication Date 2024-06-27
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Nguyen
  • Nguyen, Duy
  • Phan, Trong
  • Pham, Thanh
  • Kennan, Wayne
  • D'Agostino, Stefano

Abstract

A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.

IPC Classes  ?

  • H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/45 - Differential amplifiers
  • H03G 1/00 - CONTROL OF AMPLIFICATION - Details of arrangements for controlling amplification

19.

VARIABLE GAIN OPTICAL MODULATOR WITH OPEN COLLECTOR DRIVER AMPLIFIER AND METHOD OF OPERATION

      
Application Number 18089421
Status Pending
Filing Date 2022-12-27
First Publication Date 2024-06-27
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Nguyen
  • Nguyen, Duy
  • Phan, Trong
  • Pham, Thanh
  • Kennan, Wayne
  • D'Agostino, Stefano

Abstract

A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.

IPC Classes  ?

  • H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/45 - Differential amplifiers
  • H03G 1/00 - CONTROL OF AMPLIFICATION - Details of arrangements for controlling amplification

20.

INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME

      
Application Number 18145961
Status Pending
Filing Date 2022-12-23
First Publication Date 2024-06-27
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Jang, Haedong
  • Hasan, Mehdi
  • Marbell, Marvin
  • Fisher, Jeremy

Abstract

A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/053 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

21.

INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME

      
Application Number US2023084585
Publication Number 2024/137486
Status In Force
Filing Date 2023-12-18
Publication Date 2024-06-27
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Jang, Haedong
  • Hasan, Mehdi
  • Marbell, Marvin
  • Fisher, Jeremy

Abstract

A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 23/66 - High-frequency adaptations

22.

LOSSY MATCHING NETWORK AND WIDEBAND STABILIZER

      
Application Number 18082647
Status Pending
Filing Date 2022-12-16
First Publication Date 2024-06-20
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Nguyen
  • Phan, Trong
  • Nguyen, Duy
  • Pham, Thanh
  • D'Agostino, Stefano
  • Kennan, Wayne
  • Allen, William

Abstract

An enhanced electrical circuit can employ conductive fill components that can facilitate providing desirable resistive stabilization of the electrical circuit and other desirable circuit qualities without having to use a physical resistor. The electrical circuit can comprise a transmission line, which can be a microstrip line, that can have defined dimensions. The electrical circuit can comprise respective conductive fill components that can be in proximity to desired sides of the transmission line, wherein the respective conductive fill components can provide the desired resistive stabilization for the electrical circuit. The respective conductive fill components can be separated from, and not in contact with, each other based on respective gaps of a defined size(s) between respective adjacent conductive fill components. The respective conductive fill components can be across a single layer or multiple layers of conductive fill components.

IPC Classes  ?

  • H01P 1/00 - Auxiliary devices
  • H01P 3/08 - Microstrips; Strip lines
  • H01P 11/00 - Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type

23.

STACKED INTEGRATED PASSIVE DEVICE

      
Application Number 18078779
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Fisher, Jeremy
  • Marbell, Marvin
  • Jang, Haedong

Abstract

A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.

IPC Classes  ?

  • H01G 4/40 - Structural combinations of fixed capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
  • H01F 27/28 - Coils; Windings; Conductive connections
  • H01F 27/29 - Terminals; Tapping arrangements
  • H01G 4/228 - Terminals
  • H01G 4/33 - Thin- or thick-film capacitors
  • H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

24.

LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS

      
Application Number 18582153
Status Pending
Filing Date 2024-02-20
First Publication Date 2024-06-13
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Som, Shamit
  • Struble, Wayne Mack
  • Barrett, Jason Matthew
  • Yamujala, Nishant R.
  • Atherton, John Stephen

Abstract

An example field effect transistor includes a substrate, a first source metal over the substrate, a second source metal over the substrate, and a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor. The drain metal includes a drain metal body having a notched region between the first source metal and the second source metal over the channel, and the notched region defines a first projecting portion and a second projecting portion of the drain metal body. In one aspect, the first projecting portion and the second projecting portion are positioned on respective sides of the notched region. The notched region is a triangular-shaped notched region in one example.

IPC Classes  ?

  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

25.

CAPACITOR NETWORKS FOR HARMONIC CONTROL IN POWER DEVICES

      
Application Number 18582162
Status Pending
Filing Date 2024-02-20
First Publication Date 2024-06-13
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Patel, Prity Kirit

Abstract

New types, structures, and arrangements of capacitor networks for harmonic control and other purposes are described. An example capacitor network includes a bond pad and metal-insulator-metal (MIM) capacitors positioned over the top side of the substrate and along different sides of the bond pad. A first metal layer of each of the plurality of MIM capacitors is electrically coupled to the bond pad. A second metal layer of each of the plurality of MIM capacitors is electrically coupled to a ground plane on a bottom side of the substrate by a through-substrate via. The MIM capacitors can be arranged around the bond pad in the capacitor network for a tailored capacitance. A matching network in the integrated device can incorporate the capacitor network to reduce loss, provide better harmonic termination, and achieve better phase alignment for the power devices.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

26.

RADIO FREQUENCY POWER AMPLIFIER IMPLEMENTING AN OFF MODE OUTPUT IMPEDANCE CONTROL AND A PROCESS OF IMPLEMENTING THE SAME

      
Application Number 18061246
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Joly, Christophe
  • Devita, Michael

Abstract

A device may include an input port; a RF output port; a RF amplifier device; and an off mode output impedance control.

IPC Classes  ?

  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

27.

PARASITIC CAPACITANCE REDUCTION IN GAN-ON-SILICON DEVICES

      
Application Number 18432740
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Cueva, Gabriel R.
  • Boles, Timothy E.
  • Struble, Wayne Mack

Abstract

Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L 21/74 - Making of buried regions of high impurity concentration, e.g. buried collector layers, internal connections
  • H01L 21/76 - Making of isolation regions between components
  • H01L 21/762 - Dielectric regions
  • H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
  • H01L 23/66 - High-frequency adaptations
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

28.

High Frequency, High Temperature Transistor Devices

      
Application Number 18071768
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-30
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Bothe, Kyle
  • Ganguly, Satyaki

Abstract

Transistor devices are provided. In one example, a transistor device includes a Group III nitride-based semiconductor structure. The transistor device has a non-degradation time of at least about 350 hours without degrading an output power of the transistor device by 1 dB or greater during a test condition. The test condition is associated with an operating frequency of the transistor device of about 31.5 GHz and a junction temperature of the transistor device of about 380° ° C.

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/40 - Electrodes

29.

SEMICONDUCTOR LASER WITH METAL PULL-BACK DBR GRATING

      
Application Number 17990734
Status Pending
Filing Date 2022-11-20
First Publication Date 2024-05-23
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Jiang, Yifan
  • Parz, Wolfgang
  • Parayanthal, Padman

Abstract

Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.

IPC Classes  ?

  • H01S 5/125 - Distributed Bragg reflector [DBR] lasers
  • H01S 5/042 - Electrical excitation
  • H01S 5/0625 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes in multi-section lasers
  • H01S 5/343 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser

30.

MULTI-ZONE RADIO FREQUENCY TRANSISTOR AMPLIFIERS

      
Application Number 17991855
Status Pending
Filing Date 2022-11-22
First Publication Date 2024-05-23
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Lim, Kwangmo Chris
  • Noori, Basim
  • Mu, Qianli
  • Marbell, Marvin
  • Sheppard, Scott
  • Komposch, Alexander

Abstract

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

IPC Classes  ?

  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H01L 23/66 - High-frequency adaptations

31.

OPTIMAL EQUALIZATION PARTITIONING WITH AUTOMATIC GAIN ADJUSTMENT

      
Application Number 18424600
Status Pending
Filing Date 2024-01-26
First Publication Date 2024-05-23
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Latchman, Ryan

Abstract

An optical module configured to electrically connect to a host. A linear equalizer performs equalization on a host equalized signal to create a module equalized signal, and a driver configured to present the module equalized signal from the linear equalizer to an optical conversion device at a magnitude suitable for the optical conversion device. An optical conversion device receives the module equalized signal from the driver, converts the module equalized signal to an optical signal, and transmit the optical signal over an optical channel. Also part of the optical module is an interface which communicates supplemental equalizer settings to the host. A memory stores the supplemental equalizer settings which reflect the optical modules effect on a signal passing through the optical module. A controller oversees communication of the supplemental equalizer settings to the host such that the host uses the supplemental equalizer settings to modify host equalizer settings.

IPC Classes  ?

  • H04B 10/2507 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
  • H04B 10/2575 - Radio-over-fibre, e.g. radio frequency signal modulated onto an optical carrier
  • H04L 27/01 - Equalisers

32.

SEMICONDUCTOR LASER WITH METAL PULL-BACK DBR GRATING

      
Application Number US2023033313
Publication Number 2024/107267
Status In Force
Filing Date 2023-09-20
Publication Date 2024-05-23
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Jiang, Yifan
  • Parz, Wolfgang
  • Parayanthal, Padman

Abstract

Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.

IPC Classes  ?

  • H01S 5/125 - Distributed Bragg reflector [DBR] lasers

33.

Open-Collector Variable Gain Amplifier and Method Therefor

      
Application Number 18055647
Status Pending
Filing Date 2022-11-15
First Publication Date 2024-05-16
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Nguyen
  • Phan, Trong
  • Allen, William

Abstract

An amplifier circuit has a variable gain amplifier including an input receiving an input signal and an open-conduction output, and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit. The variable gain amplifier has a first transistor and second transistor each having a control input receiving the input signal. A third transistor has a control terminal receiving a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output. A fourth transistor has a control terminal receiving the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output.

IPC Classes  ?

  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices
  • H03F 3/45 - Differential amplifiers

34.

HOT VIA DIE ATTACH JETTING

      
Application Number US2023078194
Publication Number 2024/102592
Status In Force
Filing Date 2023-10-30
Publication Date 2024-05-16
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Farrington, Novak
  • Chan, Moses

Abstract

Devices and methods including hot via die attach jetting are described. An example integrated circuit device includes a semiconductor substrate, vias extending from a top to a bottom surface of the substrate, and a metal layer on the bottom surface of the substrate. The metal layer includes a metal pad extending around a via opening at the bottom surface of the substrate. The metal pad is electrically isolated from a remainder of the metal layer. The device also includes one or more jet-dispensed dots of a conductive die attach adhesive material on the metal pad. Electrical connections made through the metal pad and jet-dispensed dots may be preferred as compared to wire bonds or flip chip approaches, particularly for RF input and output signals. The use of jet-dispensed dots can facilitate high-volume and automated process techniques.

IPC Classes  ?

  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

35.

FIELD EFFECT TRANSISTOR INCLUDING FIELD PLATES

      
Application Number 18407695
Status Pending
Filing Date 2024-01-09
First Publication Date 2024-05-16
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Fisher, Jeremy
  • Bothe, Kyle
  • Alcorn, Terry
  • Namishia, Daniel
  • Guo, Jia
  • King, Matthew
  • Sriram, Saptharishi
  • Radulescu, Fabian
  • Sheppard, Scott
  • Liu, Yueying

Abstract

A transistor device may include a semiconductor structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer; a source contact and a drain contact on the barrier layer; a gate contact on the semiconductor structure between the source contact and the drain contact, the gate contact including a drain-side wing portion extending from a central portion of the gate contact; and a field plate on the semiconductor structure between the gate contact and the drain contact and laterally offset from the gate contact by a distance. The field plate may include a first wing portion extending from a central portion of the field plate.

IPC Classes  ?

  • H01L 29/40 - Electrodes
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT

36.

BALANCERS FOR ISOLATION BALUNS

      
Application Number 18054394
Status Pending
Filing Date 2022-11-10
First Publication Date 2024-05-16
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Bichler, Iii, Anthony Joseph

Abstract

Power amplifiers including balanced coaxial baluns are described. One example includes first and second amplifiers coupled to a balanced pair of first and second microstrip lines on a circuit board. A balun is coupled between the microstrip lines at a balanced end and between a conductive trace and a ground plane of the circuit board at an unbalanced end of the balun. The balun includes a coaxial balun line and a surface mount balancing inductor. The coaxial line includes center and shield conductors. A first end of the center conductor is coupled to the first microstrip line and a first end of the shield conductor is coupled to the second microstrip line at the balanced end of the balun. The balancing inductor is coupled between the first microstrip line and the ground plane to maintain symmetry for the balanced pair of microstrip lines.

IPC Classes  ?

  • H01P 5/10 - Coupling devices of the waveguide type for linking lines or devices of different kinds for coupling balanced with unbalanced lines or devices
  • H01Q 1/48 - Earthing means; Earth screens; Counterpoises

37.

HOT VIA DIE ATTACH JETTING

      
Application Number 18053915
Status Pending
Filing Date 2022-11-09
First Publication Date 2024-05-09
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Farrington, Novak
  • Chan, Moses

Abstract

Devices and methods including hot via die attach jetting are described. An example integrated circuit device includes a semiconductor substrate, vias extending from a top to a bottom surface of the substrate, and a metal layer on the bottom surface of the substrate. The metal layer includes a metal pad extending around a via opening at the bottom surface of the substrate. The metal pad is electrically isolated from a remainder of the metal layer. The device also includes one or more jet-dispensed dots of a conductive die attach adhesive material on the metal pad. Electrical connections made through the metal pad and jet-dispensed dots may be preferred as compared to wire bonds or flip chip approaches, particularly for RF input and output signals. The use of jet-dispensed dots can facilitate high-volume and automated process techniques.

IPC Classes  ?

  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices

38.

ENHANCED CURRENT MIRROR FOR MULTIPLE SUPPLY VOLTAGES

      
Application Number 18405323
Status Pending
Filing Date 2024-01-05
First Publication Date 2024-05-02
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Mourant, Jean-Marc

Abstract

An enhanced current mirror can be utilized to accurately control a bias current associated with an amplifier. A current controller component (CCC) can employ the enhanced current mirror and can be associated with the amplifier. The CCC can comprise a comparator that can compare an adjusted supply voltage level to a reference voltage level, the adjusted supply voltage level relating to a supply voltage level of a supply voltage supplied to the amplifier and CCC. The CCC can control switching of an operational state of a transistor of the comparator to switch in or out a resistance of a reference resistor component associated with the supply voltage, based on a result of the comparison of the adjusted supply voltage level to the reference voltage level, to facilitate accurately controlling an amount of bias current associated with the amplifier. The CCC and amplifier can be situated on the same die.

IPC Classes  ?

  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only

39.

RF AMPLIFIERS WITH IMPROVED STABILITY BY SOURCE INDUCTANCE ADJUSTMENT

      
Application Number 18483159
Status Pending
Filing Date 2023-10-09
First Publication Date 2024-05-02
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Bouisse, Gerard

Abstract

A radio frequency transistor amplifier package includes a package substrate with input, output, and ground terminals, and a transistor die on the package substrate. The transistor die includes a semiconductor structure having a plurality of transistors and gate, drain, and source contacts electrically coupled thereto. An inductance adjustment element is electrically coupled between the source contacts and the ground terminal, and is configured to provide a stability factor K of greater than or equal to 1 for a first operating frequency range of the transistor die. Related devices and methods are also discussed.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

40.

ADAPTIVE TEMPERATURE PEAKING CONTROL FOR WIDEBAND AMPLIFIERS

      
Application Number US2023076684
Publication Number 2024/086478
Status In Force
Filing Date 2023-10-12
Publication Date 2024-04-25
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Nguyen, Duy P.
  • Nguyen, Nguyen L.K.
  • Pham, Thanh T.
  • Phan, Trong
  • D'Agostino, Stefano
  • Kennan, Wayne

Abstract

Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.

IPC Classes  ?

  • H03F 1/30 - Modifications of amplifiers to reduce influence of variations of temperature or supply voltage

41.

SYMMETRICAL COMMON GATE DIRECT CURRENT BIAS NETWORK FOR STACKED FIELD EFFECT TRANSMITTER DISTRIBUTED HIGH-POWER AMPLIFIER, RELATED APPARATUSES AND RELATED METHODS

      
Application Number US2023035067
Publication Number 2024/086060
Status In Force
Filing Date 2023-10-13
Publication Date 2024-04-25
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Fujii, Kohei

Abstract

A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier (400), related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages (206, 208, 210, 212) connected in parallel between an input port (RF_IN) and an output port (RF OUT). The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages (206, 208, 210, 212). The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.

IPC Classes  ?

  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
  • H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

42.

SYMMETRICAL COMMON GATE DIRECT CURRENT BIAS NETWORK FOR STACKED FIELD EFFECT TRANSMITTER DISTRIBUTED HIGH-POWER AMPLIFIER, RELATED APPARATUSES AND RELATED METHODS

      
Application Number 17967915
Status Pending
Filing Date 2022-10-18
First Publication Date 2024-04-18
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Fujii, Kohei

Abstract

A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier, related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages connected in parallel between an input port and an output port. The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages. The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.

IPC Classes  ?

  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
  • H01P 3/08 - Microstrips; Strip lines

43.

VOICE COIL LEAF SPRING PROBER

      
Application Number 18471270
Status Pending
Filing Date 2023-09-20
First Publication Date 2024-04-18
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Vanderwerf, Timothy James
  • Chernyakov, Alex G

Abstract

Aspects of the present disclosure describe a voice coil actuated leaf spring prober that advantageously may be operated to probe every individual device (device under test—DUT) comprising a contemporary wafer. The prober according to aspects of the present disclosure includes one or more probe needles attached in an electrically isolated arrangement to an end of a horizontal-U-shaped, recurved, leaf spring arrangement. The prober includes—for example—a voice coil actuator positioned within the horizontal-U-shaped portion of the leaf spring which—when operated—results in leaf spring displacement and probe needle movement such that it may mechanically/electrically contact the DUT.

IPC Classes  ?

44.

VOICE COIL LEAF SPRING PROBER

      
Application Number US2023033314
Publication Number 2024/081107
Status In Force
Filing Date 2023-09-20
Publication Date 2024-04-18
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Vanderwerf, Timothy
  • Chernyakov, Alex

Abstract

Aspects of the present disclosure describe a voice coil actuated leaf spring prober that advantageously may be operated to probe every individual device (device under test – DUT) comprising a contemporary wafer. The prober according to aspects of the present disclosure includes one or more probe needles attached in an electrically isolated arrangement to an end of a horizontal-U-shaped, recurved, leaf spring arrangement. The prober includes – for example – a voice coil actuator positioned within the horizontal-Ushaped portion of the leaf spring which – when operated – results in leaf spring displacement and probe needle movement such that it may mechanically/electrically contact the DUT.

IPC Classes  ?

  • G01R 1/06 - Measuring leads; Measuring probes

45.

EFFICIENCY IMPROVEMENTS FOR MULTI-STAGE POWER AMPLIFIERS

      
Application Number 17766611
Status Pending
Filing Date 2019-10-29
First Publication Date 2024-04-04
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Bouisse, Gerard J.L
  • Plet, Sullivan Yvon Claude
  • Poledrelli, Carlo

Abstract

Efficiency improvements for multi-stage power amplifiers are described. In one example, a power amplifier includes a driver amplifier formed on a first semiconductor die using a first semiconductor fabrication process, an output amplifier formed on a second semiconductor die using a second semiconductor fabrication process, and an inter-stage matching network formed between the driver amplifier and the output amplifier. The first semiconductor fabrication process is a lower voltage process and the second semiconductor fabrication process is a higher voltage process. The use of the two different fabrication processes leads to a number of advantages, including the simplification of the inter-stage matching network, increased radio frequency bandwidth, and improved line-up efficiency among the stages of the power amplifier.

IPC Classes  ?

  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
  • H01L 23/66 - High-frequency adaptations
  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

46.

TRANSISTOR AMPLIFIER WITH PCB ROUTING AND SURFACE MOUNTED TRANSISTOR DIE

      
Application Number US2023074159
Publication Number 2024/064571
Status In Force
Filing Date 2023-09-14
Publication Date 2024-03-28
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Marbell, Marvin
  • Fisher, Jeremy
  • Jang, Haedong
  • Namishia, Daniel
  • Etter, Daniel

Abstract

A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and/or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
  • H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks

47.

Group III nitride-based radio frequency transistor amplifiers having source, gate and/or drain conductive vias

      
Application Number 18517065
Grant Number 12113490
Status In Force
Filing Date 2023-11-22
First Publication Date 2024-03-14
Grant Date 2024-10-08
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Noori, Basim
  • Marbell, Marvin
  • Mu, Qianli
  • Lim, Kwangmo Chris
  • Watts, Michael E.
  • Bokatius, Mario
  • Kim, Jangheon

Abstract

RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

IPC Classes  ?

  • H03F 3/187 - Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
  • H01L 23/498 - Leads on insulating substrates
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

48.

Lateral Schottky diode

      
Application Number 17211116
Grant Number 11923462
Status In Force
Filing Date 2021-03-24
First Publication Date 2024-03-05
Grant Date 2024-03-05
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Boles, Timothy E.
  • Carlson, Douglas
  • Kaleta, Anthony

Abstract

Various aspects of Schottky diodes are described. The diodes are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter in some cases among other aspects. In one example, a Schottky diode includes a conduction layer, a first layer over the conduction layer, a second layer over the first layer, a first cathode and a second cathode spaced apart and in electrical contact with the conduction layer, and an anode over the second layer between the first cathode and the second cathode. The first cathode and the second cathode can be electrically connected to each other as a cathode of the Schottky diode.

IPC Classes  ?

  • H01L 29/872 - Schottky diodes
  • H01L 21/761 - PN junctions
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
  • H01L 29/40 - Electrodes
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/861 - Diodes
  • H02M 7/00 - Conversion of ac power input into dc power output; Conversion of dc power input into ac power output

49.

TRANSISTOR DIE INCLUDING MATCHING CIRCUIT

      
Application Number 17900652
Status Pending
Filing Date 2022-08-31
First Publication Date 2024-02-29
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Farrell, Donald
  • Namishia, Dan
  • Bothe, Kyle
  • Millon, Brad

Abstract

A transistor die includes a transistor including a control terminal, an output terminal, and a first partial matching circuit. The first partial matching circuit is connected to at least one of the control terminal of the transistor and the output terminal of the transistor, and is configured to tune an input impedance of the transistor die. A packaged device is also provided.

IPC Classes  ?

  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H01L 23/66 - High-frequency adaptations
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

50.

STACKED RF CIRCUIT TOPOLOGY USING TRANSISTOR DIE WITH THROUGH SILICON CARBIDE VIAS ON GATE AND/OR DRAIN

      
Application Number 18502334
Status Pending
Filing Date 2023-11-06
First Publication Date 2024-02-29
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Noori, Basim
  • Marbell, Marvin
  • Lim, Kwangmo Chris
  • Mu, Qianli

Abstract

A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
  • H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 3/213 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits

51.

ARRAYED WAVEGUIDE GRATINGS WITH STABILIZED PERFORMANCE UNDER VARYING PARAMETERS

      
Application Number 18499598
Status Pending
Filing Date 2023-11-01
First Publication Date 2024-02-22
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Anderson, Sean P.

Abstract

An arrayed waveguide grating device includes an input coupler configured to receive a light signal and split the light signal into a plurality of output light signals. The device also includes a plurality of waveguides optically connected to the input coupler, each waveguide having a plurality of waveguide portions having respective sensitivities to variance in one or more parameters associated with operating of the optical arrayed grating device. Lengths of the respective portions are determined such that each waveguide applies a respective phase shift to the output light signal that propagates through the waveguide and the plurality of waveguides have at least substantially same change in phase shift with respective changes in the one or more parameters associated with operation of the device. An output coupler is optically connected to the plurality of waveguides to map respective light signals output from the plurality of waveguides to respective focal positions.

IPC Classes  ?

  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind

52.

HIGH ELECTRON MOBILITY TRANSISTORS HAVING IMPROVED PASSIVATION STRUCTURES AND REDUCES DRAIN CURRENT DRIFT, AS WELL AS METHODS OF FABRICATING SUCH DEVICES

      
Application Number US2023071497
Publication Number 2024/039968
Status In Force
Filing Date 2023-08-02
Publication Date 2024-02-22
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Bothe, Kyle
  • Hardiman, Chris
  • Keenan, Elizabeth
  • Guo, Jia
  • Radulescu, Fabian
  • Sheppard, Scott

Abstract

A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer (230) and a barrier layer (240) and source (250) and drain (252) contacts on the semiconductor layer structure. A gate contact (254) and a multi-layer passivation structure (262, 264, 266) are provided on the semiconductor layer structure between the gate contact (254) and the drain contact (252). The multi-layer passivation structure comprises at least first (262) and second (264) silicon nitride layers that have different material compositions. A spacer passivation layer (270) is provided at least between the gate contact (254) and the multi-layer passivation structure (262, 264, 266) on sidewalls of the first (262) and second (264) silicon nitride layers. A material composition of the spacer passivation layer (270) is different than a material composition of at least one of the layers of the multi-layer passivation structure (262, 264, 266). For example, the spacer passivation layer (270) may be a silicon nitride layer having a higher silicon content than the layers in the multi-layer passivation structure (262, 264, 266).

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/40 - Electrodes
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 21/338 - Field-effect transistors with a Schottky gate
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

53.

SEMICONDUCTOR STRUCTURES AND FABRICATION USING SUBLIMATION

      
Application Number 18449310
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-02-22
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Jessen, Gregg

Abstract

Semiconductor structures and methods of fabricating semiconductor structures using sublimation are described. An example method includes forming an opening through a mask layer over a wafer. The wafer includes a substrate, a channel layer over the substrate, a barrier layer over the channel layer, and a cap layer over the barrier layer. The method also includes subliming away a region of the cap layer, within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer. The material properties of the cap layer, as compared to the barrier layer, can be relied upon to form the opening in the cap layer down to the top surface of the barrier layer using sublimation, with high selectivity. Sublimation will stop with higher precision and selectivity at the interface between the cap layer and the barrier layer, as compared to etching.

IPC Classes  ?

  • H01L 29/66 - Types of semiconductor device
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 21/311 - Etching the insulating layers

54.

SEMICONDUCTOR STRUCTURES AND FABRICATION USING SUBLIMATION

      
Application Number US2023072152
Publication Number 2024/040019
Status In Force
Filing Date 2023-08-14
Publication Date 2024-02-22
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Jessen, Gregg

Abstract

Semiconductor structures and methods of fabricating semiconductor structures using sublimation are described. An example method includes forming an opening through a mask layer over a wafer. The wafer includes a substrate, a channel layer over the substrate, a barrier layer over the channel layer, and a cap layer over the barrier layer. The method also includes subliming away a region of the cap layer, within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer. The material properties of the cap layer, as compared to the barrier layer, can be relied upon to form the opening in the cap layer down to the top surface of the barrier layer using sublimation, with high selectivity. Sublimation will stop with higher precision and selectivity at the interface between the cap layer and the barrier layer, as compared to etching.

IPC Classes  ?

  • H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
  • H01L 21/336 - Field-effect transistors with an insulated gate
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 21/337 - Field-effect transistors with a PN junction gate
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

55.

SYMMETRICAL DOHERTY POWER AMPLIFIER HAVING IMPROVED EFFICIENCY

      
Application Number 18449963
Status Pending
Filing Date 2023-08-15
First Publication Date 2024-02-08
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Bouisse, Gerard

Abstract

Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.

IPC Classes  ?

  • H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
  • H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only

56.

SEMICONDUCTOR LASER HAVING IMPROVED FACET RELIABILITY

      
Application Number 17876180
Status Pending
Filing Date 2022-07-28
First Publication Date 2024-02-01
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Gadde, Akshitha
  • Parz, Wolfgang
  • Jiang, Yifan
  • Bowker, Jason Daniel

Abstract

Described herein are examples of improved semiconductor lasers having improved facet reliability for operation at high power and high current without significant change in device performance. The semiconductor laser may include a first semiconductor layer, an active layer, a second semiconductor layer sequentially adjacent to each other and arranged on a substrate, and a contact layer. In one example, the improved semiconductor laser may have a conductive contact less than the length of the semiconductor laser cavity and/or a dielectric layer arranged on at least one of the end portions of the contact layer.

IPC Classes  ?

  • H01S 5/042 - Electrical excitation
  • H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure

57.

Multi-Stage Driver Circuit and Method of Distributed Driver Response Shaping Using Programmable Capacitors

      
Application Number 18313952
Status Pending
Filing Date 2023-05-08
First Publication Date 2024-02-01
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Foley, David
  • Brownlee, Merrick

Abstract

A multi-stage driver circuit has a transmission line coupled to an output of the multi-stage driver circuit. The transmission line has inductive elements and programmable capacitive elements selected to shape the transmitted data signal. The programmable capacitive elements have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit.

IPC Classes  ?

  • H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
  • H03K 17/06 - Modifications for ensuring a fully conducting state
  • H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only

58.

MULTI-STAGE DRIVER CIRCUIT AND METHOD OF DISTRIBUTED DRIVER RESPONSE SHAPING USING PROGRAMMABLE CAPACITORS

      
Application Number US2023067289
Publication Number 2024/026161
Status In Force
Filing Date 2023-05-22
Publication Date 2024-02-01
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Foley, David
  • Brownlee, Merrick

Abstract

A multi-stage driver circuit (116) has a transmission line (119) coupled to an output of the multi-stage driver circuit (116). The transmission line (119) has inductive elements and programmable capacitive elements (130) selected to shape the transmitted data signal. The programmable capacitive elements (130) have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements (130) have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements (130) are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit (116).

IPC Classes  ?

  • H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/45 - Differential amplifiers

59.

TEMPERATURE DEPENDENT STABILIZATION AND PEAKING CONTROL

      
Application Number 17813508
Status Pending
Filing Date 2022-07-19
First Publication Date 2024-01-25
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Nguyen, Nguyen L.K.
  • Phan, Trong

Abstract

Aspects of temperature dependent stabilization and peaking control in amplifiers are described. An example amplifier includes a variable gain amplifier, a power amplifier, a variable compensation element coupled to the variable gain amplifier, and a controller that directs operation of the variable compensation element to adjust one or more operating characteristics of the amplifier. In one aspect, the variable compensation element comprises a variable impedance, and the controller varies the impedance across inputs of the variable gain amplifier based on temperature to stabilize the amplifier. In another aspect, the variable compensation element comprises a negative capacitance, and the controller varies a coupling of the negative capacitance across inputs of the variable gain amplifier based on temperature to linearize gain of the amplifier. The variable compensation element can include both a variable impedance and negative capacitance, and stability, peaking control, and linearity of the amplifier can be controlled.

IPC Classes  ?

  • H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices

60.

PARASITIC CHANNEL MITIGATION USING SILICON CARBIDE DIFFUSION BARRIER REGIONS

      
Application Number 18475858
Status Pending
Filing Date 2023-09-27
First Publication Date 2024-01-18
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Linthicum, Kevin J.

Abstract

Semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a substrate, a III-nitride material region over a top surface of the substrate, a first species implanted within at least one region of surface region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate, and a second species implanted within at least one region of the III-nitride material region. The second species can be implanted in a second pattern spatially defined across the lateral dimension of the substrate. The surface region of the substrate includes a parasitic channel. The at least one region of the substrate in which the first species is implanted includes a low-conductivity parasitic channel or is free of the parasitic channel.

IPC Classes  ?

  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

61.

HYBRID DISTRIBUTED DRIVER

      
Application Number 17855807
Status Pending
Filing Date 2022-07-01
First Publication Date 2024-01-04
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Foley, David

Abstract

A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.

IPC Classes  ?

  • H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F 3/45 - Differential amplifiers

62.

HYBRID DISTRIBUTED DRIVER

      
Application Number US2023021076
Publication Number 2024/005918
Status In Force
Filing Date 2023-05-04
Publication Date 2024-01-04
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Foley, David

Abstract

A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.

IPC Classes  ?

  • H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
  • H03F 3/45 - Differential amplifiers

63.

SILICON CARBIDE BASED INTEGRATED PASSIVE DEVICES FOR IMPEDENCE MATCHING OF RADIO FREQUENCY POWER DEVICES AND PROCESS OF IMPLEMENTING THE SAME

      
Application Number 17849353
Status Pending
Filing Date 2022-06-24
First Publication Date 2023-12-28
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Jang, Haedong
  • Marbell, Marvin
  • Fisher, Jeremy

Abstract

An amplifier circuit that includes an RF amplifier; an impedance matching network; a higher order harmonic termination circuit; a fundamental frequency matching circuit; and an integrated passive device (IPD) that includes a silicon carbide (SiC) substrate. The integrated passive device (IPD) includes one or more reactive components of the fundamental frequency matching circuit and one or more reactive components of the higher order harmonic termination circuit.

IPC Classes  ?

  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,
  • H01L 27/01 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices all the devices being of a type provided for in the same subgroup of groups , or in a single subclass of , , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

64.

RADIO FREQUENCY POWER AMPLIFIER IMPLEMENTING A GAIN EQUALIZER AND A PROCESS OF IMPLEMENTING THE SAME

      
Application Number 17847761
Status Pending
Filing Date 2022-06-23
First Publication Date 2023-12-28
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Joly, Christophe

Abstract

An amplifier includes an input impedance matching network; at least one transistor; and a gain equalizer configured to equalize gain. The gain equalizer is connected to components of the input impedance matching network.

IPC Classes  ?

  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03G 3/30 - Automatic control in amplifiers having semiconductor devices
  • H03F 3/24 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages

65.

MODULAR POWER TRANSISTOR COMPONENT ASSEMBLIES WITH FLIP CHIP INTERCONNECTIONS

      
Application Number 17848500
Status Pending
Filing Date 2022-06-24
First Publication Date 2023-12-28
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Mu, Qianli
  • Devita, Michael
  • Komposch, Alexander
  • Noori, Basim

Abstract

A transistor device package includes a transistor die comprising a gate terminal, a drain terminal, and a source terminal, and a passive component assembly including the transistor die on a surface thereof and comprising one or more passive electrical components electrically coupled to the gate terminal, the drain terminal, and/or the source terminal. A mold structure may be provided on the one or more passive electrical components. One or more conductive pads may be exposed by the mold structure. A support structure may extend along one or more sides of the transistor die on the surface of the passive component assembly. The support structure may provide a cavity that extends around the transistor die, and/or may be thermally conductive. Related devices and component assemblies are also discussed.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits
  • H01L 23/055 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads having a passage through the base
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/498 - Leads on insulating substrates

66.

TRACKING AND DETECTOR DEVICE FOR OPTICAL SYSTEMS

      
Application Number 18340813
Status Pending
Filing Date 2023-06-23
First Publication Date 2023-12-28
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Berman, Gregory M
  • Lefebvre, Kevin R

Abstract

A tracking detector device for use in a free-space optics (FSO) system includes a position sensor and an optical receiver coupled to the bottom surface of the position sensor. The position sensor has an optical aperture configured to allow a portion of incoming light to pass through the position sensor and a plurality of position receivers located adjacent to the optical aperture and configured to sense portions of the incoming light. The tracking detector device may also include a focusing optic disposed adjacent to the bottom surface of the position sensor and configured to focus the portion of the incoming light that passed through the position sensor onto the optical receiver. The tracking detector may advantageously be employed in FSO communications systems and provide fully automated alignment with an incoming light beam under computer control.

IPC Classes  ?

  • G01B 11/00 - Measuring arrangements characterised by the use of optical techniques

67.

TRACKING AND DETECTOR DEVICE FOR OPTICAL SYSTEMS

      
Application Number US2023026175
Publication Number 2023/250205
Status In Force
Filing Date 2023-06-24
Publication Date 2023-12-28
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Berman, Gregory
  • Lefebvre, Kevin

Abstract

A tracking detector device for use in a free-space optics (FSO) system includes a position sensor and an optical receiver coupled to the bottom surface of the position sensor. The position sensor has an optical aperture configured to allow a portion of incoming light to pass through the position sensor and a plurality of position receivers located adjacent to the optical aperture and configured to sense portions of the incoming light. The tracking detector device may also include a focusing optic disposed adjacent to the bottom surface of the position sensor and configured to focus the portion of the incoming light that passed through the position sensor onto the optical receiver. The tracking detector may advantageously be employed in FSO communications systems and provide fully automated alignment with an incoming light beam under computer control.

IPC Classes  ?

  • G01S 3/781 - Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using electromagnetic waves other than radio waves - Details
  • H04B 10/11 - Arrangements specific to free-space transmission, i.e. transmission through air or vacuum

68.

Printed circuit board configuration blocks and edge projections

      
Application Number 17807037
Grant Number 12082342
Status In Force
Filing Date 2022-06-15
First Publication Date 2023-12-21
Grant Date 2024-09-03
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Long, Rathnait
  • Cory, Richard Allen
  • Comtois, Gerald
  • Donahue, Scott

Abstract

Examples of printed circuit boards (PCBs) with board configuration blocks and board edge projections are described. In one example, a PCB includes a core material and a metal layer comprising a plurality of metal traces on the core material. The plurality of metal traces can include component interconnect traces and a board configuration block. The board configuration block can include a plan diagram for the PCB, an operational diagram for the PCB, or a combination of plan and operational diagrams. In other examples, a PCB can include a core material having a peripheral edge. The peripheral edge can include one or more board edge scheme projections positioned within projection edge regions of the peripheral edge. The scheme projections have a projection shape based on operational characteristics for the PCB. In some cases, the board configuration blocks can be located on the board edge scheme projections.

IPC Classes  ?

  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components
  • H05K 1/02 - Printed circuits - Details

69.

Baseline wander compensator and method

      
Application Number 17836722
Grant Number 12021543
Status In Force
Filing Date 2022-06-09
First Publication Date 2023-12-14
Grant Date 2024-06-25
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Foley, David

Abstract

A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.

IPC Classes  ?

  • H03M 1/12 - Analogue/digital converters
  • H03M 1/00 - Analogue/digital conversion; Digital/analogue conversion
  • H03M 1/10 - Calibration or testing

70.

MONOLITHIC PIN AND SCHOTTKY DIODE INTEGRATED CIRCUITS

      
Application Number 17806193
Status Pending
Filing Date 2022-06-09
First Publication Date 2023-12-14
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Piernas, Belinda Simone Edmee
  • Hoag, David Russell

Abstract

A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.

IPC Classes  ?

  • H01L 29/872 - Schottky diodes
  • H01L 29/868 - PIN diodes
  • H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology

71.

MONOLITHIC PIN AND SCHOTTKY DIODE INTEGRATED CIRCUITS

      
Application Number US2022081538
Publication Number 2023/239427
Status In Force
Filing Date 2022-12-14
Publication Date 2023-12-14
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Piernas, Belinda Simone Edmee
  • Hoag, David Russell

Abstract

A number of Monolithic Microwave Integrated Circuit (MMIC) devices including combinations of PIN and Schottky diodes, with integrated passive electrical components fabricated and electrically connected among them, are described herein, along with new process techniques for forming the MMIC devices. In one example, a monolithic semiconductor includes a substrate, a plurality of layers of semiconductor materials over the substrate, Schottky and Ohmic contacts on a first subset of the plurality of layers for a Schottky diode, and PIN diode Ohmic contacts on a second subset of the plurality of layers for a PIN diode. The device can also include an etch stop layer between the first subset of the plurality of layers and the second subset of the plurality of layers. The etch stop layer facilitates selective etching and isolation of the Schottky diode from the PIN diode by consecutive etchings.

IPC Classes  ?

  • H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/868 - PIN diodes
  • H01L 29/872 - Schottky diodes
  • H03F 1/52 - Circuit arrangements for protecting such amplifiers

72.

BASELINE WANDER COMPENSATOR AND METHOD

      
Application Number US2023020883
Publication Number 2023/239498
Status In Force
Filing Date 2023-05-03
Publication Date 2023-12-14
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Foley, David

Abstract

A baseline wander and offset correction system having inputs configured to receive input signals to be transmitted. Also part of the system is a driver circuit configured to receive and amplify the input signals. The driver circuit is configured with one or more transistors having an optional back bias terminal. A replica circuit receives the input signals and responsive thereto, generates back bias signals which are provided to the back bias terminal of the one or more transistors to change the back bias in response to the input signals having consecutive one values or consecutive zero values. This reduces the size of the one or more AC coupling capacitors located between the driver circuit and a channel. An embodiment may store back bias values in a memory. The back bias values are processed by DAC to generate the back bias signals for offset correction.

IPC Classes  ?

  • H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
  • H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements
  • H03F 1/38 - Positive-feedback circuit arrangements without negative feedback
  • H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F 3/45 - Differential amplifiers
  • H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving

73.

PLASMA-BASED BARRIER LAYER REMOVAL METHOD FOR INCREASING PEAK TRANSCONDUCTANCE WHILE MAINTAINING ON-STATE RESISTANCE AND RELATED DEVICES

      
Application Number 17834144
Status Pending
Filing Date 2022-06-07
First Publication Date 2023-12-07
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Hardiman, Chris
  • Lee, Kyoung-Keun
  • Bothe, Kyle
  • Radulescu, Fabian

Abstract

A transistor device includes a semiconductor structure comprising a channel layer and a barrier layer; source and drain contacts on the semiconductor structure; and a gate on the semiconductor structure between the source and drain contacts. A first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness, a second portion of the barrier layer between the gate and the channel layer has a second thickness, and the first thickness is about 1.5 times to 4 times greater than the second thickness. Related methods of fabrication using a looped recess process are also discussed.

IPC Classes  ?

  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
  • H01L 29/66 - Types of semiconductor device

74.

Semiconductor Device and Method of Forming High KT2 High Q Acoustic Wave Resonator

      
Application Number 17804916
Status Pending
Filing Date 2022-06-01
First Publication Date 2023-12-07
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Winslow, Thomas A.
  • Long, Rathnait
  • Patel, Mihir S.
  • Carlson, Douglas J.

Abstract

An acoustic wave resonator has a first conductive layer, piezoelectrical material formed over the first conductive layer, and second conductive layer formed over the piezoelectric material. An alignment of the first conductive layer, piezoelectric material and second conductive area defines an active region of the resonator and the active region includes a core area and a plurality of fractals extending from or recessed into the core area. The fractals maximize a perimeter-to-area ratio of the active region of the resonator. The fractals increase electromechanical coupling and a quality factor of the resonator. The fractals can have a star shape, rounded shape, asymmetric shape, or other shape that optimizes the perimeter-to-area ratio of the active region to maximize performance of the resonator. A frame can be disposed over or within the piezoelectric material. The frame is raised above the second conductive layer or recessed below the second conductive layer.

IPC Classes  ?

  • H03H 9/25 - Constructional features of resonators using surface acoustic waves
  • H03H 3/08 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of resonators or networks using surface acoustic waves

75.

ACOUSTIC WAVE RESONATOR WITH FRACTAL ACTIVE REGION AND METHOD OF FORMING IT

      
Application Number US2023065462
Publication Number 2023/235645
Status In Force
Filing Date 2023-04-06
Publication Date 2023-12-07
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Winslow, Thomas, A.
  • Long, Rathnait
  • Patel, Mihir, S.
  • Carlson, Douglas, J.

Abstract

An acoustic wave resonator has a first conductive layer (210), piezoelectrical material (212) formed over the first conductive layer, and second conductive layer (214) formed over the piezoelectric material. An alignment of the first conductive layer, piezoelectric material and second conductive area defines an active region (226) of the resonator and the active region includes a core area and a plurality of fractals extending from or recessed into the core area. The fractals maximize a perimeter-to-area ratio of the active region of the resonator. The fractals increase electromechanical coupling and a quality factor of the resonator. The fractals can have a star shape, rounded shape, asymmetric shape, or other shape that optimizes the perimeter-to-area ratio of the active region to maximize performance of the resonator. A frame can be disposed over or within the piezoelectric material. The frame is raised above the second conductive layer or recessed below the second conductive layer.

IPC Classes  ?

  • H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details
  • H03H 9/13 - Driving means, e.g. electrodes, coils for networks consisting of piezoelectric or electrostrictive materials
  • H03H 9/145 - Driving means, e.g. electrodes, coils for networks using surface acoustic waves
  • H03H 9/17 - Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
  • H03H 3/04 - Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks for obtaining desired frequency or temperature coefficient

76.

MICROSTRIP BOARD GROUND PLANE IMPEDANCE MATCHING ADJUSTMENT

      
Application Number US2023065580
Publication Number 2023/235646
Status In Force
Filing Date 2023-04-10
Publication Date 2023-12-07
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Achiriloaie, Benone

Abstract

Microstrip technology boards including microstrip traces matched over a range of different impedances are described. The microstrip boards include impedance-offset openings in ground planes under certain microstrip traces. The openings result in different effective dielectric constants and higher impedances for microstrip traces aligned with the openings, as compared to microstrip traces aligned over metal ground planes. The microstrip boards can also be mounted to conductive heatsinks. The conductive heatsinks act as ground planes for the microstrip traces aligned with the impedance-offset ground plane openings. The conductive heatsinks can include depressions co-located with the ground plane openings. Impedances of microstrip traces aligned with the ground plane openings are thus a function of the dielectric constant of the central core of the boards, the thickness of the central core, and the thickness of the air gap provided by the heatsink depressions.

IPC Classes  ?

  • H03F 1/08 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H03F 3/189 - High-frequency amplifiers, e.g. radio frequency amplifiers
  • H03F 3/19 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
  • H03F 3/50 - Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower
  • H03F 1/10 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of amplifying elements with multiple electrode connections
  • H03F 1/12 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of attenuating means
  • H03F 3/191 - Tuned amplifiers
  • H03F 3/193 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits

77.

Apparatus for reduction of power-dependent optical loss in silicon photonic devices

      
Application Number 18223619
Grant Number 12019318
Status In Force
Filing Date 2023-07-19
First Publication Date 2023-11-16
Grant Date 2024-06-25
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Anderson, Sean P.
  • Yamazaki, Hiroyuki

Abstract

Optical waveguides may include a substrate and a silicon based optical waveguide supported on the substrate. The silicon based optical waveguide may include a central ridge portion and a plurality of spaced apart wing portions connected through connecting portions. The number of wing portions may be greater than two. The central ridge portion may have a central ridge lateral width extent greater than a lateral width extent of at least one of the wing portions. Optical waveguides may include a substrate, a silicon based optical waveguide supported on the substrate, and a concentrator supported on the substrate and positioned within a lateral width extent of the silicon based optical waveguide and outside of a height extent of the silicon based optical waveguide. The optical waveguides may be included as part of an optical modulator.

IPC Classes  ?

  • G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements with at least one potential jump barrier, e.g. PN, PIN junction in an optical waveguide structure
  • G02B 6/12 - Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths

78.

Circuit and Method of Providing Common Mode Suppression for Amplifier

      
Application Number 17662515
Status Pending
Filing Date 2022-05-09
First Publication Date 2023-11-09
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Nguyen, Nguyen
  • Phan, Trong

Abstract

A semiconductor device has an amplifier and common mode suppression (CMS) circuit formed on a common substrate. The CMS circuit has a first input and second input coupled for receiving an input signal and further has a first output coupled to a first input of the amplifier and a second output coupled to a second input of the amplifier to reduce common mode. The CMS circuit further has a ground plane, a first conductive trace disposed over the ground plane and coupled between the first input and first output, second conductive trace disposed over the ground plane and coupled between the second input and second output, and third conductive trace disposed over the ground plane with a first end of the third conductive trace coupled to the ground plane and a second end of the third conductive trace open circuit to form a resonator.

IPC Classes  ?

  • H03F 3/04 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
  • H01L 23/66 - High-frequency adaptations
  • H01P 7/08 - Strip line resonators
  • H01P 11/00 - Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type

79.

DIAMOND-METAL COMPOSITE HIGH POWER DEVICE PACKAGES

      
Application Number 17661418
Status Pending
Filing Date 2022-04-29
First Publication Date 2023-11-02
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Martin, Quinn Don
  • Nagy, Walter

Abstract

Semiconductor device packages and methods of manufacture are described. In one example, a semiconductor device package includes a flange, a frame secured to a major surface of the flange, with the frame forming an air cavity bounded in part by a surface of the flange, and at least one conductive lead that extends from outside the frame, through a portion of the frame, and is exposed within the air cavity for wire bonding. Other packages without air cavities are also described. The flange can incorporate a composite core material including diamond particles distributed in metal. The flange offers improved thermal conductivity, for greater heat dissipation from and additional performance of semiconductor devices within the packages. The flange exhibits thermal conductivity greater than that of Copper and other materials. The flange also exhibits a coefficient of thermal expansion suitable for bonding semiconductor die including GaN and SiC materials to the flange.

IPC Classes  ?

  • H01L 23/373 - Cooling facilitated by selection of materials for the device
  • H01L 23/057 - Containers; Seals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
  • H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups

80.

DIAMOND-METAL COMPOSITE HIGH POWER DEVICE PACKAGES

      
Application Number US2023064625
Publication Number 2023/212462
Status In Force
Filing Date 2023-03-17
Publication Date 2023-11-02
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Martin, Quinn Don
  • Nagy, Walter

Abstract

Semiconductor device packages and methods of manufacture are described. In one example, a semiconductor device package includes a flange, a frame secured to a major surface of the flange, with the frame forming an air cavity bounded in part by a surface of the flange, and at least one conductive lead that extends from outside the frame, through a portion of the frame, and is exposed within the air cavity for wire bonding. Other packages without air cavities are also described. The flange can incorporate a composite core material including diamond particles distributed in metal. The flange offers improved thermal conductivity, for greater heat dissipation from and additional performance of semiconductor devices within the packages. The flange exhibits thermal conductivity greater than that of Copper and other materials. The flange also exhibits a coefficient of thermal expansion suitable for bonding semiconductor die including GaN and SiC materials to the flange.

IPC Classes  ?

  • H01L 23/047 - Containers; Seals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being parallel to the base
  • H01L 23/373 - Cooling facilitated by selection of materials for the device

81.

RF POWER PALLET WITH MANAGEMENT DAUGTHER BOARD

      
Application Number 17711509
Status Pending
Filing Date 2022-04-01
First Publication Date 2023-10-05
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Achiriloaie, Benone

Abstract

Radio frequency (RF) power pallets including primary or first circuit boards and daughter or second circuit boards are described. An example RF power pallet includes a first circuit board comprising a first side, a second side, a first metal layer, and a second metal layer. The power pallet also includes an RF power amplifier coupled to the first metal layer and a second circuit board electrically coupled to the first metal layer. The second circuit board includes a bias voltage driver for the RF power amplifier, and the first metal layer includes a bias voltage trace that extends from a contact of the second circuit board to a gate of the power amplifier. The second circuit board extends the features of the RF pallet, while avoiding some increases in size, costs, and complexity that would typically be associated with the new features.

IPC Classes  ?

  • H05K 1/14 - Structural association of two or more printed circuits
  • H01R 12/72 - Coupling devices for rigid printing circuits or like structures coupling with the edge of the rigid printed circuits or like structures
  • H05K 1/02 - Printed circuits - Details

82.

SELECTIVE ETCHING OF SILICON LAYERS IN A SEMICONDUCTOR DEVICE

      
Application Number 17711084
Status Pending
Filing Date 2022-04-01
First Publication Date 2023-10-05
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor Boles, Timothy

Abstract

Techniques regarding patterning a silicon layer of a semiconductor device are provided. For example, one or more embodiments described herein can regard a method comprising positioning an etch stop layer between a dielectric layer and the silicon layer. Additionally, the method can comprise etching the silicon layer with a chemical etchant. Further, the etching can have a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer that is at least 200:1.

IPC Classes  ?

  • H01L 49/02 - Thin-film or thick-film devices
  • H01L 21/3065 - Plasma etching; Reactive-ion etching
  • H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks

83.

GROUP III NITRIDE-BASED MONOLITHIC MICROWAVE INTEGRATED CIRCUITS HAVING MULTI-LAYER METAL-INSULATOR-METAL CAPACITORS

      
Application Number 17688952
Status Pending
Filing Date 2022-03-08
First Publication Date 2023-09-14
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Fisher, Jeremy
  • Namishia, Dan
  • Sheppard, Scott

Abstract

Semiconductor devices are provided that include a Group III nitride-based semiconductor layer structure. A first metal layer is formed on an upper surface of the semiconductor layer structure, a first dielectric layer is formed on an upper surface of the first metal layer, and a second metal layer is formed on an upper surface of the first dielectric layer. The first metal layer, the first dielectric layer and the second metal layer form a first capacitor. A second dielectric layer is formed on an upper surface of the second metal layer, a third dielectric layer is formed on an upper surface of the second dielectric layer, and a third metal layer is formed on upper surfaces of the second and third dielectric layers. The second metal layer, the second dielectric layer and the third metal layer form a second capacitor that is stacked on the first capacitor.

IPC Classes  ?

  • H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
  • H03F 1/56 - Modifications of input or output impedances, not otherwise provided for
  • H01L 23/66 - High-frequency adaptations

84.

TAPERED WAVEGUIDE SEMICONDUCTOR OPTICAL DEVICES WITH INCREASED FACET REFLECTIVITY

      
Application Number 17676674
Status Pending
Filing Date 2022-02-21
First Publication Date 2023-08-24
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Parz, Wolfgang
  • Wang, Meng

Abstract

A semiconductor optical device includes a first facet bounding a first end of the semiconductor optical device. The semiconductor optical device further includes a waveguide having a first end proximate the first facet, the first end of the waveguide being tapered towards the first facet. The first facet has a curvature to increase modal reflectivity at a first interface at which the first end of the waveguide meets the first facet.

IPC Classes  ?

  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
  • F21V 8/00 - Use of light guides, e.g. fibre optic devices, in lighting devices or systems

85.

TAPERED WAVEGUIDE SEMICONDUCTOR OPTICAL DEVICES WITH INCREASED FACET REFLECTIVITY

      
Application Number US2023011042
Publication Number 2023/158541
Status In Force
Filing Date 2023-01-18
Publication Date 2023-08-24
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Parz, Wolfgang
  • Wang, Meng

Abstract

A semiconductor optical device (100) includes a first facet (110) bounding a first end of the semiconductor optical device (100). The semiconductor optical device further includes a waveguide (101) having a first end proximate the first facet (110), the first end of the waveguide being tapered towards the first facet (110). The first facet has a curvature to increase modal reflectivity at a first interface at which the first end of the waveguide (101) meets the first facet (110).

IPC Classes  ?

  • G02B 6/122 - Basic optical elements, e.g. light-guiding paths
  • G02F 1/00 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02B 6/136 - Integrated optical circuits characterised by the manufacturing method by etching
  • H01S 3/00 - Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
  • H01S 5/00 - Semiconductor lasers
  • H01S 5/10 - Construction or shape of the optical resonator

86.

Monolithic multi-I region diode limiters

      
Application Number 18306342
Grant Number 12080708
Status In Force
Filing Date 2023-04-25
First Publication Date 2023-08-17
Grant Date 2024-09-03
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Brogle, James Joseph
  • Bukowski, Joseph Gerard
  • Barter, Margaret Mary
  • Boles, Timothy Edward

Abstract

A number of diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a diode limiter includes a first diode having a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure, a second diode having a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure, and at least one passive component. The first diode includes a first effective intrinsic region of a first thickness, the second diode includes a second effective intrinsic region of a second thickness. The first thickness is greater than the second thickness. The passive component is over the intrinsic layer and electrically coupled as part of the diode limiter.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions; Redistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
  • H01L 23/66 - High-frequency adaptations
  • H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
  • H01L 29/868 - PIN diodes
  • H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
  • H01L 29/66 - Types of semiconductor device

87.

TECHNIQUES FOR LASER ALIGNMENT IN PHOTONIC INTEGRATED CIRCUITS

      
Application Number 18307362
Status Pending
Filing Date 2023-04-26
First Publication Date 2023-08-17
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Hemenway, Roe
  • Stagarescu, Cristian
  • Meerovich, Daniel
  • Green, Malcolm R.
  • Parz, Wolfgang
  • Ma, Jichi
  • Grzybowski, Richard Robert
  • Bickel, Nathan

Abstract

Techniques for efficient alignment of a semiconductor laser in a Photonic Integrated Circuit (PIC) are disclosed. In some embodiments, a photonic integrated circuit (PIC) may include a semiconductor laser that includes a laser mating surface, and a substrate that includes a substrate mating surface. A shape of the laser mating surface and a shape of the substrate mating surface may be configured to align the semiconductor laser with the substrate in three dimensions.

IPC Classes  ?

  • H01S 5/0233 - Mounting configuration of laser chips
  • G02B 6/42 - Coupling light guides with opto-electronic elements
  • H01S 5/023 - Mount members, e.g. sub-mount members
  • H01S 5/0235 - Method for mounting laser chips
  • H01S 5/02326 - Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
  • H01S 5/02345 - Wire-bonding
  • H01S 5/02375 - Positioning of the laser chips
  • H01S 5/026 - Monolithically integrated components, e.g. waveguides, monitoring photo-detectors or drivers

88.

BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY

      
Application Number 18121628
Status Pending
Filing Date 2023-03-15
First Publication Date 2023-08-10
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Fisher, Jeremy
  • Sheppard, Scott
  • Fayed, Khaled
  • Wood, Simon

Abstract

A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

IPC Classes  ?

  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
  • H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
  • H01L 29/205 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds in different semiconductor regions

89.

SEMICONDUCTOR LASERS AND PROCESSES FOR THE PLANARIZATION OF SEMICONDUCTOR LASERS

      
Application Number 18174250
Status Pending
Filing Date 2023-02-24
First Publication Date 2023-08-03
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Dow, Ali Badar Alamin
  • Bowker, Jason Daniel
  • Green, Malcolm R.

Abstract

A laser structure may include a substrate, an active region arranged on the substrate, and a waveguide arranged on the active region. The waveguide may include a first surface and a second surface that join to form a first angle relative to the active region. A material may be deposited on the first surface and the second surface of the waveguide.

IPC Classes  ?

  • H01S 5/223 - Buried stripe structure
  • H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
  • H01S 5/028 - Coatings
  • H01L 21/3105 - After-treatment
  • H01L 21/68 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for positioning, orientation or alignment
  • H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure
  • H01S 5/10 - Construction or shape of the optical resonator
  • H01S 5/024 - Arrangements for thermal management
  • H01S 5/042 - Electrical excitation
  • C23C 14/30 - Vacuum evaporation by wave energy or particle radiation by electron bombardment
  • H01S 5/00 - Semiconductor lasers
  • H01S 5/02 - Structural details or components not essential to laser action
  • H01S 5/343 - Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser

90.

METHODS, SYSTEMS, AND APPARATUSES FOR PASSIVE OPTICAL NETWORKS

      
Application Number US2023011653
Publication Number 2023/146986
Status In Force
Filing Date 2023-01-26
Publication Date 2023-08-03
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Zeydel, Bart

Abstract

In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.

IPC Classes  ?

91.

Adjusting eye heights and optical power levels of a multi-level optical signal

      
Application Number 18127586
Grant Number 11838058
Status In Force
Filing Date 2023-03-28
First Publication Date 2023-07-27
Grant Date 2023-12-05
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Draper, Daniel
  • Brownlee, Merrick

Abstract

A multi-level optical signal is sampled to generate an eye diagram. The signal can be adjusted when eyes in the eye diagram have different heights. More specifically, a first value is determined, and the height of a first eye is adjusted using the first value. The first value is multiplied by a stored factor to produce a second value, and the height of a second eye is adjusted using the second value, and so on for other eyes. As a result, eye heights are the same. Similarly, optical power levels of the signal can be adjusted when the levels are not equally spaced. As a result, the optical power levels are equally spaced.

IPC Classes  ?

  • H04B 10/524 - Pulse modulation
  • H04B 10/079 - Arrangements for monitoring or testing transmission systems; Arrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
  • H04B 10/2581 - Multimode transmission
  • H04B 10/50 - Transmitters

92.

METHODS, SYSTEMS, AND APPARATUSES FOR PASSIVE OPTICAL NETWORKS

      
Application Number 18101538
Status Pending
Filing Date 2023-01-25
First Publication Date 2023-07-27
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Zeydel, Bart

Abstract

In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.

IPC Classes  ?

93.

SUPPRESSION OF PARASITIC ACOUSTIC WAVES IN INTEGRATED CIRCUIT DEVICES

      
Application Number 18001141
Status Pending
Filing Date 2021-06-18
First Publication Date 2023-07-06
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Cueva, Gabriel R.
  • Boles, Timothy E.
  • Struble, Wayne Mack

Abstract

Structures for suppressing parasitic acoustic waves in semiconductor structures and integrated circuit devices are described. Such integrated circuit devices can, typically, produce undesirable acoustic wave resonances, and the acoustic waves can degrade the performance of the devices. In that context, some embodiments described herein relate to spoiling a conductive path that participates in the generation of acoustic waves. Some embodiments relate to spoiling acoustic characteristics of an acoustic resonant structure that may be present in the vicinity of the device. Combined embodiments that spoil the conductive path and acoustic characteristics are also possible.

IPC Classes  ?

  • H03H 9/02 - Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators - Details
  • H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
  • H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
  • H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
  • H01L 29/267 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups , , , , in different semiconductor regions

94.

Device having a coupled interstage transformer and process implementing the same

      
Application Number 17560811
Grant Number 12068265
Status In Force
Filing Date 2021-12-23
First Publication Date 2023-06-29
Grant Date 2024-08-20
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Marbell, Marvin

Abstract

A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.

IPC Classes  ?

  • H01L 23/66 - High-frequency adaptations
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
  • H01L 23/495 - Lead-frames
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different subgroups of the same main group of groups , or in a single subclass of ,

95.

MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON SILICON

      
Application Number 18170773
Status Pending
Filing Date 2023-02-17
First Publication Date 2023-06-29
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Carlson, Douglas
  • Boles, Timothy E.
  • Struble, Wayne Mack

Abstract

Various integrated circuits formed using gallium nitride and other materials are described. In one example, an integrated circuit includes a first integrated device formed over a first semiconductor structure in a first region of the integrated circuit, a second integrated device formed over a second semiconductor structure in a second region of the integrated circuit, and a passive component formed over a third region of the integrated circuit, between the first region and the second region. The third region comprises an insulating material, which can be glass in some cases. The insulating material extends through the semiconductor substrate and separates the semiconductor substrate between the first semiconductor structure and the second semiconductor structure.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/762 - Dielectric regions
  • H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
  • H01L 23/66 - High-frequency adaptations

96.

MICROWAVE INTEGRATED CIRCUITS INCLUDING GALLIUM-NITRIDE DEVICES ON SILICON

      
Application Number 18170794
Status Pending
Filing Date 2023-02-17
First Publication Date 2023-06-29
Owner MACOM Technology Solutions Holdings, Inc. (USA)
Inventor
  • Carlson, Douglas
  • Boles, Timothy E.
  • Struble, Wayne Mack

Abstract

Various methods of forming integrated circuits formed using gallium nitride and other materials are described. An example method includes forming a first integrated device over a first semiconductor structure in a first region of the integrated circuit, forming a second integrated device over a second semiconductor structure in a second region of the integrated circuit, etching a cavity in a third region of the of the integrated circuit located between the first region and the second region, filling the cavity with an insulating material, and forming a passive component over the insulating material in the third region of the integrated circuit. In other aspects, the method can include grinding a back side of a semiconductor substrate of the integrated circuit to electrically isolate the first semiconductor structure from the second semiconductor structure and, after the grinding, forming a ground plane over the back side of the semiconductor substrate.

IPC Classes  ?

  • H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
  • H01L 21/762 - Dielectric regions
  • H01L 21/8258 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by , , or
  • H01L 23/66 - High-frequency adaptations

97.

CONFIGURABLE METAL - INSULATOR - METAL CAPACITOR AND DEVICES AND PROCESSES IMPLEMENTING THE SAME

      
Application Number 17554971
Status Pending
Filing Date 2021-12-17
First Publication Date 2023-06-22
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Fisher, Jeremy

Abstract

A metal-insulator-metal (MIM) capacitor component that includes a substrate, where the metal-insulator-metal (MIM) capacitor component is configured to form a first capacitor with a top metal and a first bottom metal having a dielectric layer therebetween; and where the metal-insulator-metal (MIM) capacitor component is configured to form a second capacitor with the top metal and a second bottom metal having the dielectric layer therebetween. Additionally, the top metal, the dielectric layer, the first bottom metal, and the second bottom metal are arranged on the substrate.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind

98.

METHOD AND APPARATUS FOR ELECTROMIGRATION REDUCTION

      
Application Number US2022045368
Publication Number 2023/113902
Status In Force
Filing Date 2022-09-30
Publication Date 2023-06-22
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor Piccin, Yohan

Abstract

A semiconductor circuit configured to reduce electromigration. The circuit comprises a power rail and ground rail located on a first layer. A power finger and a ground finger are located on a second layer. Cells are located on the second layer, such that the one or more cells are electrically connected to a power finger and a ground finger. The circuit also includes one or more power vias electrically connecting the power rail to the power finger. The one or more power vias extend from the first layer to the second layer. One or more ground vias electrically connecting the ground rail to the ground finger, such that the one or more ground vias extend from the first layer to the second layer. The placement of the fingers on a different level than the rails establishing the fingers as non-contiguous sections thereby reducing electromigration and overcoming design analysis errors.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

99.

MULTI-TYPED INTEGRATED PASSIVE DEVICE (IPD) COMPONENTS AND DEVICES AND PROCESSES IMPLEMENTING THE SAME

      
Application Number 17555015
Status Pending
Filing Date 2021-12-17
First Publication Date 2023-06-22
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Marbell, Marvin
  • Jang, Haedong
  • Fisher, Jeremy
  • Noori, Basim

Abstract

A transistor device includes a metal submount; a transistor die arranged on said metal submount; a first integrated passive device (IPD) component that includes a first substrate arranged on said metal submount; and a second integrated passive device (IPD) component that includes a second substrate arranged on the metal submount. Additionally, the first substrate is a different material from the second substrate.

IPC Classes  ?

  • H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid state devices the devices being of types provided for in two or more different main groups of groups , or in a single subclass of , , e.g. forming hybrid circuits

100.

IPD COMPONENTS HAVING SIC SUBSTRATES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME

      
Application Number 17555106
Status Pending
Filing Date 2021-12-17
First Publication Date 2023-06-22
Owner MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC. (USA)
Inventor
  • Farrell, Donald
  • Marbell, Marvin
  • Fisher, Jeremy
  • Namishia, Dan
  • Sheppard, Scott
  • Etter, Dan

Abstract

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

IPC Classes  ?

  • H01L 23/495 - Lead-frames
  • H01L 23/64 - Impedance arrangements
  • H01L 23/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details of semiconductor or other solid state devices
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