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1.

POLICY-BASED PROCESSING OF AUTHENTICATION REQUESTS USING LOCATION DATA FOR CLOUD-HOSTED SYSTEMS AND APPLICATIONS

      
Application Number 18085226
Status Pending
Filing Date 2022-12-20
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor Batni, Dhruva Lakshmana Rao

Abstract

Disclosed are apparatuses, systems, and techniques that improve efficiency and decrease latency of processing of authorization requests by cloud-based access servers that evaluate access rights to access various cloud-based services. The techniques include but are not limited to using location tracking data to predict that a user is to move from an area served by a first access point of the cloud-based services to an area served by a second access point of the cloud-based services. The techniques further include proactively providing policy data and policy dependencies to the second access point to minimize latency of processing of access requests generated by the user.

IPC Classes  ?

2.

EFFICIENT FREQUENCY-BASED AUDIO RESAMPLING FOR USING NEURAL NETWORKS

      
Application Number 18068187
Status Pending
Filing Date 2022-12-19
First Publication Date 2024-06-20
Owner Nvidia Corporation (USA)
Inventor
  • Jjoshi, Suchitra Mandar
  • Nyayate, Mihir Manohar
  • Gode, Nitin Mahesh

Abstract

Systems and methods described relate to the enhancement of audio, such as through machine learning-based audio super-resolution processing. An efficient resampling approach can be used for audio data received at a lower frequency than is needed for an audio enhancement neural network. This audio data can be converted into the frequency domain using, and once in the frequency domain (e.g., represented using a spectrogram) this lower frequency data can be resampled to provide a frequency-based representation that is at the target input resolution for the neural network. To keep this resampling process lightweight, the upper frequency bands can be padded with zero value entries (or other such padding values). This resampled, higher frequency spectrogram can be provided as input to the neural network, which can perform an enhancement operation such as audio upsampling or super-resolution.

IPC Classes  ?

  • G10L 21/14 - Transforming into visible information by displaying frequency domain information
  • G10L 21/0232 - Processing in the frequency domain
  • G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks

3.

APPLICATION PROGRAMMING INTERFACE TO GENERATE DATA PACKETS

      
Application Number 18083544
Status Pending
Filing Date 2022-12-18
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Boccuzzi, Joseph
  • Kundu, Lopamudra

Abstract

Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

IPC Classes  ?

  • H04W 28/06 - Optimising, e.g. header compression, information sizing
  • G06F 9/54 - Interprogram communication

4.

APPLICATION PROGRAMMING INTERFACE TO GENERATE PACKAGING INFORMATION

      
Application Number 18083545
Status Pending
Filing Date 2022-12-18
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Boccuzzi, Joseph
  • Kundu, Lopamudra

Abstract

Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

IPC Classes  ?

  • H04W 48/18 - Selecting a network or a communication service

5.

APPLICATION PROGRAMMING INTERFACE TO GENERATE SYNCHRONIZATION INFORMATION

      
Application Number 18083546
Status Pending
Filing Date 2022-12-18
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Boccuzzi, Joseph
  • Kundu, Lopamudra

Abstract

Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

IPC Classes  ?

  • G06F 1/12 - Synchronisation of different clock signals
  • G06F 9/54 - Interprogram communication

6.

APPLICATION PROGRAMMING INTERFACE TO LOAD SYNCHRONIZATION INFORMATION

      
Application Number 18083547
Status Pending
Filing Date 2022-12-18
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Boccuzzi, Joseph
  • Kundu, Lopamudra

Abstract

Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

IPC Classes  ?

  • H04L 69/28 - Timers or timing mechanisms used in protocols
  • G06F 9/52 - Program synchronisation; Mutual exclusion, e.g. by means of semaphores
  • H04W 56/00 - Synchronisation arrangements

7.

REPLICATING PHYSICAL ENVIRONMENTS AND GENERATING 3D ASSETS FOR SYNTHETIC SCENE GENERATION

      
Application Number 18066135
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-06-20
Owner Nvidia Corporation (USA)
Inventor
  • Foco, Marco
  • Bódis-Szomorú, András
  • Deutsch, Isaac
  • Rozantsev, Artem
  • Shelley, Michael
  • State, Gavriel
  • Wang, Jiehan
  • Hu, Anita
  • Lafleche, Jean-Francois

Abstract

Approaches presented herein can provide for the automatic generation of a digital representation of an environment that may include multiple objects of various object types. An initial representation (e.g., a point cloud) of the environment can be generated from registered image or scan data, for example, and objects in the environment can be segmented and identified based at least on that initial representation. For objects that are recognized based on these segmentations, stored accurate representations can be substituted for those objects in the representation of the environment, and if no such model is available then a mesh or other representation of that object can be generated and positioned in the environment. A result can then include a 3D representation of a scene or environment in which objects are identified and segmented as individual objects, and representations of the scene or environment can be viewed, and interacted with, through various viewports, positions, and perspectives.

IPC Classes  ?

  • G06T 17/20 - Wire-frame description, e.g. polygonalisation or tessellation
  • G06T 7/33 - Determination of transform parameters for the alignment of images, i.e. image registration using feature-based methods
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks

8.

EGO TRAJECTORY PLANNING WITH RULE HIERARCHIES FOR AUTONOMOUS VEHICLES

      
Application Number 18335028
Status Pending
Filing Date 2023-06-14
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Veer, Sushant
  • Leung, Karen
  • Cosner, Ryan
  • Chen, Yuxiao
  • Pavone, Marco

Abstract

Autonomous vehicles (AVs) may need to contend with conflicting traveling rules and the AV controller would need to select the least objectionable control action. A rank-preserving reward function can be applied to trajectories derived from a rule hierarchy. The reward function can be correlated to a robustness vector derived for each trajectory. Thereby the highest ranked rules would result in the highest reward, and the lower ranked rules would result in lower reward. In some aspects, one or more optimizers, such as a stochastic optimizer can be utilized to improve the results of the reward calculation. In some aspects, a sigmoid function can be applied to the calculation to smooth out the step function used to calculate the robustness vector. The preferred trajectory selected using the results from the reward function can be communicated to an AV controller for implementation as a control action.

IPC Classes  ?

  • B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles
  • B60W 40/02 - Estimation or calculation of driving parameters for road vehicle drive control systems not related to the control of a particular sub-unit related to ambient conditions

9.

APPLICATION PROGRAMMING INTERFACE TO STORE INFORMATION IN FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number CN2022138418
Publication Number 2024/124376
Status In Force
Filing Date 2022-12-12
Publication Date 2024-06-20
Owner NVIDIA CORPORATION (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, 5G-NR information to be shared between one or more processes is stored by one or more statically-sized regions of linked storage locations in response to an application programming interface (API).

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • H04W 48/08 - Access restriction or access information delivery, e.g. discovery data delivery

10.

OBJECT POSE ESTIMATION

      
Application Number 18244050
Status Pending
Filing Date 2023-09-08
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Pavone, Marco
  • Yang, Heng

Abstract

Apparatuses, systems, and techniques to obtain prediction set(s) (e.g., region(s)) for keypoint prediction(s) based at least in part on data associated with an object, compute a set of candidate poses for the object based at least in part on the prediction set(s), and estimate an estimated object pose based at least in part on the set of candidate poses. The estimated object pose may be used to move a device. For example the estimated object pose may be used to provide collision-free motion generation for a real-world or virtual device (e.g., a robot, an autonomous machine, or a semi-autonomous machine). In at least one embodiment, at least a portion of the object pose estimation and/or at least a portion of the collision-free motion generation is performed in parallel.

IPC Classes  ?

  • B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles
  • B60W 50/00 - CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT - Details of control systems for road vehicle drive control not related to the control of a particular sub-unit
  • G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods

11.

REAL-TIME OBJECT TRACKING USING MOTION AND VISUAL CHARACTERISTICS FOR INTELLIGENT VIDEO ANALYTICS SYSTEMS

      
Application Number 18542389
Status Pending
Filing Date 2023-12-15
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Shin, Joonhwa
  • Li, Fangyu
  • Verjus, Hugo Maxence
  • Liu, Zheng
  • Purandare, Kaustubh

Abstract

A first visual appearance descriptor associated with a first object in an environment is obtained based on a first set of images of a first time period. The first object is subsequently absent from the environment in a second set of images of a second time period. A second visual appearance descriptor associated with a second object is obtained based on a third set of images, of a third time period subsequent to the second time period. A compound similarity metric between the first and second objects is obtained in view of visual appearance similarity and motion similarity metrics. The visual appearance similarity metric corresponds to a degree of similarity between the first and second visual appearance descriptors. An identifier associated with the second object is updated to correspond to an identifier associated with the first object in response to determining that the compound similarity metric meets a threshold value.

IPC Classes  ?

  • G06T 7/20 - Analysis of motion
  • G06V 10/74 - Image or video pattern matching; Proximity measures in feature spaces

12.

FREQUENCY-LOCKED AND PHASE-LOCKED LOOP-BASED CLOCK GLITCH DETECTION FOR SECURITY

      
Application Number 18595042
Status Pending
Filing Date 2024-03-04
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Song, Sanquan
  • Tell, Stephen G.
  • Nedovic, Nikola

Abstract

A glitch detection device includes an oscillator to generate multiple local clocks of multiple different phases and a sampling circuit to oversample, using the multiple local clocks, a system clock to generate multiple samples of the system clock. The device further includes a glitch detector to monitor a variation in pulse width of the system clock based on counting the multiple samples and to report a glitch in response to detecting a variation in the pulse width that exceeds a threshold value.

IPC Classes  ?

  • H03L 7/099 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L 7/089 - Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

13.

DYNAMICALLY REDUCING LATENCY IN PROCESSING PIPELINES

      
Application Number 18594099
Status Pending
Filing Date 2024-03-04
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Li, Sau Yan Keith
  • Schneider, Seth
  • Robson, Cody
  • Nordskog, Lars
  • Hansen, Charles
  • Dimitrov, Rouslan

Abstract

A weighted average execution time associated with each execution stage of a plurality of execution stages used to process a plurality of frames in parallel is obtained. The processing of each of the plurality of frames is performed at each of the plurality of execution stages in a sequential order, starting with an initial execution stage and continuing with each subsequent execution stage. A first largest weighted average execution time associated with one of the plurality of execution stages is determined. A delay to the initial execution stage prior to processing a first next frame is applied. The delay is determined based on the first largest weighted average execution time.

IPC Classes  ?

  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt

14.

APPLICATION PROGRAMMING INTERFACE TO WRITE INFORMATION

      
Application Number 18083548
Status Pending
Filing Date 2022-12-18
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Boccuzzi, Joseph
  • Kundu, Lopamudra

Abstract

Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

IPC Classes  ?

  • H04W 28/16 - Central resource management; Negotiation of resources or communication parameters, e.g. negotiating bandwidth or QoS [Quality of Service]
  • G06F 9/54 - Interprogram communication
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • H04W 52/54 - Signalisation aspects of the TPC commands, e.g. frame structure

15.

APPLICATION PROGRAMMING INTERFACE TO READ INFORMATION

      
Application Number 18083549
Status Pending
Filing Date 2022-12-18
First Publication Date 2024-06-20
Owner NVIDIA Corporation (USA)
Inventor
  • Boccuzzi, Joseph
  • Kundu, Lopamudra

Abstract

Apparatuses, systems, and techniques including APIs to enable one or more fifth generation new radio (5G-NR) network components to write, read, send, transmit, load, or otherwise obtain packaging, synchronization, and/or management information. For example, a processor comprising one or more circuits to perform an application programming interface (API) to cause fifth generation new radio (5G-NR) packaging, synchronization, or management information to be indicated to one or more accelerators.

IPC Classes  ?

  • H04L 67/133 - Protocols for remote procedure calls [RPC]
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

16.

APPLICATION PROGRAMMING INTERFACE TO ALLOCATE FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number CN2022138416
Publication Number 2024/124375
Status In Force
Filing Date 2022-12-12
Publication Date 2024-06-20
Owner NVIDIA CORPORATION (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, one or more statically-sized regions of linked storage locations are pre-allocated, in response to an application programming interface (API), to store 5G-NR information to be shared between one or more processes.

IPC Classes  ?

  • G06F 12/08 - Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

17.

ALLOCATING RADIO RESOURCES USING ARTIFICIAL INTELLIGENCE

      
Application Number US2023084133
Publication Number 2024/130034
Status In Force
Filing Date 2023-12-14
Publication Date 2024-06-20
Owner NVIDIA CORPORATION (USA)
Inventor
  • Huang, Yan
  • Delfeld, James
  • Gao, Yuan
  • Lin, Xingqin
  • Casas, Christian Ibars

Abstract

Apparatuses, systems, and techniques to allocate one or more compute resources to a user device. In at least one embodiment, one or more circuits cause one or more compute resources to be allocated to two or more fifth-generation (5G) radio access network (RAN) cells based, at least in part, on interference between the two or more 5G RAN cells.

IPC Classes  ?

  • H04W 72/23 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal
  • H04W 72/54 - Allocation or scheduling criteria for wireless resources based on quality criteria
  • H04W 72/541 - Allocation or scheduling criteria for wireless resources based on quality criteria using the level of interference

18.

APPLICATION PROGRAMMING INTERFACE TO DEALLOCATE FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number 18229298
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, one or more statically-sized regions of linked storage locations are deallocated, in response to an application programming interface (API), to free memory used to store 5G-NR information to be shared between one or more processes.

IPC Classes  ?

19.

APPLICATION PROGRAMMING INTERFACE TO STORE INFORMATION IN FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number 18229525
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, 5G-NR information to be shared between one or more processes is stored by one or more statically-sized regions of linked storage locations in response to an application programming interface (API).

IPC Classes  ?

  • H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
  • H04L 67/1001 - Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers

20.

APPLICATION PROGRAMMING INTERFACE TO INVALIDATE INFORMATION IN FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number 18229562
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, 5G-NR information stored by one or more statically-sized regions of linked storage locations is to be invalidated in response to an application programming interface (API).

IPC Classes  ?

21.

LUMINANCE-PRESERVING AND TEMPORALLY STABLE DALTONIZATION

      
Application Number 18491993
Status Pending
Filing Date 2023-10-23
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Ebelin, Johan Pontus
  • Crassin, Cyril
  • Akenine-Möller, Tomas Guy

Abstract

It is difficult for people with color vision deficiency (CVD) to distinguish between certain colors, e.g., reds and greens may be indistinguishable, causing a loss of information. Image recoloring, daltonization, techniques aim to improve the experience for people with CVD. Preserving luminance between the original image as seen by a person with normal color vision and someone with a CVD assists in preserving image appearance. Conventional algorithms attempt to daltonize images by exploiting the content of the image itself. While this is a suitable idea for an image in isolation, temporal inconsistencies (e.g., flickering) occur when applied to a stream of images, as a color c could be mapped to a color a in one frame and b in another. In contrast, the luminance-preserving technique operates on pixels and provides a consistent mapping and therefore is temporally stable.

IPC Classes  ?

  • G06T 11/00 - 2D [Two Dimensional] image generation
  • G06T 7/90 - Determination of colour characteristics

22.

OBJECT DETECTION AND DETECTION CONFIDENCE SUITABLE FOR AUTONOMOUS DRIVING

      
Application Number 18582358
Status Pending
Filing Date 2024-02-20
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Koivisto, Tommi
  • Janis, Pekka
  • Kuosmanen, Tero
  • Roman, Timo
  • Sarathy, Sriya
  • Zhang, William
  • Assaf, Nizar
  • Tracey, Colin

Abstract

In various examples, detected object data representative of locations of detected objects in a field of view may be determined. One or more clusters of the detected objects may be generated based at least in part on the locations and features of the cluster may be determined for use as inputs to a machine learning model(s). A confidence score, computed by the machine learning model(s) based at least in part on the inputs, may be received, where the confidence score may be representative of a probability that the cluster corresponds to an object depicted at least partially in the field of view. Further examples provide approaches for determining ground truth data for training object detectors, such as for determining coverage values for ground truth objects using associated shapes, and for determining soft coverage values for ground truth objects.

IPC Classes  ?

  • G01S 7/41 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisation; Target signature; Target cross-section
  • B60W 50/00 - CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT - Details of control systems for road vehicle drive control not related to the control of a particular sub-unit
  • G01S 7/48 - RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES - Details of systems according to groups , , of systems according to group
  • G01S 13/86 - Combinations of radar systems with non-radar systems, e.g. sonar, direction finder
  • G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
  • G01S 17/931 - Lidar systems, specially adapted for specific applications for anti-collision purposes of land vehicles
  • G06F 16/35 - Clustering; Classification
  • G06F 18/21 - Design or setup of recognition systems or techniques; Extraction of features in feature space; Blind source separation
  • G06F 18/214 - Generating training patterns; Bootstrap methods, e.g. bagging or boosting
  • G06F 18/23 - Clustering techniques
  • G06F 18/2413 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on distances to training or reference patterns
  • G06N 3/044 - Recurrent networks, e.g. Hopfield networks
  • G06N 3/045 - Combinations of networks
  • G06N 3/047 - Probabilistic or stochastic networks
  • G06N 3/048 - Activation functions
  • G06N 3/084 - Backpropagation, e.g. using gradient descent
  • G06N 20/00 - Machine learning
  • G06V 10/20 - Image preprocessing
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
  • G06V 10/46 - Descriptors for shape, contour or point-related descriptors, e.g. scale invariant feature transform [SIFT] or bags of words [BoW]; Salient regional features
  • G06V 10/762 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using clustering, e.g. of similar faces in social networks
  • G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
  • G06V 10/77 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]; Blind source separation
  • G06V 10/774 - Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting
  • G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestrians; Recognition of traffic objects, e.g. traffic signs, traffic lights or roads

23.

OPTIMIZING INTERMEDIATE OUTPUT ACCUMULATION OF PARALLEL PROCESSING OPERATIONS IN STREAMING AND LATENCY-SENSITIVE APPLICATIONS

      
Application Number 18077942
Status Pending
Filing Date 2022-12-08
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor Wachowicz, Dominik

Abstract

Disclosed are apparatuses, systems, and techniques for efficient parallel execution of multiple processes in real-time streaming and latency-sensitive applications. The techniques include but are not limited to executing in parallel multiple processing threads, storing data output by the multiple processing threads in respective accumulation buffers, and applying an aggregation function to the stored data to generate an aggregated data.

IPC Classes  ?

24.

FALLBACK MECHANISM FOR AUTO WHITE BALANCING

      
Application Number 18078670
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Taylor, Douglas
  • Khemka, Animesh
  • Dujardin, Eric

Abstract

Improved fallback mechanisms for auto white balancing are presented. In at least one embodiment, white balance correction factors produced by a first white balance technique are blended with white balance correction factors produced by a second white balance technique based on a confidence level in the white balance correction factors produced by the first white balance technique.

IPC Classes  ?

  • H04N 23/88 - Camera processing pipelines; Components thereof for processing colour signals for colour balance, e.g. white-balance circuits or colour temperature control
  • G01J 1/10 - Photometry, e.g. photographic exposure meter by comparison with reference light or electric value
  • G06T 7/90 - Determination of colour characteristics

25.

DOMAIN-CUSTOMIZABLE MODELS FOR CONVERSATIONAL AI SYSTEMS AND APPLICATIONS

      
Application Number 18064125
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Dong, Yi
  • Wu, Xianchao

Abstract

In various examples, systems and methods are disclosed that train a machine learning model(s)—such as a large language model (LLM)—for one or more specific domains. In some embodiments, the machine learning model(s) may include at least a base model(s) as well as additional parts, such as additional layers, associated with the domains for which the machine learning model(s) is being trained. As such, the parts of the machine learning model(s) may be trained separately, such that training data associated with a domain is used to train a part of the machine learning model(s) that is associated with the domain without training the other part(s) of the machine learning model(s). The systems and methods may then use these parts when deploying the machine learning model(s), such as by activating and/or deactivating parts based on the input data being processed.

IPC Classes  ?

  • G06N 5/043 - Distributed expert systems; Blackboards
  • G06F 40/40 - Processing or translation of natural language

26.

DISTURBANCE COMPENSATION USING CONTROL SYSTEMS FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18065484
Status Pending
Filing Date 2022-12-13
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Nasir, Mohammed
  • Murali, Vishal
  • Sun, Yue

Abstract

The present disclosure relates to determining an observed state of a system based at least on sensor data generated using one or more sensors of the system. The present disclosure further relates to generating disturbance data based at least on comparing an estimated state of the system with the observed state of the system. The present disclosure further relates to updating one or more disturbance terms of a state space formulation based at least on the disturbance data. The present disclosure further relates to generating, based at least on the state space formulation, a control command that directs one or more operations of the system according to plan data indicative of a plan for completing one or more tasks of the system.

IPC Classes  ?

  • B60W 30/18 - Propelling the vehicle
  • B60W 40/10 - Estimation or calculation of driving parameters for road vehicle drive control systems not related to the control of a particular sub-unit related to vehicle motion

27.

BRIGHTNESS BASED CHROMATICITY WEIGHTING FOR IMPROVED ILLUMINANT COLOR ESTIMATION FOR AUTO WHITE BALANCING

      
Application Number 18078667
Status Pending
Filing Date 2022-12-09
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Taylor, Douglas
  • Khemka, Animesh

Abstract

Apparatuses, systems, and techniques for white balancing an image are presented. In at least one embodiment, a chromaticity-based weighting function is determined based at least on an estimated scene brightness of the image and applied to exclude or minimize the impact of large colored portions or objects within an image when estimating an illuminant color.

IPC Classes  ?

  • H04N 23/88 - Camera processing pipelines; Components thereof for processing colour signals for colour balance, e.g. white-balance circuits or colour temperature control
  • G06T 7/90 - Determination of colour characteristics
  • H04N 9/77 - Circuits for processing the brightness signal and the chrominance signal relative to each other, e.g. adjusting the phase of the brightness signal relative to the colour signal, correcting differential gain or differential phase
  • H04N 23/71 - Circuitry for evaluating the brightness variation
  • H04N 23/76 - Circuitry for compensating brightness variation in the scene by influencing the image signals

28.

APPLICATION PROGRAMMING INTERFACE TO ALLOCATE FIFTH GENERATION NEW RADIO (5G-NR) STORAGE

      
Application Number 18229288
Status Pending
Filing Date 2023-08-02
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, one or more statically-sized regions of linked storage locations are pre-allocated, in response to an application programming interface (API), to store 5G-NR information to be shared between one or more processes.

IPC Classes  ?

29.

NEURAL VECTOR FIELDS FOR 3D SHAPE GENERATION

      
Application Number 18361587
Status Pending
Filing Date 2023-07-28
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Hao, Zekun
  • Liu, Ming-Yu
  • Mallya, Arun Mohanray

Abstract

Synthesis of high-quality 3D shapes with smooth surfaces has various creative and practical use cases, such as 3D content creation and CAD modeling. A vector field decoder neural network is trained to predict a generative vector field (GVF) representation of a 3D shape from a latent representation (latent code or feature volume) of the 3D shape. The GVF representation is agnostic to surface orientation, all dimensions of the vector field vary smoothly, the GVF can represent both watertight and non-watertight 3D shapes, and there is a one-to-one mapping between a predicted 3D shape and the ground truth 3D shape (i.e., the mapping is bijective). The vector field decoder can synthesize 3D shapes in multiple categories and can also synthesize 3D shapes for objects that were not included in the training dataset. In other words, the vector field decoder is also capable of zero-shot generation.

IPC Classes  ?

  • G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts

30.

APPLICATION MANAGEMENT PLATFORM FOR HYPER-CONVERGED CLOUD INFRASTRUCTURES

      
Application Number 18416320
Status Pending
Filing Date 2024-01-18
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Vijaywargiya, Vishvesh
  • Adithya V, Lalit
  • Duraisamy, Krishnan
  • Rajani, Rohit
  • Vadlamudi, Gopi
  • Stock, Andrew
  • Pelavin, Alexander
  • Mishra, Shivam
  • Kotian, Prathik

Abstract

An application management platform comprising at least a packaging and bundling component, a deployment management component, and an update component. The packaging and bundling component versions, packages, and bundles a plurality of infrastructure components for a remote data center. The deployment management component provisions one or more nodes of the remote data center with the plurality of infrastructure components for an application. The update component monitors available updates to one or more of the plurality of infrastructure components used by the remote data center and facilitates update of the one or more of the plurality of infrastructure components at the remote data center.

IPC Classes  ?

31.

TRANSFORMERS AS NEURAL RENDERERS

      
Application Number 18516625
Status Pending
Filing Date 2023-11-21
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Wang, Yue
  • Pavone, Marco

Abstract

Apparatuses, systems, and techniques to use one or more machine learning processes to obtain a set of feature values based at least in part on a set of locations along a ray that intersects an object. A color value is obtained based at least in part on the set of feature values. A view of the object may be generated using the color value. A path of motion may be determined based at least in part on the color value and used to cause a device to move.

IPC Classes  ?

32.

RELIABLE LINK MANAGEMENT FOR A HIGH-SPEED SIGNALING INTERCONNECT

      
Application Number 18587111
Status Pending
Filing Date 2024-02-26
First Publication Date 2024-06-13
Owner NVIDIA Corporation (USA)
Inventor
  • Kumar, Seema
  • Chadha, Ish

Abstract

A device includes receiver circuitry to receive incoming signals on a clock lane and data lanes and detection circuitry. The detection circuitry is to monitor the incoming signals on the clock lane, and determine that an incoming pattern of the incoming signals on the clock lane does not correspond to a clock pattern associated with communicating data on the data lanes. The detection circuitry is to initiate a power-down sequence in response to determining that the incoming pattern does not correspond to the clock pattern.

IPC Classes  ?

  • H04L 7/00 - Arrangements for synchronising receiver with transmitter

33.

APPLICATION PROGRAMMING INTERFACE TO DEALLOCATE FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number CN2022138042
Publication Number 2024/119497
Status In Force
Filing Date 2022-12-09
Publication Date 2024-06-13
Owner NVIDIA CORPORATION (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock-free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, one or more statically-sized regions of linked storage locations are deallocated, in response to an application programming interface (API), to free memory used to store 5G-NR information to be shared between one or more processes.

IPC Classes  ?

  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

34.

APPLICATION PROGRAMMING INTERFACE TO INVALIDATE INFORMATION IN FIFTH GENERATION NEW RADIO (5G-NR) STATICALLY-SIZED LINKED STORAGE

      
Application Number CN2022138053
Publication Number 2024/119499
Status In Force
Filing Date 2022-12-09
Publication Date 2024-06-13
Owner NVIDIA CORPORATION (USA)
Inventor Wu, Jinyou

Abstract

Apparatuses, systems, and techniques to perform and facilitate lock- free data sharing between processes performing computations in fifth generation (5G) new radio (NR) wireless communication. In at least one embodiment, 5G-NR information stored by one or more statically-sized regions of linked storage locations is to be invalidated in response to an application programming interface (API).

IPC Classes  ?

  • G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs

35.

GENERATING COMPLETE THREE-DIMENSIONAL SCENE GEOMETRIES USING MACHINE LEARNING

      
Application Number 18339936
Status Pending
Filing Date 2023-06-22
First Publication Date 2024-06-06
Owner NVIDIA CORPORATION (USA)
Inventor
  • Zhang, Dongsu
  • Kar, Amlan
  • Williams, Francis
  • Gojcic, Zan
  • Kreis, Karsten
  • Fidler, Sanja

Abstract

In various examples, a technique for performing three-dimensional (3D) scene completion includes determining an initial representation of a first 3D scene. The technique also includes executing a machine learning model to generate a first update to the initial representation at a previous time step and a second update to the initial representation at a current time step, wherein the second update is generated based at least on a threshold applied to a set of predictions corresponding to the first update. The technique also includes generating a 3D model of the 3D scene based at least on the second update to the initial representation.

IPC Classes  ?

  • G06T 17/10 - Volume description, e.g. cylinders, cubes or using CSG [Constructive Solid Geometry]

36.

ALIAS-FREE TAGGED ERROR CORRECTING CODES FOR MACHINE MEMORY OPERATIONS

      
Application Number 18485132
Status Pending
Filing Date 2023-10-11
First Publication Date 2024-06-06
Owner NVIDIA Corp. (USA)
Inventor
  • Sullivan, Michael B.
  • Hassan, Mohamed Tarek Bnziad Mohamed
  • Jaleel, Aamer

Abstract

Implicit Memory Tagging (IMT) mechanisms utilizing alias-free memory tags that enable hardware-assisted memory tagging without incurring storage overhead above those incurred by conventional tagging mechanisms, while providing enhanced data integrity and memory security. The IMT mechanisms enhance the utility of error correcting codes (ECCs) to test memory tags in addition to the traditional utility of ECCs for detecting and correcting data errors and enable a finer granularity of memory tagging than many conventional approaches.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

37.

DISTRIBUTION OF QUANTUM STATE VECTOR ELEMENTS ACROSS NETWORK DEVICES IN QUANTUM COMPUTING SIMULATION

      
Application Number 18526829
Status Pending
Filing Date 2023-12-01
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor Morino, Shinya

Abstract

Aspects of this technical solution can identify, based at least on a representation of a quantum computing circuit, a first node of a topology of a computing platform configured to simulate at least a portion of the quantum computing circuit, compute a first metric indicating a first latency including the first node, the first latency based at least on a portion of the topology including the first node, select a second node of the topology having a second metric indicating a second latency less than the first latency, the second latency based at least on a portion of the topology including the second node, and simulate the quantum computing circuit on the computing platform using the second node.

IPC Classes  ?

  • G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers
  • G06N 10/40 - Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control

38.

GENERATING VARIATIONAL DIALOGUE RESPONSES FROM STRUCTURED DATA FOR CONVERSATIONAL AI SYSTEMS AND APPLICATIONS

      
Application Number 18061027
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Mahabaleshwarkar, Ameya Sunil
  • Wang, Zhilin
  • Olabiyi, Oluwatobi

Abstract

In various examples, systems and methods are disclosed relating to generating dialogue responses from structured data for conversational artificial intelligence (AI) systems and applications. Systems and methods are disclosed for training or updating a machine learning model—such as a deep neural network—for deployment using structured data from dialogues of multiple domains. The systems and methods can generate responses to users to provide a more natural user experience, such as by generating alternative outputs that vary in syntax with respect to how the outputs incorporate data used to respond to user utterances, while still accurately providing information to satisfy requests from users.

IPC Classes  ?

39.

EPOCH-BASED MECHANISM FOR PROVIDING DATA INTEGRITY AND RELIABILITY IN A MESSAGING SYSTEM

      
Application Number 18074362
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Klenk, Benjamin
  • Davis, Al
  • Dennison, Larry Robert

Abstract

Messaging protocols used by components in a messaging system to exchange messages conventionally use a reliability mechanism to ensure that each message sent by a sender is received, without compromise, by the intended receiver. Typically, this reliability mechanism involves use of a returned acknowledgement message to the message sender, with automatic retransmission of the message by the sender when the acknowledgement message is not received (e.g. within a defined timeframe). However, existing acknowledgement-based reliability mechanisms require that a sender identifier be included in the message header, which increases the overhead of the message. The present disclosure provides an epoch-based reliability mechanism that allows the sender identifier to be omitted from the message header to minimize overhead and maximize the efficient use of the available bandwidth.

IPC Classes  ?

  • G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures

40.

DATASET GENERATION USING LARGE LANGUAGE MODELS

      
Application Number 18075942
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Nagaraju, Divija
  • Parisien, Christopher

Abstract

Disclosed are systems and techniques that may generate datasets for training task-oriented dialogue systems. The techniques include generating natural language queries by selecting a template query, sampling one or more tokens from a data store of domain-specific tokens, modifying the selected template query using the one or more sampled tokens to generate a query prompt, and using a natural language generative machine-learning model to generate, based on the query prompt, a respective natural language query of the subset of the plurality of natural language queries, and causing the generated plurality of natural language queries to be provided to a machine-learning model training engine configured to train, using the generated plurality of natural language queries, a conversational machine-learning model to perform a domain-specific conversational task.

IPC Classes  ?

  • G06F 40/56 - Natural language generation
  • G06F 40/284 - Lexical analysis, e.g. tokenisation or collocates

41.

GENERATING GLOBAL HIERARCHICAL SELF-ATTENTION

      
Application Number 18130648
Status Pending
Filing Date 2023-04-04
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Hatamizadeh, Ali
  • Heinrich, Gregory
  • Yin, Hongxu
  • Alvarez Lopez, Jose Manuel
  • Kautz, Jan
  • Molchanov, Pavlo

Abstract

Apparatuses, systems, and techniques of using one or more machine learning processes (e.g., neural network(s)) to process data (e.g., using hierarchical self-attention). In at least one embodiment, image data is classified using hierarchical self-attention generated using carrier tokens that are associated with windowed subregions of the image data, and local attention generated using local tokens within the windowed subregions and the carrier tokens.

IPC Classes  ?

42.

APPLICATION PROGRAMMING INTERFACE TO INDICATE ACCELERATOR ERROR HANDLERS

      
Application Number US2023081208
Publication Number 2024/118526
Status In Force
Filing Date 2023-11-27
Publication Date 2024-06-06
Owner NVIDIA CORPORATION (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.

IPC Classes  ?

  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

43.

APPLICATION PROGRAMMING INTERFACE TO CAUSE PERFORMANCE OF ACCELERATOR OPERATIONS

      
Application Number US2023081356
Publication Number 2024/118609
Status In Force
Filing Date 2023-11-28
Publication Date 2024-06-06
Owner NVIDIA CORPORATION (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more operations in a sequence of operations to be performed by one or more accelerators within a heterogeneous processor.

IPC Classes  ?

  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/54 - Interprogram communication

44.

SLOT FILLING USING A ZERO SHOT MODEL FOR CONVERSATIONAL AI SYSTEMS AND APPLICATIONS

      
Application Number 18074394
Status Pending
Filing Date 2022-12-02
First Publication Date 2024-06-06
Owner NVIDIA CORPORATION (USA)
Inventor
  • Das, Shubhadeep
  • Lee, Yi-Hui
  • Olabiyi, Oluwatobi
  • Wang, Zhilin

Abstract

In various examples, a technique for slot filling includes receiving a natural language sentence from a user and identifying a first mention span included in the natural language sentence. The technique also includes determining, using a first machine learning model, that the first mention span is associated with a first slot class included in a set of slot classes based on a set of slot class descriptions corresponding to the set of slot classes.

IPC Classes  ?

  • G06F 40/56 - Natural language generation
  • G06F 40/284 - Lexical analysis, e.g. tokenisation or collocates

45.

PREPROCESSING DATA USING A NETWORK INTERFACE

      
Application Number 18076221
Status Pending
Filing Date 2022-12-06
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Ihsani, Alvin
  • Arazi, Shaul
  • Agostini, Elena
  • Tasinga, Penn
  • Lacey, Jr., Carl Everett
  • Groff, Dana
  • Levi, Dotan David
  • Wasko, Wojciech
  • Nath, Vishwesh
  • Alle, Sachidanand

Abstract

Methods and systems for obtaining data having a first format, converting the data to a second format, storing the converted data in memory accessible by at least one parallel processing unit, and processing the converted data stored in the memory using the at least one parallel processing unit.

IPC Classes  ?

  • G06N 5/04 - Inference or reasoning models
  • G16H 30/20 - ICT specially adapted for the handling or processing of medical images for handling medical images, e.g. DICOM, HL7 or PACS

46.

GENERATING A MOTION PLAN TO POSITION AT LEAST A PORTION OF A DEVICE WITH RESPECT TO A REGION

      
Application Number 18120864
Status Pending
Filing Date 2023-03-13
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Hermans, Tucker Ryer
  • Pavlasek, Jana
  • Tozeto Ramos, Fabio

Abstract

Apparatuses, systems, and techniques to perform inference to determine a trajectory based at least in part on a loss function including a cost associated with an amount of divergence between a set of terminal states and a set of goal states within a goal region.

IPC Classes  ?

  • G05D 1/02 - Control of position or course in two dimensions
  • G05D 1/00 - Control of position, course, altitude, or attitude of land, water, air, or space vehicles, e.g. automatic pilot

47.

DETERMINING INTENTS AND RESPONSES USING MACHINE LEARNING IN CONVERSATIONAL AI SYSTEMS AND APPLICATIONS

      
Application Number 18173622
Status Pending
Filing Date 2023-02-23
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Das, Shubhadeep
  • Bhattacharya, Sumit Kumar
  • Olabiyi, Oluwatobi

Abstract

In various examples, hybrid models for determining intents in conversational AI systems and applications are disclosed. Systems and methods are disclosed that use a machine learning model(s) and a data file(s) that associates requests (e.g., questions) with responses (e.g., answers) in order to generate final responses to requests. For instance, the machine learning model(s) may determine confidence scores that indicate similarities between the requests from the data file(s) and an input request represented by text data. The data file(s) is then used to determine, based on the confidence scores, one of the responses that is associated with one of the requests that is related to the input request. Additionally, the response may then used to generate a final response to the input request.

IPC Classes  ?

48.

VISION TRANSFORMER FOR IMAGE GENERATION

      
Application Number 18222725
Status Pending
Filing Date 2023-07-17
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Hatamizadeh, Ali
  • Song, Jiaming
  • Kautz, Jan
  • Vahdat, Arash

Abstract

Apparatuses, systems, and techniques to generate images. In at least one embodiment, one or more machine learning models generate an output image based, at least in part, on calculating attention scores using time embeddings.

IPC Classes  ?

  • G06T 5/00 - Image enhancement or restoration
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 7/00 - Image analysis

49.

POLICY PLANNING USING BEHAVIOR MODELS FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18354892
Status Pending
Filing Date 2023-07-19
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Chen, Yuxiao
  • Karkus, Peter
  • Ivanovic, Boris
  • Weng, Xinshuo
  • Pavone, Marco

Abstract

In various examples, policy planning using behavior models for autonomous and semi-autonomous systems and applications is described herein. Systems and methods are disclosed that determine a policy for navigating a vehicle, such as a semi-autonomous vehicle or an autonomous vehicle (or other machine), where the policy allows for multistage reasoning that leverages future reactive behaviors of one or more other objects. For instance, a first behavior model (e.g., a trajectory tree) may be generated that represents candidate trajectories for the vehicle and one or more second behavior models (e.g., one or more scenario trees) may be generated that respectively represent future behaviors of the other object(s). The first behavior model and the second behavior model(s) may then be processed, such as in a closed-loop simulation based on a realistic data-driven traffic model, to determine the policy for navigating the vehicle.

IPC Classes  ?

  • B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles

50.

HYBRID DIFFERENTIABLE RENDERING FOR LIGHT TRANSPORT SIMULATION SYSTEMS AND APPLICATIONS

      
Application Number 18441486
Status Pending
Filing Date 2024-02-14
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Chen, Wenzheng
  • Litalien, Joey
  • Gao, Jun
  • Wang, Zian
  • Fuji Tsang, Clement Tse Tsian Christophe Louis
  • Khamis, Sameh
  • Litany, Or
  • Fidler, Sanja

Abstract

In various examples, information may be received for a 3D model, such as 3D geometry information, lighting information, and material information. A machine learning model may be trained to disentangle the 3D geometry information, the lighting information, and/or material information from input data to provide the information, which may be used to project geometry of the 3D model onto an image plane to generate a mapping between pixels and portions of the 3D model. Rasterization may then use the mapping to determine which pixels are covered and in what manner, by the geometry. The mapping may also be used to compute radiance for points corresponding to the one or more 3D models using light transport simulation. Disclosed approaches may be used in various applications, such as image editing, 3D model editing, synthetic data generation, and/or data set augmentation.

IPC Classes  ?

  • G06T 15/06 - Ray-tracing
  • G06T 15/50 - Lighting effects
  • G06T 19/20 - Editing of 3D images, e.g. changing shapes or colours, aligning objects or positioning parts

51.

SIMULATING REALISTIC TEST DATA FROM TRANSFORMED REAL-WORLD SENSOR DATA FOR AUTONOMOUS MACHINE APPLICATIONS

      
Application Number 18442753
Status Pending
Filing Date 2024-02-15
First Publication Date 2024-06-06
Owner NVIDIA Corporation (USA)
Inventor
  • Hong, Jesse
  • Muller, Urs
  • Firner, Bernhard
  • Yang, Zongyi
  • Daw, Joyjit
  • Nister, David
  • Valenti, Roberto Giuseppe Luca
  • Aviv, Rotem

Abstract

In various examples, sensor data recorded in the real-world may be leveraged to generate transformed, additional, sensor data to test one or more functions of a vehicle—such as a function of an AEB, CMW, LDW, ALC, or ACC system. Sensor data recorded by the sensors may be augmented, transformed, or otherwise updated to represent sensor data corresponding to state information defined by a simulation test profile for testing the vehicle function(s). Once a set of test data has been generated, the test data may be processed by a system of the vehicle to determine the efficacy of the system with respect to any number of test criteria. As a result, a test set including additional or alternative instances of sensor data may be generated from real-world recorded sensor data to test a vehicle in a variety of test scenarios.

IPC Classes  ?

  • G01M 17/007 - Wheeled or endless-tracked vehicles
  • B60W 30/08 - Predicting or avoiding probable or impending collision
  • B60W 30/12 - Lane keeping
  • B60W 30/14 - Cruise control
  • B60W 50/00 - CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT - Details of control systems for road vehicle drive control not related to the control of a particular sub-unit
  • B60W 50/04 - Monitoring the functioning of the control system
  • B60W 60/00 - Drive control systems specially adapted for autonomous road vehicles
  • G06F 11/36 - Preventing errors by testing or debugging of software
  • G06V 10/774 - Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting
  • G06V 20/56 - Context or environment of the image exterior to a vehicle by using sensors mounted on the vehicle
  • G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time

52.

APPLICATION PROGRAMMING INTERFACE TO TRANSFER INFORMATION BETWEEN ACCELERATOR MEMORY

      
Application Number US2023081364
Publication Number 2024/118616
Status In Force
Filing Date 2023-11-28
Publication Date 2024-06-06
Owner NVIDIA CORPORATION (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to transfer information between memory of two or more accelerators.

IPC Classes  ?

53.

APPLICATION PROGRAMMING INTERFACE TO INDICATE STORAGE OF ACCELERATOR ERRORS

      
Application Number US2023081368
Publication Number 2024/118620
Status In Force
Filing Date 2023-11-28
Publication Date 2024-06-06
Owner NVIDIA CORPORATION (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more memory regions to store error information from one or more accelerators within a heterogeneous processor.

IPC Classes  ?

  • G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance

54.

QUERY RESPONSE GENERATION USING STRUCTURED AND UNSTRUCTURED DATA FOR CONVERSATIONAL AI SYSTEMS AND APPLICATIONS

      
Application Number 18172571
Status Pending
Filing Date 2023-02-22
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Das, Shubhadeep
  • Bhattacharya, Sumit Kumar
  • Olabiyi, Oluwatobi

Abstract

In various examples, contextual data may be generated using structured and unstructured data for conversational AI systems and applications. Systems and methods are disclosed that use structured data (converted to unstructured form) and unstructured data, such as from a knowledge database(s), to generate contextual data. For instance, the contextual data may represent text (e.g., narratives), where a first portion of the text is generated using the structured data and a second portion of the text is generated using the unstructured data. The systems and methods may then use a neural network(s), such as a neural network(s) associated with a dialogue manager, to process input data representing a request (e.g., a query) and the contextual data in order to generate a response to the request. For instance, if the request includes a query for information associated with a topic, the neural network(s) may generate a response that includes the requested information.

IPC Classes  ?

55.

TENSOR MAP CACHE STORAGE

      
Application Number 18219622
Status Pending
Filing Date 2023-07-07
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Minkin, Alexander Lev
  • Edwards, Harold Carter
  • Narawane, Yashwardhan

Abstract

Apparatuses, systems, and techniques to store one or more tensor maps in one or more cache storages. In at least one embodiment, a processor includes one or more tensor acceleration logic circuits to cause one or more tensor maps to be stored in one or more cache storages.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

56.

SAFETY PROCEDURE ANALYSIS FOR OBSTACLE AVOIDANCE IN AUTONOMOUS VEHICLES

      
Application Number 18432887
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Nister, David
  • Lee, Hon-Leung
  • Ng, Julia
  • Wang, Yizhou

Abstract

In various examples, a current claimed set of points representative of a volume in an environment occupied by a vehicle at a time may be determined. A vehicle-occupied trajectory and at least one object-occupied trajectory may be generated at the time. An intersection between the vehicle-occupied trajectory and an object-occupied trajectory may be determined based at least in part on comparing the vehicle-occupied trajectory to the object-occupied trajectory. Based on the intersection, the vehicle may then execute the first safety procedure or an alternative procedure that, when implemented by the vehicle when the object implements the second safety procedure, is determined to have a lesser likelihood of incurring a collision between the vehicle and the object than the first safety procedure.

IPC Classes  ?

  • B60W 30/09 - Taking automatic action to avoid collision, e.g. braking and steering
  • B60W 30/095 - Predicting travel path or likelihood of collision

57.

DYNAMIC ALLOCATION OF COMPUTE RESOURCES FOR HIGHLIGHT GENERATION IN CLOUD GAMING SYSTEMS

      
Application Number 18432957
Status Pending
Filing Date 2024-02-05
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Holmes, Stephen
  • Gervais, Pierre

Abstract

In various examples, compute resources may be allocated for highlight generation in cloud gaming systems. Systems and methods are disclosed that distribute, between and among various devices, processing including user interface generation and overlay, analysis of game streams for actionable events, generation of highlights, storage of highlights, and sharing of highlights. The distribution of processing or compute resources within the cloud gaming system may be dependent on system information of various devices and/or networks. Recordings, snapshots, and/or other highlights may be generated within the cloud gaming system using the determined distribution of compute resources.

IPC Classes  ?

  • A63F 13/86 - Watching games played by other players
  • A63F 13/355 - Performing operations on behalf of clients with restricted processing capabilities, e.g. servers transform changing game scene into an MPEG-stream for transmitting to a mobile phone or a thin client
  • A63F 13/537 - Controlling the output signals based on the game progress involving additional visual information provided to the game scene, e.g. by overlay to simulate a head-up display [HUD] or displaying a laser sight in a shooting game using indicators, e.g. showing the condition of a game character on screen

58.

CHANNEL ESTIMATION USING ARTIFICIAL INTELLIGENCE

      
Application Number 18058692
Status Pending
Filing Date 2022-11-23
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor Delfeld, James Hansen

Abstract

Apparatuses, systems, and techniques to estimate one or more wireless channels between one or more user devices and a base station. In at least one embodiment, one or more circuits use one or more groups of two or more reflected wireless reference signals to estimate the one or more wireless channels based, at least in part, on one or more bandlimited functions.

IPC Classes  ?

59.

SENSOR FUSION USING ULTRASONIC SENSORS FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18060376
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Weikersdorfer, David
  • Lin, Qian
  • Jhunjhunwala, Aman
  • Wirbel, Emilie Lucie Eloïse
  • Oh, Sangmin
  • Park, Minwoo
  • Cheon, Gyeong Woo
  • Rajala, Arthur Henry
  • Chen, Bor-Jeng

Abstract

In various examples, techniques for sensor-fusion based object detection and/or free-space detection using ultrasonic sensors are described. Systems may receive sensor data generated using one or more types of sensors of a machine. In some examples, the systems may then process at least a portion of the sensor data to generate input data, where the input data represents one or more locations of one or more objects within an environment. The systems may then input at least a portion of the sensor data and/or at least a portion of the input data into one or more neural networks that are trained to output one or more maps or other output representations associated with the environment. In some examples, the map(s) may include a height, an occupancy, and/or height/occupancy map generated, e.g., from a birds-eye-view perspective. The machine may use these outputs to perform one or more operations.

IPC Classes  ?

  • G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
  • G01S 15/86 - Combinations of sonar systems with lidar systems; Combinations of sonar systems with systems not using wave reflection

60.

SENSOR FUSION USING ULTRASONIC SENSORS FOR AUTONOMOUS SYSTEMS AND APPLICATIONS

      
Application Number 18060444
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Weikersdorfer, David
  • Lin, Qian
  • Jhunjhunwala, Aman
  • Wirbel, Emilie Lucie Eloïse
  • Oh, Sangmin
  • Park, Minwoo
  • Cheon, Gyeong Woo
  • Rajala, Arthur Henry
  • Chen, Bor-Jeng

Abstract

In various examples, techniques for sensor-fusion based object detection and/or free-space detection using ultrasonic sensors are described. Systems may receive sensor data generated using one or more types of sensors of a machine. In some examples, the systems may then process at least a portion of the sensor data to generate input data, where the input data represents one or more locations of one or more objects within an environment. The systems may then input at least a portion of the sensor data and/or at least a portion of the input data into one or more neural networks that are trained to output one or more maps or other output representations associated with the environment. In some examples, the map(s) may include a height, an occupancy, and/or height/occupancy map generated, e.g., from a birds-eye-view perspective. The machine may use these outputs to perform one or more operations

IPC Classes  ?

  • G01S 15/931 - Sonar systems specially adapted for specific applications for anti-collision purposes of land vehicles
  • G01S 15/86 - Combinations of sonar systems with lidar systems; Combinations of sonar systems with systems not using wave reflection

61.

SIMULATING QUANTUM COMPUTING CIRCUITS USING KRONECKER FACTORIZATION

      
Application Number 18060498
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor Jones, Matthew

Abstract

In various examples, systems and methods for simulation of quantum computing circuits using Kronecker factorization are provided. A partitioned quantum computing circuit may be generated by partitioning the quantum computing circuit using at least one partition boundary with respect to its state vector, to subdivide the quantum computing circuit into a plurality of circuit partitions. Circuit instances may be generated for the circuit partitions, where at least one circuit partition comprises a circuit instance that includes at least one operator derived from a Kronecker factorization that corresponds to a quantum operator that operates using qudits from more than one of the circuit partitions. A representation of at least a component of a state of the state vector for the quantum computing circuit may be generated based at least on simulating the at least one circuit instance for the circuit partitions.

IPC Classes  ?

  • G06N 10/20 - Models of quantum computing, e.g. quantum circuits or universal quantum computers

62.

APPLICATION PROGRAMMING INTERFACE TO CAUSE PERFORMANCE OF ACCELERATOR OPERATIONS

      
Application Number 18070084
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more operations in a sequence of operations to be performed by one or more accelerators within a heterogeneous processor.

IPC Classes  ?

63.

APPLICATION PROGRAMMING INTERFACE TO INDICATE ACCELERATOR ERROR HANDLERS

      
Application Number 18070148
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/54 - Interprogram communication

64.

APPLICATION PROGRAMMING INTERFACE TO INDICATE STORAGE OF ACCELERATOR ERRORS

      
Application Number 18070156
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more memory regions to store error information from one or more accelerators within a heterogeneous processor.

IPC Classes  ?

65.

APPLICATION PROGRAMMING INTERFACE TO TRANSFER INFORMATION BETWEEN ACCELERATOR MEMORY

      
Application Number 18070180
Status Pending
Filing Date 2022-11-28
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Ravi, Karthik Raghavan
  • Jain, Ashutosh
  • Suresh, Rahul

Abstract

Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to transfer information between memory of two or more accelerators.

IPC Classes  ?

66.

APPLICATION PROGRAMMING INTERFACE TO PROVIDE MEMORY TRANSACTION INFORMATION

      
Application Number 18081547
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to provide memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information about one or more memory transactions to be provided to one or more users.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

67.

APPLICATION PROGRAMMING INTERFACE TO CHECK MEMORY TRANSACTION INFORMATION

      
Application Number 18081550
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to check memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided in a token by one or more users about one or more memory transactions after a first amount of time indicated by one or more users.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

68.

COLLISION DETECTION FOR OBJECT REARRANGEMENT USING A 3D SCENE REPRESENTATION

      
Application Number 18126900
Status Pending
Filing Date 2023-03-27
First Publication Date 2024-05-30
Owner NVIDIA Corporation (USA)
Inventor
  • Murali, Adithyavairavan
  • Mousavian, Arsalan
  • Eppner, Clemens
  • Fishman, Adam
  • Fox, Dieter

Abstract

One common robotic task is the rearrangement of physical objects situated in an environment. This typically involves a robot manipulator picking up a target object and placing the target object in some target location, such as a shelf, cabinet or cubby, and requires the skills of picking, placing and generating complex collision-free motions, oftentimes in a cluttered environment. The present disclosure provides collision detection for object rearrangement using a three-dimensional (3D) scene representation.

IPC Classes  ?

69.

SYSTEMS, METHODS, AND APPARATUSES FOR MAKING WRITES TO PERSISTENT MEMORY

      
Application Number 18424082
Status Pending
Filing Date 2024-01-26
First Publication Date 2024-05-30
Owner Nvidia Corporation (USA)
Inventor Glaser, Stephen David

Abstract

A method, computer program product, apparatus, and system are provided. Some embodiments may include transmitting a request to make one or more writes associated with an identification tag. The request may include the identification tag, the one or more writes, a first instruction to make the one or more writes to one of a plurality of persistence levels of a memory, and a second instruction to respond with at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory. Some embodiments may include receiving the at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

70.

MOTION VECTOR OPTIMIZATION FOR MULTIPLE REFRACTIVE AND REFLECTIVE INTERFACES

      
Application Number 18527770
Status Pending
Filing Date 2023-12-04
First Publication Date 2024-05-30
Owner Nvidia Corporation (USA)
Inventor
  • Kozlowski, Pawel
  • Aizenshtein, Maksim

Abstract

Systems and methods relate to the determination of accurate motion vectors, for rendering situations such as a noisy Monte Carlo integration where image object surfaces are at least partially translucent. To optimize the search for “real world” positions, this invention defines the background as first path vertices visible through multiple layers of refractive interfaces. To find matching world positions, the background is treated as a single layer morphing in a chaotic way, permitting the optimized algorithm to be executed only once. Further improving performance over the prior linear gradient descent, the present techniques can apply a cross function and numerical optimization, such as Newton's quadratic target or other convergence function, to locate pixels via a vector angle minimization. Determined motion vectors can then serve as input for services including image denoising.

IPC Classes  ?

  • G06T 15/00 - 3D [Three Dimensional] image rendering
  • G06T 5/70 - Denoising; Smoothing
  • G06T 7/20 - Analysis of motion
  • G06T 7/70 - Determining position or orientation of objects or cameras

71.

MACHINE LEARNING FOR MASK OPTIMIZATION IN INVERSE LITHOGRAPHY TECHNOLOGIES

      
Application Number 18232757
Status Pending
Filing Date 2023-08-10
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Yang, Haoyu
  • Ren, Haoxing

Abstract

In the semiconductor industry, lithography refers to a manufacturing process in which light is projected through a geometric design on a mask to illuminate the design on a semiconductor wafer. The wafer has a light-sensitive material (i.e. resist) on its surface which, when illuminated by the light, causes the design to be etched onto the wafer. However, this lithography process does not perfectly transfer the design to the wafer, particularly because some diffracted light will inevitably distort the pattern etched onto the wafer (i.e. the resist image). To address this issue in lithography, an inverse lithography technology has been developed which optimizes the mask to match the desired shapes on the wafer. The present disclosure improves current inverse lithography technology by employing machine learning for mask optimization.

IPC Classes  ?

  • G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
  • G06T 7/00 - Image analysis

72.

METHOD FOR FORWARD PROGRESS AND PROGRAMMABLE TIMEOUTS OF TREE TRAVERSAL MECHANISMS IN HARDWARE

      
Application Number 18420449
Status Pending
Filing Date 2024-01-23
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Muthler, Greg
  • Babich, Jr., Ronald Charles
  • Newhall, Jr., William Parsons
  • Nelson, Peter
  • Robertson, James
  • Burgess, John

Abstract

In a ray tracer, to prevent any long-running query from hanging the graphics processing unit, a traversal coprocessor provides a preemption mechanism that will allow rays to stop processing or time out early. The example non-limiting implementations described herein provide such a preemption mechanism, including a forward progress guarantee, and additional programmable timeout options that can be time or cycle based. Those programmable options provide a means for quality of service timing guarantees for applications such as virtual reality (VR) that have strict timing requirements.

IPC Classes  ?

  • G06T 15/06 - Ray-tracing
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06N 5/046 - Forward inferencing; Production systems
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06T 1/60 - Memory management
  • G06T 17/00 - 3D modelling for computer graphics

73.

GENERATING NEURAL NETWORKS

      
Application Number 17990498
Status Pending
Filing Date 2022-11-18
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Yang, Dong
  • He, Yufan
  • Xu, Ziyue
  • Hatamizadeh, Ali
  • Nath, Vishwesh
  • Li, Wenqi
  • Myronenko, Andriy
  • Zhao, Can
  • Roth, Holger Reinhard
  • Xu, Daguang

Abstract

Apparatuses, systems, and techniques to generate one or more neural networks. In at least one embodiment, one or more neural networks are generated, based on, for example, one or more convolutional neural network operations and one or more transformer neural network operations.

IPC Classes  ?

  • G06N 3/04 - Architecture, e.g. interconnection topology

74.

DIRECTED INFERENCING USING INPUT DATA TRANSFORMATIONS

      
Application Number 17990508
Status Pending
Filing Date 2022-11-18
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor Dwivedi, Shekhar

Abstract

Apparatuses, systems, and techniques to segment a region of interest in an input data for a machine learning model by obtaining a plurality of progressively compressed representations of the input data and processing at least two of the compressed representations to obtain matching locations of a region of interest of the input data.

IPC Classes  ?

  • G06V 10/26 - Segmentation of patterns in the image field; Cutting or merging of image elements to establish the pattern region, e.g. clustering-based techniques; Detection of occlusion
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining
  • G06V 10/774 - Generating sets of training patterns; Bootstrap methods, e.g. bagging or boosting

75.

APPLICATION PROGRAMMING INTERFACE TO SYNCHRONIZE MATRIX MULTIPLY-ACCUMULATE MEMORY TRANSACTIONS

      
Application Number 18072053
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Perelygin, Kyrylo
  • Tyrlik, Maciej
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atukuri, Balaji Krishna Yugandhar
  • Kulkarni, Rishkul
  • Kyriakopoulos, Konstantinos
  • Gornish, Edward H.
  • Berson, David Allan
  • Sathe, Bageshri
  • Player, James
  • Arora, Aman
  • Kaatz, Alan
  • Kerr, Andrew
  • Wu, Haicheng
  • Cecka, Cris
  • Thakkar, Vijay
  • Treichler, Sean
  • Choquette, Jack H.
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Addison, Cody
  • Bharambe, Girish Bhaskarrao

Abstract

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until matrix multiply-accumulate (MMA) memory transactions are performed.

IPC Classes  ?

  • G06F 17/16 - Matrix or vector computation
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

76.

APPLICATION PROGRAMMING INTERFACE TO PERFORM ASYNCHRONOUS DATA MOVEMENT

      
Application Number 18081534
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to facilitate asynchronous data movement accounting. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more memory transactions to be performed without storing information about the one or more memory transactions.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

77.

APPLICATION PROGRAMMING INTERFACE TO STORE MEMORY TRANSACTION INFORMATION

      
Application Number 18081537
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to store memory transaction information. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information received by the API about one or more memory transactions to be stored.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt

78.

APPLICATION PROGRAMMING INTERFACE TO INDICATE MEMORY TRANSACTION

      
Application Number 18081559
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to create one or more memory transaction software objects. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more software objects to indicate whether one or more memory transactions have been performed.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

79.

APPLICATION PROGRAMMING INTERFACE TO TRANSFORM AND STORE INFORMATION CORRESPONDING TO A MEMORY TRANSACTION

      
Application Number 18086429
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Li, Chao
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to transform and store information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed and stored.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

80.

APPLICATION PROGRAMMING INTERFACE TO GENERATE A TENSOR MAPPING

      
Application Number 18086451
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Mehta, Vishalkumar Ketankumar
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to generate a tensor mapping. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a mapping from a first tensor to a second tensor to be generated.

IPC Classes  ?

81.

STORAGE OF TRANSFORMED TENSOR IN A CACHE

      
Application Number 18086484
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be transformed and stored into one or more GPU caches.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

82.

APPLICATION PROGRAMMING INTERFACE TO PERFORM ASYNCHRONOUS DATA MOVEMENT

      
Application Number CN2022132533
Publication Number 2024/103338
Status In Force
Filing Date 2022-11-17
Publication Date 2024-05-23
Owner NVIDIA CORPORATION (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoory
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to facilitate asynchronous data movement accounting. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause one or more memory transactions to be performed without storing information about the one or more memory transactions.

IPC Classes  ?

  • G06F 9/44 - Arrangements for executing specific programs

83.

MANAGING COMPOSABLE INFRASTRUCTURE WITHIN A COMPUTING ENVIRONMENT

      
Application Number 17991542
Status Pending
Filing Date 2022-11-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor Bahirat, Shirish

Abstract

Apparatuses, systems, and techniques to select action(s) predicted to modify at least one current state of a computing system using values of at least one parameter, values of at least one system objective, and at least one desired state of the computing system defined at least in part by the at least one system objective, and provide the action(s) to an application that implements the action(s) with respect to the computing system.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]

84.

WIRELESS SIGNAL TIMING WINDOW ADJUSTMENT

      
Application Number 17991622
Status Pending
Filing Date 2022-11-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor Martin, Timothy James

Abstract

Apparatuses, systems, and techniques are described herein to help adjust one or more timing windows of a base station to receive wireless signals. In at least one embodiment, one or more user equipment (UE) devices transmits one or more fifth generation new radio (“5G NR”) signals to a base station. In at least one embodiment, one or more resources of said base station adjusts said one or more timing windows based, at least in part, on one or more previously received 5G NR signals.

IPC Classes  ?

85.

GRAPH MODIFICATION

      
Application Number 17991657
Status Pending
Filing Date 2022-11-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Fontaine, David
  • Hoffman, Houston Thompson
  • Zulfiqar, Arslan
  • Jones, Stephen
  • Dinan, James
  • Kraus, Jiri Johannes

Abstract

Apparatuses, systems, and techniques to modify graphs. In at least one embodiment, a processor comprises one or more circuits to modify an execution order of at least one graph portion.

IPC Classes  ?

  • G06F 9/48 - Program initiating; Program switching, e.g. by interrupt
  • G06F 8/41 - Compilation

86.

APPLICATION PROGRAMMING INTERFACE TO INDICATE MATRIX MULTIPLY-ACCUMULATE

      
Application Number 18072060
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Perelygin, Kyrylo
  • Tyrlik, Maciej
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atukuri, Balaji Krishna Yugandhar
  • Kulkarni, Rishkul
  • Kyriakopoulos, Konstantinos
  • Gornish, Edward H.
  • Berson, David Allan
  • Sathe, Bageshri
  • Player, James
  • Arora, Aman
  • Kaatz, Alan
  • Kerr, Andrew
  • Wu, Haicheng
  • Cecka, Cris
  • Thakkar, Vijay
  • Treichler, Sean
  • Choquette, Jack H.
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Addison, Cody
  • Bharambe, Girish Bhaskarrao

Abstract

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to indicate whether matrix multiply-accumulate (MMA) memory operations are complete.

IPC Classes  ?

87.

APPLICATION PROGRAMMING INTERFACE TO WAIT ON MATRIX MULTIPLY-ACCUMULATE

      
Application Number 18072081
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Perelygin, Kyrylo
  • Tyrlik, Maciej
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atukuri, Balaji Krishna Yugandhar
  • Kulkarni, Rishkul
  • Kyriakopoulos, Konstantinos
  • Gornish, Edward H.
  • Berson, David Allan
  • Sathe, Bageshri
  • Player, James
  • Arora, Aman
  • Kaatz, Alan
  • Kerr, Andrew
  • Wu, Haicheng
  • Cecka, Cris
  • Thakkar, Vijay
  • Treichler, Sean
  • Choquette, Jack H.
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Addison, Cody
  • Bharambe, Girish Bhaskarrao

Abstract

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 17/16 - Matrix or vector computation

88.

APPLICATION PROGRAMMING INTERFACE TO INDICATE OPERATIONS TO BE PERFORMED BY CORRESPONDING STREAMING MULTIPROCESSORS

      
Application Number 18072300
Status Pending
Filing Date 2022-11-30
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Perelygin, Kyrylo
  • Tyrlik, Maciej
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atukuri, Balaji Krishna Yugandhar
  • Kulkarni, Rishkul
  • Kyriakopoulos, Konstantinos
  • Gornish, Edward H.
  • Berson, David Allan
  • Sathe, Bageshri
  • Player, James
  • Arora, Aman
  • Kaatz, Alan
  • Kerr, Andrew
  • Wu, Haicheng
  • Cecka, Cris
  • Thakkar, Vijay
  • Treichler, Sean
  • Choquette, Jack H.
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Addison, Cody
  • Bharambe, Girish Bhaskarrao

Abstract

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause two or more other computational operations to be performed by two or more streaming multiprocessors (SMs).

IPC Classes  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 17/16 - Matrix or vector computation

89.

APPLICATION PROGRAMMING INTERFACE TO PERFORM DELAYED MEMORY TRANSACTION INFORMATION CHECK

      
Application Number 18081552
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to perform delayed memory transaction information check. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to check for information provided by one or more users about one or more memory transactions after a timeout event indicated by one or more users.

IPC Classes  ?

  • G06F 9/46 - Multiprogramming arrangements
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/54 - Interprogram communication

90.

APPLICATION PROGRAMMING INTERFACE TO PROVIDE INFORMATION

      
Application Number 18081561
Status Pending
Filing Date 2022-12-14
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Giroux, Olivier
  • Choquette, Jack H.
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Guo, Rui
  • Li, Chao
  • Mehta, Vishalkumar Ketankumar
  • Dastous St. Hilaire, David
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Chakraborty, Subhasmita
  • Dhar, Vikram

Abstract

Apparatuses, systems, and techniques to cause information to be provided. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause an amount of information to be accessed as a result of one or more memory transactions to be provided to one or more users.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

91.

APPLICATION PROGRAMMING INTERFACE TO TRANSFORM INFORMATION CORRESPONDING TO A MEMORY TRANSACTION

      
Application Number 18086433
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Li, Chao
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to transform information corresponding to one or more memory transactions. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information corresponding to one or more memory transactions resulting from performance of the API to be transformed.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06F 9/54 - Interprogram communication
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

92.

APPLICATION PROGRAMMING INTERFACE TO STORE INFORMATION IN A PLURALITY OF STORAGE LOCATIONS

      
Application Number 18086442
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Mehta, Vishalkumar Ketankumar
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Li, Chao
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to store information in a plurality of storage locations allocated to a graphics processing unit (GPU). In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause information to be stored in a plurality of storage locations allocated to a first GPU.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06F 9/54 - Interprogram communication
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

93.

APPLICATION PROGRAMMING INTERFACE TO INDICATE STORAGE LOCATIONS

      
Application Number 18086461
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to indicate storage locations of information to be mapped from a first tensor to a second tensor. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to indicate one or more storage locations of information to be mapped from a first tensor to a second tensor.

IPC Classes  ?

94.

APPLICATION PROGRAMMING INTERFACE TO TRANSLATE A TENSOR ACCORDING TO A TENSOR MAP

      
Application Number 18086473
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Li, Chao
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to cause a first tensor to be translated into a second tensor according to a tensor map. In at least one embodiment, one or more circuits are to perform an application programming interface (API) to cause a first tensor to be translated into a second tensor according to a tensor map.

IPC Classes  ?

95.

STORAGE OF INFORMATION IN A GRAPHICS PROCESSING UNIT CACHE

      
Application Number 18086476
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to perform a graphics processing unit (GPU) prefetch instruction to cause a variable amount of information to be stored into one or more GPU caches. In at least one embodiment, one or more circuits of a GPU are to perform a GPU prefetch instruction to cause a variable amount of information to be stored into one or more GPU caches.

IPC Classes  ?

  • G06T 1/60 - Memory management
  • G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
  • G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

96.

STORAGE OF TENSOR IN A CACHE

      
Application Number 18086478
Status Pending
Filing Date 2022-12-21
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Edwards, Harold Carter
  • Jones, Stephen Anthony Bernard
  • Minkin, Alexander Lev
  • Giroux, Olivier
  • Hirisave Chandra Shekhara, Gokul Ramaswamy
  • Atluri, Aditya Avinash
  • Parle, Apoorv
  • Krashinsky, Ronny Meir
  • Kaatz, Alan
  • Kerr, Andrew Robert
  • Choquette, Jack H.

Abstract

Apparatuses, systems, and techniques to perform a tensor prefetch instruction to cause one or more tensors to be stored into one or more caches. In at least one embodiment, one or more circuits of a GPU are to perform a tensor prefetch instruction to cause one or more tensors to be stored into one or more GPU caches.

IPC Classes  ?

  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode

97.

HIGH-RESOLUTION VIDEO GENERATION USING IMAGE DIFFUSION MODELS

      
Application Number 18181729
Status Pending
Filing Date 2023-03-10
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Kreis, Karsten Julian
  • Rombach, Robin
  • Blattmann, Andreas
  • Kim, Seung Wook
  • Ling, Huan
  • Fidler, Sanja
  • Dockhorn, Tim

Abstract

In various examples, systems and methods are disclosed relating to aligning images into frames of a first video using at least one first temporal attention layer of a neural network model. The first video has a first spatial resolution. A second video having a second spatial resolution is generated by up-sampling the first video using at least one second temporal attention layer of an up-sampler neural network model, wherein the second spatial resolution is higher than the first spatial resolution.

IPC Classes  ?

  • H04N 21/2343 - Processing of video elementary streams, e.g. splicing of video streams or manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
  • G06T 9/00 - Image coding
  • G06V 10/24 - Aligning, centring, orientation detection or correction of the image
  • G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • H04N 7/01 - Conversion of standards

98.

PHYSICS-GUIDED MOTION DIFFUSION MODEL

      
Application Number 18317378
Status Pending
Filing Date 2023-05-15
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Yuan, Ye
  • Song, Jiaming
  • Iqbal, Umar
  • Vahdat, Arash
  • Kautz, Jan

Abstract

Systems and methods are disclosed that improve performance of synthesized motion generated by a diffusion neural network model. A physics-guided motion diffusion model incorporates physical constraints into the diffusion process to model the complex dynamics induced by forces and contact. Specifically, a physics-based motion projection module uses motion imitation in a physics simulator to project the denoised motion of a diffusion step to a physically plausible motion. The projected motion is further used in the next diffusion iteration to guide the denoising diffusion process. The use of physical constraints in the physics-guided motion diffusion model iteratively pulls the motion toward a physically-plausible space, reducing artifacts such as floating, foot sliding, and ground penetration.

IPC Classes  ?

  • G06T 13/40 - 3D [Three Dimensional] animation of characters, e.g. humans, animals or virtual beings
  • G06T 5/00 - Image enhancement or restoration
  • G06T 13/80 - 2D animation, e.g. using sprites

99.

CLASS AGNOSTIC OBJECT MASK GENERATION

      
Application Number 18355856
Status Pending
Filing Date 2023-07-20
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Lan, Shiyi
  • Yu, Zhiding
  • Radhakrishnan, Subhashree
  • Alvarez Lopez, Jose Manuel
  • Anandkumar, Animashree

Abstract

Class agnostic object mask generation uses a vision transformer-based auto-labeling framework requiring only images and object bounding boxes to generate object (segmentation) masks. The generated object masks, images, and object labels may then be used to train instance segmentation models or other neural networks to localize and segment objects with pixel-level accuracy. The generated object masks may supplement or replace conventional human generated annotations. The human generated annotations may be misaligned compared with the object boundaries, resulting in poor quality labeled segmentation masks. In contrast with conventional techniques, the generated object masks are class agnostic and are automatically generated based only on a bounding box image region without relying on either labels or semantic information.

IPC Classes  ?

  • G06T 7/11 - Region-based segmentation
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining

100.

OBJECT DETECTION USING SKEWED POLYGONS SUITABLE FOR PARKING SPACE DETECTION

      
Application Number 18424219
Status Pending
Filing Date 2024-01-26
First Publication Date 2024-05-23
Owner NVIDIA Corporation (USA)
Inventor
  • Lee, Dongwoo
  • Kwon, Junghyun
  • Oh, Sangmin
  • Zheng, Wenchao
  • Seo, Hae-Jong
  • Nister, David
  • Rodriguez Hervas, Berta

Abstract

A neural network may be used to determine corner points of a skewed polygon (e.g., as displacement values to anchor box corner points) that accurately delineate a region in an image that defines a parking space. Further, the neural network may output confidence values predicting likelihoods that corner points of an anchor box correspond to an entrance to the parking spot. The confidence values may be used to select a subset of the corner points of the anchor box and/or skewed polygon in order to define the entrance to the parking spot. A minimum aggregate distance between corner points of a skewed polygon predicted using the CNN(s) and ground truth corner points of a parking spot may be used simplify a determination as to whether an anchor box should be used as a positive sample for training.

IPC Classes  ?

  • G06T 7/13 - Edge detection
  • G06T 7/40 - Analysis of texture
  • G06T 17/30 - Surface description, e.g. polynomial surface description
  • G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersections; Connectivity analysis, e.g. of connected components
  • G06V 10/75 - Image or video pattern matching; Proximity measures in feature spaces using context analysis; Selection of dictionaries
  • G06V 10/772 - Determining representative reference patterns, e.g. averaging or distorting patterns; Generating dictionaries
  • G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
  • G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestrians; Recognition of traffic objects, e.g. traffic signs, traffic lights or roads
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