2014
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Invention
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Ct-nor differential bitline sensing architecture. Providing for a non-volatile semiconductor memo... |
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Invention
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Gate formation memory by planarization. Semiconductor devices and methods of producing the device... |
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G/S
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Semiconductors; integrated circuits; microcontrollers; applications software, utility software, a... |
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Invention
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Three-dimensional charge trapping nand cell with discrete charge trapping film. A three-dimension... |
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G/S
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Non-volatile memory devices, namely, flash memory semiconductor chips and mass storage semiconduc... |
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G/S
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Volatile memory devices, namely, random-access memory semiconductor chips; applications and utili... |
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G/S
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Interfaces for high-speed throughput of data between a processor or microcontroller and other sem... |
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Invention
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Method of depositing copper using physical vapor deposition.
The present method of forming an el... |
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Invention
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Programmable latency count to achieve higher memory bandwidth. Disclosed herein are system, metho... |
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Invention
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Methods, circuits, devices and systems for comparing signals.
Disclosed is a method of comparing... |
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Invention
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Charge-trap nor with silicon-rich nitride as a charge trap layer. A charge-trapping NOR (CT-NOR) ... |
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Invention
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Die seal layout for dual damascene in a semiconductor device. A semiconductor may include several... |
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Invention
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Restoring ecc syndrome in non-volatile memory devices. A method of restoring an ECC syndrome in a... |
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Invention
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Semiconductor memory device.
Based on a continuous erase start signal outputted, in response to ... |
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Invention
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Authentication for recognition systems. Embodiments include a method, apparatus, and computer pro... |
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Invention
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Combining of results from multiple decoders. Embodiments include a method, apparatus, and a compu... |
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Invention
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Modified local segmented self-boosting of memory cell channels. A method of programming a memory ... |
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Invention
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Erase verification. Embodiments described herein generally relate to verifying that a FLASH memor... |
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Invention
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Contact configuration for undertaking tests on circuit board. An electronic structure (for exampl... |
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Invention
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Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their ... |
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Invention
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Semiconductor device and erasing method thereof. [Problem] To provide a semiconductor storage dev... |
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Invention
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Pipelining in a memory. A system including a memory cell array including a plurality of memory ce... |
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Invention
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Non-volatile memory based system ram. A memory module includes an input/output (I/O) interface ad... |
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Invention
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Apparatus and method to reduce bit line disturbs. A non-volatile memory device comprising a memor... |
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Invention
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Memory device with source-side sensing. A source-sensing configuration for non-volatile memory de... |
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G/S
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Interfaces for high speed throughput of data between a processor or microcontroller and other sem... |
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Invention
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Improved non-volatile memory device. A non-volatile memory device includes a memory cell array ha... |
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Invention
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Non-volatile memory with silicided bit line contacts. An approach to use silicided bit line conta... |
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Invention
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Manufacturing of fet devices having lightly doped drain and source regions. Embodiments described... |
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Invention
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Programmable and flexible reference cell selection method for memory devices. Systems, methods, a... |
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Invention
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Distributed speech recognition system. Embodiments of the present invention include an apparatus,... |
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Invention
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Multi-chip package assembly with improved bond wire separation. A multi-chip package is disclosed... |
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Invention
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Buried hard mask for embedded semiconductor device patterning. Methods and apparatus for manufact... |
2013
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Invention
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Design for test (dft) read speed through transition detector in built-in self-test (bist) sort. A... |
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Invention
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Phoneme score accelerator. Embodiments of the present invention include an acoustic processing de... |
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Invention
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Memory device with internal data processing logic. Embodiments of the present invention include a... |
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Invention
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Histogram based pre-pruning scheme for active hmms. Embodiments of the present invention include ... |
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Invention
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Hybrid hashing scheme for active hmms. Embodiments of the present invention include a data storag... |
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Invention
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High voltage gate formation. Embodiments described herein generally relate to methods of manufact... |
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Invention
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Charge trapping device with improved select gate to memory gate isolation. Embodiments described ... |
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Invention
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Memory gate landing pad made from dummy features. Embodiments described herein generally relate t... |
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Invention
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Use disposable gate cap to form transistors, and split gate charge trapping memory cells. A semic... |
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Invention
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Charge trapping split gate device and method of fabricating same. Embodiments provide a split gat... |
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Invention
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Three dimensional capacitor. Integrated capacitor structures and methods for fabricating same are... |
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Invention
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Process charging protection for split gate charge trapping flash. A semiconductor device and meth... |
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Invention
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Memory first process flow and device. Semiconductor devices and methods of manufacturing such dev... |
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Invention
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Charge trapping split gate embedded flash memory and associated methods. Semiconductor devices an... |
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Invention
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Integrated circuits with non-volatile memory and methods for manufacture. Semiconductor devices a... |
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Invention
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Forming a substantially uniform wing height among elements in a charge trap semiconductor device.... |
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Invention
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Inter-layer insulator for electronic devices and apparatus for forming same. A semiconducting dev... |
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Invention
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Apparatus and method for smart vcc trip point design for testability. An apparatus and method for... |
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Invention
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Reflecting parabolic splice solar smelter. A revolution-of-a-parabolic-curve is sliced by two pla... |
2012
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Invention
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Chip positioning in multi-chip package. Embodiments of the present invention include a substrate ... |
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G/S
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[ Computer programs featuring simulation and behavioral modeling functions for use in power circu... |
2007
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G/S
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Non-volatile semiconductor memory devices, and operating, application and utility software associ... |
2006
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G/S
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Non-volatile semiconductor memory devices, namely, flash memory, and operating, application and u... |
2005
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Invention
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Method for manufacturing a contact for a semiconductor component and related structure. A semicon... |
2003
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G/S
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Primarily volatile and non-volatile memory devices, and computer software associated therewith. C... |
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G/S
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Volatile and non-volatile memory devices, namely, flash memory semiconductor chips and mass stora... |
2001
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G/S
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Primarily volatile and non-volatile memory devices, and computer software associated therewith. |
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G/S
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Volatile and non-volatile semiconductor memory devices, and operating, application and utility so... |