Spansion LLC

United States of America


 
Total IP 443
Total IP incl. subs 443 (+ 0 for subs)
Total IP Rank # 2,831
IP Activity Score 0/5.0    0
IP Activity Rank # 1,598,975
Parent Entity Cypress Semiconductor Corporation
Dominant Nice Class Scientific and electric apparatu...

Patents

Trademarks

90 9
0 1
335 0
8
 
Last Patent 2015 - Method for manufacturing a conta...
First Patent 1995 - Control system for charging batt...
Last Trademark 2014 - TRAVEO
First Trademark 2001 - MIRRORBIT

Subsidiaries

1 subsidiaries with IP (0 patents, 0 trademarks)

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Industry (Nice Classification)

Latest Inventions, Goods, Services

2014 Invention Ct-nor differential bitline sensing architecture. Providing for a non-volatile semiconductor memo...
Invention Gate formation memory by planarization. Semiconductor devices and methods of producing the device...
G/S Semiconductors; integrated circuits; microcontrollers; applications software, utility software, a...
Invention Three-dimensional charge trapping nand cell with discrete charge trapping film. A three-dimension...
G/S Non-volatile memory devices, namely, flash memory semiconductor chips and mass storage semiconduc...
G/S Volatile memory devices, namely, random-access memory semiconductor chips; applications and utili...
G/S Interfaces for high-speed throughput of data between a processor or microcontroller and other sem...
Invention Method of depositing copper using physical vapor deposition. The present method of forming an el...
Invention Programmable latency count to achieve higher memory bandwidth. Disclosed herein are system, metho...
Invention Methods, circuits, devices and systems for comparing signals. Disclosed is a method of comparing...
Invention Charge-trap nor with silicon-rich nitride as a charge trap layer. A charge-trapping NOR (CT-NOR) ...
Invention Die seal layout for dual damascene in a semiconductor device. A semiconductor may include several...
Invention Restoring ecc syndrome in non-volatile memory devices. A method of restoring an ECC syndrome in a...
Invention Semiconductor memory device. Based on a continuous erase start signal outputted, in response to ...
Invention Authentication for recognition systems. Embodiments include a method, apparatus, and computer pro...
Invention Combining of results from multiple decoders. Embodiments include a method, apparatus, and a compu...
Invention Modified local segmented self-boosting of memory cell channels. A method of programming a memory ...
Invention Erase verification. Embodiments described herein generally relate to verifying that a FLASH memor...
Invention Contact configuration for undertaking tests on circuit board. An electronic structure (for exampl...
Invention Switchable memory diodes based on ferroelectric/conuugated polymer heterostructures and/or their ...
Invention Semiconductor device and erasing method thereof. [Problem] To provide a semiconductor storage dev...
Invention Pipelining in a memory. A system including a memory cell array including a plurality of memory ce...
Invention Non-volatile memory based system ram. A memory module includes an input/output (I/O) interface ad...
Invention Apparatus and method to reduce bit line disturbs. A non-volatile memory device comprising a memor...
Invention Memory device with source-side sensing. A source-sensing configuration for non-volatile memory de...
G/S Interfaces for high speed throughput of data between a processor or microcontroller and other sem...
Invention Improved non-volatile memory device. A non-volatile memory device includes a memory cell array ha...
Invention Non-volatile memory with silicided bit line contacts. An approach to use silicided bit line conta...
Invention Manufacturing of fet devices having lightly doped drain and source regions. Embodiments described...
Invention Programmable and flexible reference cell selection method for memory devices. Systems, methods, a...
Invention Distributed speech recognition system. Embodiments of the present invention include an apparatus,...
Invention Multi-chip package assembly with improved bond wire separation. A multi-chip package is disclosed...
Invention Buried hard mask for embedded semiconductor device patterning. Methods and apparatus for manufact...
2013 Invention Design for test (dft) read speed through transition detector in built-in self-test (bist) sort. A...
Invention Phoneme score accelerator. Embodiments of the present invention include an acoustic processing de...
Invention Memory device with internal data processing logic. Embodiments of the present invention include a...
Invention Histogram based pre-pruning scheme for active hmms. Embodiments of the present invention include ...
Invention Hybrid hashing scheme for active hmms. Embodiments of the present invention include a data storag...
Invention High voltage gate formation. Embodiments described herein generally relate to methods of manufact...
Invention Charge trapping device with improved select gate to memory gate isolation. Embodiments described ...
Invention Memory gate landing pad made from dummy features. Embodiments described herein generally relate t...
Invention Use disposable gate cap to form transistors, and split gate charge trapping memory cells. A semic...
Invention Charge trapping split gate device and method of fabricating same. Embodiments provide a split gat...
Invention Three dimensional capacitor. Integrated capacitor structures and methods for fabricating same are...
Invention Process charging protection for split gate charge trapping flash. A semiconductor device and meth...
Invention Memory first process flow and device. Semiconductor devices and methods of manufacturing such dev...
Invention Charge trapping split gate embedded flash memory and associated methods. Semiconductor devices an...
Invention Integrated circuits with non-volatile memory and methods for manufacture. Semiconductor devices a...
Invention Forming a substantially uniform wing height among elements in a charge trap semiconductor device....
Invention Inter-layer insulator for electronic devices and apparatus for forming same. A semiconducting dev...
Invention Apparatus and method for smart vcc trip point design for testability. An apparatus and method for...
Invention Reflecting parabolic splice solar smelter. A revolution-of-a-parabolic-curve is sliced by two pla...
2012 Invention Chip positioning in multi-chip package. Embodiments of the present invention include a substrate ...
G/S [ Computer programs featuring simulation and behavioral modeling functions for use in power circu...
2007 G/S Non-volatile semiconductor memory devices, and operating, application and utility software associ...
2006 G/S Non-volatile semiconductor memory devices, namely, flash memory, and operating, application and u...
2005 Invention Method for manufacturing a contact for a semiconductor component and related structure. A semicon...
2003 G/S Primarily volatile and non-volatile memory devices, and computer software associated therewith. C...
G/S Volatile and non-volatile memory devices, namely, flash memory semiconductor chips and mass stora...
2001 G/S Primarily volatile and non-volatile memory devices, and computer software associated therewith.
G/S Volatile and non-volatile semiconductor memory devices, and operating, application and utility so...