Registre Brevet USPTO
Numéro d'application 17342397
Statut En instance
Date de dépôt 2021-06-08
Date de la première publication 2023-01-19
Date de publication 2023-01-19
Propriétaire Intel Corporation (USA)
  • Whitcombe, Amy
  • Carlton, Brent


A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.

Classes IPC  ?

  • G04F 10/00 - Apparatus for measuring unknown time intervals by electric means
  • H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
  • G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit