PERFORMING GLOBAL MEMORY ATOMICS IN A PRIVATE CACHE OF A SUB-CORE OF A GRAPHICS PROCESSING UNIT

Registre Brevet USPTO
Numéro d'application 17379121
Statut En instance
Date de dépôt 2021-07-19
Date de la première publication 2023-01-26
Date de publication 2023-01-26
Propriétaire Intel Corporation (USA)
Inventeur(s)
  • Ray, Joydeep
  • Shinde, Prathamesh Raghunath
  • Qi, Yue
  • Appu, Abhishek R.
  • Tian, Xinmin
  • Ranganathan, Vasanth
  • Ashbaugh, Ben J.

Abrégé

Embodiments are directed to systems and methods for performing global memory atomics in a private cache of a sub-core of a GPU. An embodiment of a GPU includes multiple sub-cores each including a load/store pipeline. The load/store pipeline is operable to receive information specifying an atomic operation to be performed within a primary data cache of the load/store pipeline. The load/store pipeline is also operable to read data to be modified by the atomic operation into the primary data cache from a memory hierarchy shared by the multiple sub-cores. The load/store pipeline is further operable to produce an atomic result of the atomic operation by modifying the data within the primary data cache based on the atomic operation.

Classes IPC  ?

  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode