Registre Brevet USPTO
Numéro d'application 17448604
Statut En instance
Date de dépôt 2021-09-23
Date de la première publication 2023-03-23
Date de publication 2023-03-23
Propriétaire Intel Corporation (USA)
  • Zhang, Yongmei
  • Hilewitz, Yedidya
  • Liu, Yen-Cheng


In an embodiment, a processor may include an execution engine to execute a plurality of instructions, a memory to store a tagged data structure comprising a plurality of entries, and an eviction circuit. The eviction circuit may be to: generate a pseudo-random number responsive to an eviction request for the tagged data structure; in response to a determination that the pseudo-random number is outside of a valid eviction range for the plurality of entries, generate an alternative identifier by rotating through the valid eviction range, the valid eviction range comprising a range of numbers that are valid to identify victim entries of the tagged data structure; and evict a victim entry from the tagged data structure, the victim entry associated with the alternative identifier. Other embodiments are described and claimed.

Classes IPC  ?

  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F 7/58 - Random or pseudo-random number generators