SCALABLE EOS AND AGING TOLERANT LEVEL SHIFTER FOR A HIGH VOLTAGE DESIGN FOR THIN GATE TECHNOLOGY
| Registre | Brevet USPTO |
|---|---|
| Numéro d'application | 17482912 |
| Statut | En instance |
| Date de dépôt | 2021-09-23 |
| Date de la première publication | 2023-03-23 |
| Date de publication | 2023-03-23 |
| Propriétaire | Intel Corporation (USA) |
| Inventeur(s) |
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Abrégé
A level shifter circuit, comprising one or more thin gate transistors having source and drain terminals coupled, respectively, to a power supply node and a reference node, where the one or more thin gate transistors have an electrical over stress (EOS) threshold voltage that is lower than a voltage of the power supply applied across two terminals of the one or more thin gate transistors. The circuit further includes a PFET pulldown circuit coupled to an EOS protection circuit to limit the voltage difference across at least two terminals of the one or more thin gate transistors to a voltage below the EOS threshold voltage based on the threshold voltage the PFET.Classes IPC ?
- H03K 19/0185 - Coupling arrangements; Interface arrangements using field-effect transistors only