System, Apparatus And Method For Synchronizing Multiple Virtual Link States Over A Package Interconnect
|Date de dépôt||2022-08-12|
|Date de la première publication||2023-01-26|
|Date de publication||2023-01-26|
|Propriétaire||Intel Corporation (USA)|
AbrégéIn one embodiment, an apparatus includes an arbitration circuit with virtual link state machines to virtualize link states associated with multiple communication protocol stacks. The apparatus further includes a physical circuit coupled to the arbitration circuit and to interface with a physical link, where the physical circuit, in response to a retraining of the physical link, is to cause a plurality of the virtual link state machines to synchronize with corresponding virtual link state machines associated with a second side of the physical link, and where at least one of the communication protocol stacks is to remain in a low power state during the retraining and the synchronization. Other embodiments are described and claimed.
Classes IPC ?
- G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
- G06F 13/40 - Bus structure
- G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation