Registre Brevet USPTO
Numéro d'application 17849201
Statut En instance
Date de dépôt 2022-06-24
Date de la première publication 2023-01-19
Date de publication 2023-01-19
Propriétaire Intel Corporation (USA)
  • Ray, Joydeep
  • Koker, Altug
  • George, Varghese
  • Macpherson, Mike
  • Anantaraman, Aravindh
  • Appu, Abhishek R.
  • Ould-Ahmed-Vall, Elmoustapha
  • Galoppo Von Borries, Nicolas
  • Ashbaugh, Ben J.


Embodiments described herein provide techniques to facilitate instruction-based control of memory attributes. One embodiment provides a graphics processor comprising a processing resource, a memory device, a cache coupled with the processing resources and the memory, and circuitry to process a memory access message received from the processing resource. The memory access message enables access to data of the memory device. To process the memory access message, the circuitry is configured to determine one or more cache attributes that indicate whether the data should be read from or stored the cache. The cache attributes may be provided by the memory access message or stored in state data associated with the data to be accessed by the access message.

Classes IPC  ?

  • G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
  • G06T 1/60 - Memory management
  • G06T 1/20 - Processor architectures; Processor configuration, e.g. pipelining