SCALAR CORE INTEGRATION

Registre Brevet USPTO
Numéro d'application 17868448
Statut En instance
Date de dépôt 2022-07-19
Date de la première publication 2023-01-26
Date de publication 2023-01-26
Propriétaire Intel Corporation (USA)
Inventeur(s)
  • Ray, Joydeep
  • Anantaraman, Aravindh
  • Appu, Abhishek R.
  • Koker, Altug
  • Ould-Ahmed-Vall, Elmoustapha
  • Andrei, Valentin
  • Maiyuran, Subramaniam
  • Galoppo Von Borries, Nicolas
  • George, Varghese
  • Macpherson, Mike
  • Ashbaugh, Ben
  • Ramadoss, Murali
  • Vemulapalli, Vikranth
  • Sadler, William
  • Pearce, Jonathan
  • Kim, Sungye

Abrégé

Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Classes IPC  ?

  • G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/38 - Concurrent instruction execution, e.g. pipeline, look ahead
  • G06T 15/00 - 3D [Three Dimensional] image rendering