SYSTEM, APPARATUS AND METHOD FOR FINE-GRAIN ADDRESS SPACE SELECTION IN A PROCESSOR

Registre Brevet USPTO
Numéro d'application 17891180
Statut En instance
Date de dépôt 2022-08-19
Date de la première publication 2023-01-26
Date de publication 2023-01-26
Propriétaire Intel Corporation (USA)
Inventeur(s)
  • Kakaiya, Utkarsh Y.
  • Sankaran, Rajesh
  • Neiger, Gilbert
  • Lantz, Philip
  • Kumar, Sanjay K.

Abrégé

In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

Classes IPC  ?

  • G06F 9/34 - Addressing or accessing the instruction operand or the result
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 12/109 - Address translation for multiple virtual address spaces, e.g. segmentation