UNIFIED ACCELERATOR FOR CLASSICAL AND POST-QUANTUM DIGITAL SIGNATURE SCHEMES IN COMPUTING ENVIRONMENTS

Registre Brevet USPTO
Numéro d'application 17934682
Statut En instance
Date de dépôt 2022-09-23
Date de la première publication 2023-01-19
Date de publication 2023-01-19
Propriétaire Intel Corporation (USA)
Inventeur(s)
  • Mathew, Sanu
  • Sastry, Manoj
  • Ghosh, Santosh
  • Suresh, Vikram
  • Reinders, Andrew H.
  • Kumar, Raghavan
  • Misoczki, Rafael

Abrégé

A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments, according to one embodiment. A method of embodiments, as described herein, includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

Classes IPC  ?

  • H04L 9/32 - Arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system
  • G06F 21/76 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
  • H04L 9/08 - Key distribution