Registre Brevet USPTO
Numéro d'application 17936862
Statut En instance
Date de dépôt 2022-09-30
Date de la première publication 2023-01-26
Date de publication 2023-01-26
Propriétaire Intel Corporation (USA)
Inventeur(s) Piwko, Maciej


An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to determine that a first composite link of a plurality of composite PCIe links terminating at the same PCIe root port lacks support for enabling a desired power saving state or an exit latency for the first composite link is above a first latency threshold. The processing circuitry is further configured to determine whether an exit latency for a second composite link of the plurality of composite PCIe links is below a second latency threshold and selectively trigger at least one sub-link of the second composite link to enable the desired power saving state if the exit latency for the second composite link is below the second latency threshold.

Classes IPC  ?

  • G06F 13/42 - Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F 1/3203 - Power management, i.e. event-based initiation of a power-saving mode