METHOD AND APPARATUS TO PERFORM TRAINING ON A DATA BUS BETWEEN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND A DATA BUFFER ON A BUFFERED DUAL IN-LINE MEMORY MODULE
|Date de dépôt||2022-09-22|
|Date de la première publication||2023-01-19|
|Date de publication||2023-01-19|
|Propriétaire||Intel Corporation (USA)|
AbrégéSystem boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.